ST has a broad offer to support designs in 28nm FD-SOI with a variety of key design block available to designers.

Standard cells
Standard cells are crucial elements, typically making up a large portion of any ASIC or SoC design. With a rich portfolio, ST’s FD-SOI standard cell libraries address requirements in multiple markets. We offer multiple channel length and VT options to cover a broad range of architectures, from low power to high performance. Learn more about the standard cells here.

ST’s embedded memory compilers offer best-in-class performance, power and area figure of merit and include patented well structures for ultra-low voltage operation. The broad offer, including high performance, low leakage and low voltage SRAMs, ROMs and special memories, suits a large variety of SoC design requirements. FD-SOI specific architecture allows an extremely low Soft Error Rate (below 10FIT/Mb) compared to other technologies, providing a very reliable platform.

The inputs/Output library provides a high programmability as well as flexibility in frame and row configuration. The library covers a supply range from 1.0 V to 3.3 V, with smaller footprint at 3.3V compared to competition. Thanks to compensation techniques, 20% of reduction of supply pads can be achieved compared to a standard implementation.

Data converters
The data convertor library includes high speed Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) with a high resolution feature up to 24-bit. Available for various applications, the data converters are customizable upon request.

Clock generators
ST’s clock generators offer best-in-class features, such as on-the-fly switching, multi-mode operation, automatic bandwidth tracking and very small PLLs. Addressing standard, spread-spectrum, fractional and high-performance architectures, the broad portfolio of clock generators  can match any design requirements.

Specific IP
To complement the standard cells libraries, ST offers a large choice of additional specific cells, such as a programmable body-bias generator, thermal and voltage sensors, regulators, an optimized OTP security cell and process monitoring sensors and controllers for silicon learning and yield enhancement.


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