意法半导体的SPC56 P和L器件属于SPC5系列32位Flash MCU,专门用于满足底盘与安全系统的特殊需求,特别注重功能安全性和高级三相电机控制。

架构独有的模块化和可升级性使得器件符合底盘和安全应用的要求,并且实现了最佳成本、安全性和性能。

ASIL-D compliant SPC56 L-line and SPC57 S-line Devices

The new SPC56 L-line (SPC56EL60 and SPC56EL70) and SPC57 S-line (SPC570S40 and SPC570S50) devices comply with the most stringent automotive safety standards (ISO 26262). Featuring an increased non-volatile memory size, these lines are designed so that customers using existing parts can migrate their platforms to these new devices very simply. These devices cover a wide range of automotive applications that need to respect the automotive safety integrity levels (ASIL) that are now required, up to and including the most stringent ASIL-D level.  ASIL-D classification is now commonplace in critical systems such as anti-lock braking, electric power steering, active suspension and advanced driver assistance systems (ADAS). The dual-core architecture of the L- and S-line devices reduces duplication of components at a system level, lowering overall system costs. Their architecture also provides unique flexibility by allowing the user to select lockstep or dual parallel processing (independent core operation) modes, enabling support of multiple safety architectures that the user can configure to achieve the required balance between safety and performance levels.  

These SPC56EL60 and SPC56EL70 devices are designed to cover a wide range of automotive applications that need to respect the automotive safety integrity levels (ASIL) that are now required, up to and including the most stringent ASIL-D level.  ASIL-D is now a commonplace in critical systems such as anti-lock braking, electric power steering, active suspension and advanced driver assistance systems (ADAS). 

The SPC56EL60L3, SPC56EL60L5 and SPC56EL70L5  devices combine:

  • Two high-performance e200z4d cores
  • 1 MB (SPC56EL60) or 2 MB (SPC56EL70) of Flash memory
  • 192 KB RAM  Flash memory
  • Three CAN interfaces
  • An optimized peripheral set for safety and motor-control applications, supporting up to two brushless 3-phase motors

The dual-core architecture reduces duplication of components at a system level, lowering overall system costs. The architecture also provides unique flexibility by allowing the user to select lockstep or dual parallel processing (independent core operation) modes, enabling support of multiple safety architectures that the user can configure to achieve the required balance between safety and performance level.

 

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