The SPEAr300 is a member of the SPEAr family of embedded MPUs for networked devices.
It is based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in applications where high computation performance is required.
In addition, SPEAr300 has an MMU that allows virtual memory management -- making the system compliant with Linux operating system. It also offers 16 KB of data cache, 16 KB of instruction cache, JTAG and ETM (embedded trace macro-cell) for debug operations.
A full set of peripherals allows the system to be used in many applications, some typical applications being HMI, Security and VoIP phones.
- SecurityC3 cryptographic accelerator
- Connectivity2 x USB 2.0 HostUSB 2.0 DeviceFast Ethernet (MII port)1x SSP Synchronous serial peripheral (SPI, Microwire or TI protocol)1x I2 C1x I2 S,1x fast IrDA interface1x UART interfaceTDM bus (512 timeslots)Up to 8 additional I2 C/SPI chip selects
- Miscellaneous functionsIntegrated real time clock, watchdog, and system controller8-channel 10-bit ADC, 1 Msps1-bit DACJPEG codec acceleratorSix 16-bit general purpose timers with capture mode and programmable prescalerUp to 62 GPIOs
- ARM926EJ-S core up to 333 MHz
- Dynamic power-saving features
- High-performance 8-channel DMA
- Memory32 KB ROM and 56 KB internal SRAMLPDDR-333/DDR2-666 external memory interface (up to 1 GB addressable memory)SDIO/MMC card interfaceSerial Flash memory interface (SMI)Flexible static memory controller (FSMC) up to 16-bit data bus width, supporting external SRAM, NAND/NOR Flash and FPGAsSerial SPI Flash interface
- Peripherals supportedCamera interface (ITU-601/656 and CSI2 support)TFT/STN LCD controller (resolution up to 1024 x 768 and up to 24 bpp)Touchscreen support (using the ADC)9 x 9 keyboard controllerGlueless management of up to 8 SLICs/CODECs
- Configurable peripheral functions on 102 shared I/Os