| Author | beginning argument ( Replies received: 2 ) |
| siksik |
 Posted 07-01-2004 at 11:14 |
Registered on :
01-07-2004
From Israel
Messages : 2
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Hi,
I want to connect an external ram to a upsd3333 using the pld for latching the address. i used the PA port for the low address bus.
1. Where should i connect the data-bus? to AD[0..7] or to a port?
2. Do i have to use the ALE signal? Can i leave it unconnected?
3. I need a RAM with 17 bit address. Can i use PB port for the high bits
of the address-bus :A[12..16]?
4.Do you have an application-note with a shema of a upsd3333 with
an external RAM?
Thanks,
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| uPSD |
 Posted 08-01-2004 at 00:31 |
Registered on :
12-10-2002
Messages : 281
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1. D7-D0 of external RAM should be connected to AD7-AD0 on the uPSD.
2. You can configure port A as "Latched Address Out", and connect PA7-PA0 to A7-A0 of the external RAM. Please see the attached picture. Connect mcu A11 - mcu A8 to ext. RAM A11-A8.
3. uPSD is 8032 based, a standard 8032 only has 16-bit address bus and can address up to 64K memory when memory paging is NOT used. To address beyond 64K, memory paging must be used. You can use PB3-PB0 and write PLD equations like the example shown in AN1560 (a15_x - a12_x) and connect them to A15 - A12 of your ext. RAM.
4. Sorry we do not have an app. note on this subject.
| Attachments : |  XRAM_addr.bmp | | | |
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| khtang |
 Posted 08-05-2008 at 08:38 |
Registered on :
05-02-2008
Messages : 1
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I am using uPSD3422 and I tried to map the PA and PB ports to latched address low and lateched address high as described without success. I do not get any expected address out.
My solution is to define these pins as Combinational logic output, then at the Design Assistant's I/O Logic Equation page I equate these pins to the corresponding adresses, i.e. pa7 = a7, pb7 = a15, etc. I also tie the Output enable pins of these pins to _reset. It seems to work.
Any idea or comment to my solution?
[ This message was edited by: khtang on 08-05-2008 08:40 ]
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external ram in upsd33xx
