AN1773 Application note
Conversion Guide, uPSD3300 to uPSD3400 series
1
Introduction
The uPSD family currently consists of three series, uPSD3200, uPSD3300, and uPSD3400. All three series are available in the same kind of packages (52-pin and 80-pin TQFP), but there are a few differences in pin definitions. This document describes these differences and suggests methods to easily migrate designs from the uPSD3300 series to uPSD3400. You can implement simple techniques on your printed circuit board to accept either a uPSD3300 or a uPSD3400 during manufacturing. Please see Application Note AN1724 for similar information regarding migrating designs from the uPSD3200 series to the uPSD3300 series, and Application Note AN1787 for migrating uPSD3200 designs to uPSD3400 designs. For simplicity, the uPSD3300 series will be referred in this document as 3300, and the uPSD3400 series will be referred to as 3400.
1.1
1.1.1
Summary of pin differences
USB
The 3300 does not support USB. The 3400 supports USB 2.0 Full-Speed (12Mbps).
1.1.2
52-pin devices
52-pin 3400 devices have only two pin differences from 52-pin 3300 devices. The USB+ and USB signals on the 3400 replace pins that are optional JTAG signals on the 3300.
1.1.3
80-pin devices
80-pin 3400 devices have five pin differences from 80-pin 3300 devices. There is a shift of pin definitions on three pins, and two pins that were formerly No-Connect (NC) on the 3300 are now used on the 3400.
1.2
Summary of new uPSD3400 Functions
Listed below are new functions on the 3400 that were not available on the 3300:
May 2007
Rev 2
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www.st.com
Introduction
AN1773
1.2.1
USB
The 3400 supports USB 2.0 Full-Speed (12Mbps) and includes the USB physical interface. There are a total of 5 pair of endpoints (each pair consists of In and Out). One endpoint pair is for USB Control transfer types, the remaining four endpoint pairs can be used for any combination of USB Interrupt or USB Bulk transfer types. Each individual endpoint has a 64byte FIFO (10 FIFOs total) to maintain USB data throughput.
1.2.2
MCU core
The 8032 MCU core of the 3400 operates on 4-clocks per instruction, with a maximum clock rate of 40MHz, yielding 10 MIPS (Million Instructions Per Second) maximum performance for single-byte instructions. This is the same as the 3300 series. However, the 3400 MCU core has a 16-bit internal path from memory to enhance performance, meaning that doublebyte instructions are fetched in a single MCU cycle, which pushes average performance close to the peak performance. No firmware changes are required to take advantage of this enhancement. In contrast the 8032 MCU core of the 3300 has an 8-bit path to memory requiring two MCU cycles to fetch a double-byte instruction. In summary, both the 3300 and the 3400 have 10 MIPS peak performance, but you can expect about 9 MIPS average performance from the 3400 and about 6 MIPS average performance from the 3300.
Note:
PSD functions have NOT changed from the 3300 to 3400. These functions include PLD, memory mapping, memory management (code space vs. data space, and paging), Flash memories, SRAM memory, and PSD I/O. Please note the SRAM on the 3400 can not be configured to reside in code space.
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Pin definitions
2
Pin definitions
Figure 1 and Figure 2 show pin assignments of the 3300 and 3400 devices in both 52-pin and 80-pin TQFP packages. Please see the 3300 and 3400 data sheets for detailed pin function descriptions and physical dimensions of packages. Pins affected by changes are darkened in the figures.
Figure 1.
uPSD3300 52-pin TQFP pin definition
41 P1.7/SPISEL_(2)/ADC7 40 P1.6/SPITXD(2)/ADC6
47 3.3V VCC/VREF(3)
44 RESET_IN_
45 GND
46 PB5
43 PB6
42 PB7
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3.3V VCC 6 PC4/TERR_ 7 VDD
(1)
39 P1.5/SPIRXD(2)/ADC5 38 P1.4/SPICLK(2)/ADC4 37 P1.3/TXD1(IrDA)(2)/ADC3 36 P1.2/RXD1(IrDA)(2)/ADC2 35 P1.1/T2X(2)/ADC1 34 P1.0/T2(2)/ADC0
8
uPSD33XX 52-pin TQFP
33 VDD(1) 32 XTAL2 31 XTAL1 30 P3.7/I2CSCL 29 P3.6/I2CSDA 28 P3.5/C1 27 P3.4/C0
GND 9 PC3/TSTAT 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13
SPISEL_(2)/PCACLK1/P4.7 14
15
16
SPICLK(2)/TCM3/P4.4 17
TXD1(IrDA)(2)/PCACLK0/P4.3 18
GND 19
RXD1(IrDA)(2)/TCM2/P4.2 20
21
22
RXD0/P3.0 23
TXD0/P3.1 24
EXTINT0/TG0/P3.2 25
SPIRXD(2)/TCM4/P4.5
SPITXD(2)/TCM5/P4.6
EXTINT1/TG1/P3.3 26
T2X(2)/TCM1/P4.1
T2(2)/TCM0/P4.0
AI08876
1. For 5V applications, VDD must be connected to 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port 1. 3. VREF and 3.3V VCC are shared. ADC channels must use 3.3V as VREF for 52-pin package.
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Pin definitions Figure 2. uPSD3400 52-pin TQFP pin definition
41 P1.7/SPISEL_(2)/ADC7 40 P1.6/SPITXD(2)/ADC6
AN1773
47 A VCC/VREF(3)
44 RESET_IN_
45 GND
46 PB5
43 PB6
42 PB7
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3.3V VCC 6 USB+ 7 VDD
(1)
39 P1.5/SPIRXD(2)/ADC5 38 P1.4/SPICLK(2)/ADC4 37 P1.3/TXD1(IrDA)(2)/ADC3 36 P1.2/RXD1(IrDA)(2)/ADC2 35 P1.1/T2X(2)/ADC1 34 P1.0/T2(2)/ADC0
8
uPSD34XX 52-pin TQFP
33 VDD(1) 32 XTAL2 31 XTAL1 30 P3.7/I2CSCL 29 P3.6/I2CSDA 28 P3.5/C1 27 P3.4/C0
GND 9 USB 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13
SPISEL_(2)/PCACLK1/P4.7 14
SPITXD(2)/TCM5/P4.6 15
SPIRXD(2)/TCM4/P4.5 16
17
18
GND 19
RXD1(IrDA)(2)/TCM2/P4.2 20
T2X(2)/TCM1/P4.1 21
T2(2)/TCM0/P4.0 22
RXD0/P3.0 23
TXD0/P3.1 24
EXTINT0/TG0/P3.2 25
SPICLK(2)/TCM3/P4.4
TXD1(IrDA)(2)/PCACLK0/P4.3
EXTINT1/TG1/P3.3 26
AI08877
1. For 5V applications, VDD must be connected to 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port 1. 3. VREF and 3.3V AVCC are shared. ADC channels must use 3.3V as VREF for 52-pin package.
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AN1773 Figure 3. uPSD3300 80-pin TQFP pin definition
64 P1.7/SPISEL_(2)/ADC7 61 P1.6/SPITXD(2)/ADC6 79 P3.2/EXINT0/TG0
Pin definitions
68 RESET_IN_
75 P3.0/RXD0
77 P3.1/TXD0
72 3.3V VCC
6 3 PSEN _
70 VREF
69 GND
62 WR_
65 RD_
8 0 PB0
7 8 PB1
7 6 PB2
7 4 PB3
7 3 PB4
7 1 PB5
6 7 PB6
6 6 PB7
PD2 1 P3.3/TG1/EXINT1 2 PD1 3 ALE 4 PC7 5 JTAG TDO 6 JTAG TDI 7 DEBUG 8 PC4/TERR_ 9 3.3V VCC 10 NC 11 VDD(1) 12 GND 13 PC3/TSTAT 14 PC2/VSTBY 15 JTAG TCK 16 NC 17 SPISEL_(2)/PCACLK1/P4.7 18 SPITXD(2)/TCM5/P4.6 19 JTAG TMS 20
60 P1.5/SPIRXD(2)/ADC5 59 P1.4/SPICLK(2)/ADC4 58 P1.3/TXD1(IrDA)(2)/ADC3 57 MCU A11 56 P1.2/RXD1(IrDA)(2)/ADC2 55 MCU A10 54 P1.1/T2X(2)/ADC1 53 MCU A9 52 P1.0/T2(2)/ADC0
uPSD33XX 80-pin TQFP
51 MCU A8 50 VDD(1) 49 XTAL2 48 XTAL1 47 MCU AD7 46 P3.7/I2CSCL 45 MCU AD6 44 P3.6/I2CSDA 43 MCU AD5 42 P3.5/C1 41 MCU AD4
PA7 21
PA6 22
SPIRXD(2)/TCM4/P4.5 23
PA5 24
SPICLK(2)/TCM3/P4.4 25
PA4 26
TXD1(IrDA)(2)/PCACLK0/P4.3 27
PA3 28
GND 29
RXD1(IrDA)(2)/TCM2/P4.2 30
T2X(2)/TCM1/P4.1 31
PA2 32
T2(2)/TCM0/P4.0 33
PA1 34
PA0 35
MCU AD0 36
MCU AD1 37
MCU AD2 38
MCU AD3 39
P3.4/C0 40
AI08878
1. For 5V applications, VDD must be connected to 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port 1.
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Pin definitions Figure 4. uPSD3400 80-pin TQFP pin definition
64 P1.7/SPISEL_(2)/ADC7 61 P1.6/SPITXD(2)/ADC6 79 P3.2/EXINT0/TG0
AN1773
68 RESET_IN_
75 P3.0/RXD0
77 P3.1/TXD0
6 3 PSEN _
72 AVCC
70 VREF
69 GND
62 WR_
65 RD_
8 0 PB0
7 8 PB1
7 6 PB2
7 4 PB3
7 3 PB4
7 1 PB5
6 7 PB6
6 6 PB7
PD2 1 P3.3/TG1/EXINT1 2 PD1 3 ALE 4 PC7 5 JTAG TDO 6 JTAG TDI 7 DEBUG 8 PC4/TERR_ 9 3.3V VCC 10 USB+ 11 VDD(1) 12 GND 13 USB 14 PC3/TSTAT 15 PC2/VSTBY 16 JTAG TCK 17 SPISEL_(2)/PCACLK1/P4.7 18 SPITXD(2)/TCM5/P4.6 19 JTAG TMS 20
60 P1.5/SPIRXD(2)/ADC5 59 P1.4/SPICLK(2)/ADC4 58 P1.3/TXD1(IrDA)(2)/ADC3 57 NC 56 P1.2/RXD1(IrDA)(2)/ADC2 55 NC 54 P1.1/T2X(2)/ADC1 53 NC 52 P1.0/T2(2)/ADC0 51 NC 50 VDD(1) 49 XTAL2 48 XTAL1 47 MCU AD7 46 P3.7/I2CSCL 45 MCU AD6 44 P3.6/I2CSDA 43 MCU AD5 42 P3.5/C1 41 MCU AD4
uPSD34XX 80-pin TQFP
PA7 21
PA6 22
SPIRXD(2)/TCM4/P4.5 23
PA5 24
SPICLK(2)/TCM3/P4.4 25
PA4 26
TXD1(IrDA)(2)/PCACLK0/P4.3 27
PA3 28
GND 29
RXD1(IrDA)(2)/TCM2/P4.2 30
T2X(2)/TCM1/P4.1 31
PA2 32
T2(2)/TCM0/P4.0 33
PA1 34
PA0 35
MCU AD0 36
MCU AD1 37
MCU AD2 38
MCU AD3 39
P3.4/C0 40
AI08879
1. for 5v applications, vdd must be connected to 5.0v source. for 3.3v applications, vdd must be connected to a 3.3v source. 2. these signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port 1.
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AN1773
Details of pin changes
3
3.1
Details of pin changes
52-pin devices
Refer to Figure 1 and Figure 2. Pins 7 and 10:
The function of pins 7, 10 and 47 have changed per Table 1. The signals TSTAT and TERR are optional signals used to speed programming times while performing JTAG In-System Programming (ISP). If these signals were used in your 3300 design, they are no longer available on the 3400, meaning that only standard JTAG signals must be used (TCK, TMS, TDI, TDO) without the two additional optional signals TSTAT and TERR. Full-speed USB requires a pull-up resistor on the USB+ bus signal (pin 7) for identification purposes, using 1.5K to 3.3V VCC. This pull-up resistor should be in place on 3400 designs even if USB is not used. Pin 47 is dedicated to A/D Converter on the 3400 devices 52-pin device changes
Pin 7 3300 3400 PC4/TERR USB+ Pin 10 PC3/TSTAT USB Pin 47 3.3V VCC/VREF AVCC/VREF
Table 1.
3.2
80-pin devices
Refer to Figure 3 and Figure 4. Pins 11, 14, 15, 16, 17, 72, 51, 53, 55, and 57:
Three signals on the 3300 have shifted by one pin number on the 3400, and two NoConnect signals on the 3300 are now used on the 3400 (see Section 3.2: 80-pin devices). Full-speed USB requires a pull-up resistor on the USB+ bus signal (pin 11) for identification purposes, using 1.5K to 3.3V VCC. This pull-up resistor should be in place on 3400 designs even if USB is not used. Pin 72 is dedicated to A/D Converter on 3400 devices Pin 51, 53, 55 and 57 are No Connect on 3400 devices. Address A8-A11 can be brought out on PLD pins. 80-pin device changes
Pin 11 3300 3400 NC USB+ Pin 14 PC3/ TSTAT USB Pin 15 PC2/ VSTBY PC3/ TSTAT Pin 16 JTAG/ TCK PC2/ VSTBY Pin 17 NC JTAG CLK Pin 72 3.3V VCC AVCC Pin 51, 53, 55, 57 A8-A11 No Connect
Table 2.
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PC layout suggestions
AN1773
4
PC layout suggestions
You can plan your printed circuit board layout in anticipation of migrating from the 3300 to the 3400 by using simple and low cost techniques. One method involves the use of zeroohm resistors (either surface mount or thru-hole) and multiple circuit traces on the printed circuit board. The idea is to install or not install these zero-ohm resistors at the time of board manufacture, depending on which uPSD is installed. For example, Figure 5 shows how you can use this method to handle the new functions of Pins 7 and 10 on the 52-pin uPSD. If a 3300 device is installed, resistor positions R1 and R4 would be populated with zero-ohm resistors during manufacturing while R2, R3, and R5 are not populated. If a 3400 device is installed, zero-ohm resistors would be populated at R2 and R3, R5 is populated with 1.5K, while R1 and R4 are blank.
Figure 5.
PC layout example for 52-pin devices
uPSD (52-pin)
R1 Pin 10
PC3/TSTAT
R2
USB
R3
USB+
R4 Pin 7
PC4/TERR
Pin 6
R5, 1.5K
AI08880
3V VCC
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AN1773
PC layout suggestions Figure 6 illustrates one way to handle the differing functions of Pins 11, 14, 15, 16, and 17 on the 80-pin uPSD. If a 3300 device is installed, resistor positions R6, R7, and R8 would be populated with zero-ohm resistors during manufacturing while R1, R2, R3, R4, and R5 are not populated. If a 3400 device is installed, resistors R1, R2, R3, R4, and R5 are populated with zero-ohm resistors, R9 is populated with a 1.5K resistor, while R6, R7, and R8 are blank.
Figure 6.
uPSD (80-pin) Pin 17
PC layout example for 80-pin devices
R1 JTAG TCK
R6 Pin 16 R2 R7 R3 PC3/TSTAT R8 Pin 14 R4 USB PC2/VSTBY
Pin 15
R5 Pin 11 USB+
R9, 1.5K Pin 10
AI08881
3.3V VCC
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Special function register (SFR) differences
AN1773
5
Special function register (SFR) differences
There are 20 new SFRs in the 3400 to accommodate the USB function. They are highlighted with gray background in Table 3. See uPSD34XX data sheet for SFR details.
Table 3.
SFR Addr F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80
SFRs in the 3400
SFR Register Name CCON0 B UIF0 ACC SCON1 PSW T2CON P4 IP P3 IE P2 SCON0 P1 TCON P0 SBUF0 P3SFS TMOD SP P4SFS0 TL0 DPL P4SFS1 TL1 DPH ADCPS TH0 CAP COMH1 TCM MODE0 CAP COML3 SBUF1 SPICLKD RCAP2L CAP COMH3 PCACL1 CAP COML2 TCM MODE1 PCACL0 UCON UIF1 CCON1 USIZE UIF2 UADDR CCON2 UBASEH UIF3 UPAIR S1SETUP SPISTAT RCAP2H CAP COML4 PCACH1 CAP COMH2 TCM MODE2 PCACH0 CCON3 UBASEL UCTL UIE0 S1CON SPITDR TL2 CAP COMH4 PCACON1 PWMF0 CAP COML0 PCACON0 CAP COMH0 PCASTA BUSCON ADAT0 TH1 DPTC WDTKEY WDRST DIR ADAT1 P1SFS0 DPTM USCI USTA UIE1 S1STA SPIRDR TH2 CAP COML5 TCM MODE3 UIE2 S1DAT SPICON0 IRDACON CAP COMH5 TCM MODE4 USC V USEL UIE3 S1ADR SPICON1 DSTAT PWMF1 TCM MODE5 IPA CAP COML1 IEA DVR ACON P1SFS1 PCON SFR Addr FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
KEY:
SAME
NEW
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AN1773
Conclusion
6
Conclusion
The suggestions for methods to easily migrate designs from the uPSD3300 series to uPSD3400 allow the user to implement simple techniques on the printed circuit board to accept either a uPSD3300 or a uPSD3400 during manufacturing.
7
Contact Information
If you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses:
apps.psd@st.com
(for application support)
Please remember to include your name, company, location, telephone number, and fax number.
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Revision history
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8
Revision history
Table 4.
Date 23-Jan-2004 14-May-2007
Document revision history
Revision 1 2 First Issue Document reformatted. Updated page 1, 3, 5,6 Changes
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