AN1787 Application note
Conversion Guide, uPSD3200 to uPSD3400 series
1
Introduction
The uPSD family currently consists of three series, uPSD3200, uPSD3300, and uPSD3400. All three series are available in the same kind of packages (52-pin and 80-pin TQFP), but there are a few differences in pin definitions. This document describes the differences and suggests methods to easily migrate designs from the uPSD3200 series to uPSD3400. You can implement simple techniques on your printed circuit board to accept either a uPSD3200 or a uPSD3400 during manufacturing. Please see Application Note AN1724 for similar information regarding migrating designs from the uPSD3200 series to the uPSD3300 series, and see AN1773 for migrating from uPSD3300 to uPSD3400 designs. Pin differences will be presented two categories:
Mandatory pin function changes for all applications, and Conditional pin function changes depending on the application.
There are also differences in SFRs and interrupt vectors, which may impact firmware depending on the application. These differences are identified to help you migrate your firmware. For simplicity, the uPSD3200 series will be referred in this document as 3200, and the uPSD3400 series will be referred to as 3400.
May 2007
Rev 2
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Contents
AN1787
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Summar y of differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 1.1.9 1.1.10 MCU Core Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 MCU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 UART and I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
Summar y of new uPSD3400 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.2.11 1.2.12 1.2.13 1.2.14 1.2.15 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MCU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MCU core timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MCU core data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 IrDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 JTAG debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MCU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MCU clock division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Cross-Bar I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 High Current I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5V-tolerant I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 3
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mandatory pin changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 52-pin Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 80-pin devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Contents
4 5
PC layout suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Conditional pin changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 52-pin devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 80-pin devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PC Layout Suggestion for PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ADC, reassigned ADC channel numbers . . . . . . . . . . . . . . . . . . . . . . . . . 18 ADC voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ADC reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 7 8 9
Special function register (SFR) differences . . . . . . . . . . . . . . . . . . . . . 22 Interrupt vector differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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1.1
1.1.1
Summary of differences
MCU Core Voltage
The 3400 MCU core requires a 3.3V supply, even when used in a 5V system. This means two separate supplies (5V VDD and 3.3V VCC) are required in a 5V system, but just one supply (3.3V VCC) is required for a 3.3V system. In contrast, 3200 devices use only a single VCC supply, which is 5V VCC for 5V devices, or 3.3V VCC for 3.3V devices.
1.1.2
MCU Core
The 3200 MCU requires 12 clocks per instruction but the 3400 uses just 4 clocks. The 3400 does not have an optional 12-clock operation mode. No modifications are needed to 3200 firmware for standard 8032 functions unless timing was established with software loops. Modifications ARE required for firmware controlling some peripherals when migrating to 3400.
1.1.3
PWM
The five 8-bit PWM channels of the 3200 are implemented with the Programmable Counter Array (PCA) in the 3400, which has six 16-bit timer/counter modules. There are new SFRs, and some PWM pin number assignments have changed on the 3400.
1.1.4
ADC
The four 8-bit ADC channels of the 3200 are implemented using four of the eight 10-bit ADC channels on the 3400. There are new SFRs, but there are no ADC input pin number changes. The ADC reference voltage (VREF) input pin is not available on 52-pin 3400 devices and VREF is shared internally with the 3.3V VCC core supply. 80-pin 3400 devices do have an ADC VREF pin, and its maximum input voltage is VCC (3.3V). The maximum input voltage on any 3400 ADC input or reference is VCC (3.3V) even in a 5V system.
1.1.5
LVD
Both 5V and 3.3V 3400 devices have Low-Voltage Detect (LVD) trip point set for the 3.3V VCC supply level (2.5V). This must be considered when designing 5V systems.
1.1.6
Watchdog
The watchdog timer is enabled after reset on 3200 devices, but it is disabled after reset on 3400 devices.
1.1.7
I/O characteristics
The 3.3V 3400 devices have 5V tolerant I/O on ports 3, and 4, but ports A,B,C, and D are not 5V tolerant. The 3.3V 3200 devices do not have any 5V tolerant I/O ports.
1.1.8
USB
The 3200 supports low-speed USB 1.1 (1.5Mbps), the 3400 supports full-speed USB 2.0 (12Mbps). The 3400 has all new SFRs for the USB channel. Some USB bus pin numbers have changed between the 3200 and 3400.
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1.1.9
UART and I2C
Minor changes to SFR definitions.
1.1.10
DDC
No DDC interface is on the 3400.
1.2
Summary of new uPSD3400 functions
Listed below are new functions on the 3400 that were not available on the 3300:
1.2.1
USB
The 3400 supports USB 2.0 Full-Speed (12Mbps) and includes the USB physical interface. There are a total of 5 pair of endpoints (each pair consists of In and Out). One endpoint pair is for USB Control transfer types, the remaining four endpoint pairs can be used for any combination of USB Interrupt or USB Bulk transfer types. Each individual endpoint has a 64byte FIFO (10 FIFOs total) to maintain USB data throughput.
1.2.2
MCU Core
The 8032 MCU core of the 3400 operates on 4-clocks per instruction, with a maximum clock rate of 40MHz, yielding 10 MIPS (Million Instructions Per Second) maximum performance for single-byte instructions. The 3400 MCU core has a 16-bit internal path from memory to enhance performance, meaning that double-byte instructions are fetched in a single MCU cycle, which pushes average performance close to the peak performance. No firmware changes are required to take advantage of this enhancement. In summary, 3400 has 10 MIPS peak performance, but you can expect about 9 MIPS average performance, compared to 3.3 MIPS peak and 3.0 MIPS average performance from the 3200.
1.2.3
MCU core timing
The 3400 Turbo MCU core has a six-deep instruction prefetch queue and a four-way branching address cache to increase performance. Code in smaller localities operate very fast. No special firmware is required to take advantage of the prefetch queue or branching cache. Be aware that firmware timing loops will not be accurate because of the nondeterministic nature of pipeline and cache architecture. Please use one of the many hardware timer modules to create timing functions, not firmware loops.
1.2.4
MCU core data pointers
The 3400 Turbo MCU core includes dual data pointers to speed data transfers of XDATA. The pointers can auto-increment and auto-decrement, providing rapid data movement from source to destination locations. The 3200 has one only data pointer.
1.2.5
SPI
An SPI bus master interface is provided on the 3400.
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1.2.6
ADC
Eight 10-bit ADC inputs are provided, compared to only four 8-bit ADC inputs on the 3200.
1.2.7
IrDA
The 2nd UART channel supports IrDA protocol, which be connected directly to an IR transceiver.
1.2.8
PCA
The Programmable Counter Array unit has six 16-bit timer/counter (TC) modules that can be used for PWM, Capture/Compare, Timers, or Counters. Three of the six TC modules can operate from one time base, and the other three TC modules can operate from another time base if desired. These six TC modules are in addition to the standard three 16-bit timer units inside the 8032 MCU core, bringing a total of nine 16-bit timer/counters. The 3200 provides only the three standard 16-bit 8032 timers.
1.2.9
JTAG debug
The JTAG port now functions as a debug port in addition to In-System Programming (ISP). This eliminates the need for conventional hardware In-Circuit Emulation (ICE) tools.
1.2.10
Debug
The 3400 has a dedicated debug input/output pin. As an output, it can signal that a specified debug event has occurred, as an input it can trigger a debug event to begin (e.g., breakpoint or trace)
1.2.11
MCU clock
3.3V 3400 devices can be clocked up to 40MHz, unlike 3.3V 3200 with 24MHz maximum.
1.2.12
MCU clock division
The 8032 MCU clock can be divided internally for lower power operation. The MCU may change the clock divider ratio on-the-fly using SFRs. This affects the MCU only, not peripheral clocks.
1.2.13
Cross-Bar I/O
Peripheral functions on Port 1 are also available on Port 4 (cross-bar switch), providing more flexibility. There is no need to sacrifice one peripheral function when two functions are available on a single pin, just use the other port.
1.2.14
High Current I/O
Eight I/O pins on Port 4 are each capable of sinking or sourcing 10mA for both, 3.3V and 5.0V 3400. In contrast, 3.3V 3200 pins are capable of sinking 4mA each, while the 5V 3200 can sink 8mA each.
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AN1787
1.2.15
5V-tolerant I/O
The following pins are 5V tolerant on 3.3V, 52-pin 3400 devices: P1.1 through P1.7, P3.1 through P3.7, P4.1 through P4.7, and RESET_IN_. On 3.3V, 80-pin 3400 devices, the following pins are also 5V tolerant: MCU_AD0 through MCU_AD7, RD_, WR_, and _PSEN. In contrast, 3.3V 3200 devices had no 5V tolerant I/O pins.
Note:
PSD functions have NOT changed from the 3200 to 3400. These functions include PLD, memory mapping, memory management (code space vs. data space, and paging), Flash memories, SRAM memory, and PSD I/O. The wider 16-bit internal data path on the 3400 (compared to 8-bit path on 3200) is transparent to the user. Please note the SRAM on the 3400 can not be configured to reside in code space.
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Pin definitions
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2
Pin definitions
Figure 1 and Figure 2 show pin assignments of the 3200 and 3400 devices in both 52-pin and 80-pin TQFP packages. Please see the 3200 and 3400 data sheets for detailed pin function descriptions and physical dimensions of packages. Pins requiring mandatory changes during migration are darkened in the figures, this assumes that USB will be used in both the 3200 and 3400 applications.
Note:
5V 3200 devices support USB while the 3.3V 3200 devices do NOT support USB. Figure 1. uPSD3200 52-pin TQFP pin definition
41 P1.7/ADC3 40 P1.6/ADC2 44 RESET
46 VREF 45 GND
43 PB6
PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 USB 5 PC4/TERR 6 USB+ 7 VCC 8 GND 9 PC3/TSTAT 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13
42 PB7
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
47 PB5
39 P1.5/ADC1 38 P1.4/ADC0 37 P1.3/TXD1 36 P1.2/RXD1 35 P1.1/T2X 34 P1.0/T2
uPSD32XX 52-pin TQFP
33 VCC 32 XTAL2 31 XTAL1 30 P3.7/SCL1 29 P3.6/SDA1 28 P3.5/T1 27 P3.4/T0
P4.7/PWM4 14
P4.6/PWM3 15
P4.5/PWM2 16
P4.4/PWM1 17
P4.3/PWM0 18
GND 19
P4.2/DDC VSYNC 20
P4.1/DDC SCL 21
P4.0/DDC SDA 22
P3.0/RXD 23
P3.1/TXD 24
P3.2/EXINT0 25
P3.3/EXINT1 26
AI08885
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AN1787 Figure 2. uPSD3400 52-pin TQFP pin definition
40 P1.6/SPITXD(2)/ADC6 41 P1.7/SPISEL(2)/ADC7
Pin definitions
47 AVCC/VREF(3)
44 RESET_IN_
45 GND
46 PB5
43 PB6
42 PB7
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3.3V VCC 6 USB+ 7 VDD(1) 8 GND 9 USB 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13
39 P1.5/SPIRXD(2)/ADC5 38 P1.4/SPICLK(2)/ADC4 37 P1.3/TXD1(IrDA)(2)/ADC3 36 P1.2/RXD1(IrDA)(2)/ADC2 35 P1.1/T2X(2)/ADC1 34 P1.0/T2(2)/ADC0
uPSD34XX 52-pin TQFP
33 VDD(1) 32 XTAL2 31 XTAL1 30 P3.7/I2CSCL 29 P3.6/I2CSDA 28 P3.5/C1 27 P3.4/C0
SPISEL_(2)/PCACLK1/P4.7 14
SPITXD(2)/TCM5/P4.6 15
SPIRXD(2)/TCM4/P4.5 16
SPICLK(2)/TCM3/P4.4 17
TXD1(IrDA)(2)/PCACLK0/P4.3 18
GND 19
RXD1(IrDA)(2)/TCM2/P4.2 20
T2X(2)/TCM1/P4.1 21
T2(2)/TCM0/P4.0 22
RXD0/P3.0 23
TXD0/P3.1 24
EXTINT0/TG0/P3.2 25
EXTINT1/TG1/P3.3 26
AI08887
1. For 5V applications, VDD must be connected to 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port 1. 3. VREF and 3.3V AVCC are shared. ADC channels must use 3.3V as VREF for 52-pin package.
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Pin definitions Figure 3. uPSD3200 80-pin TQFP pin definition
79 P3.2/EXINT0 64 P1.7/ADC3 61 P1.6/ADC2 75 P3.0/RXD 77 P3.1/TXD
AN1787
68 RESET
63 PSEN
70 VREF 69 GND
80 PB0
78 PB1
76 PB2
74 PB3
73 PB4
72 PB5
67 PB6
66 PB7
PD2 1 P3.3/EXINT 2 PD1 3 ALE 4 PC7 5 JTAG TDO 6 JTAG TDI 7 USB 8 PC4/TERR 9 USB+ 10 NC 11 VCC 12 GND 13 PC3/TSTAT 14 PC2/VSTBY 15 JTAG TCK 16 NC 17 P4.7/PWM4 18 P4.6/PWM3 19 JTAG TMS 20
62 WR
71 NC
65 RD
60 P1.5/ADC1 59 P1.4/ADC0 58 P1.3/TXD1 57 P2.3/A11 56 P1.2/RXD1 55 P2.2/A10 54 P1.1/T2X 53 P2.1/A9 52 P1.0/T2
uPSD32XX 80-pin TQFP
51 P2.0/A8 50 VCC 49 XTAL2 48 XTAL1 47 P0.7/AD7 46 P3.7/SCL1 45 P0.6/AD6 44 P3.6/SDA1 43 P0.5/AD5 42 P3.5/T1 41 P0.4/AD4
PA7 21
PA6 22
P4.5/PWM2 23
PA5 24
P4.4/PWM1 25
PA4 26
P4.3/PWM0 27
PA3 28
GND 29
P4.2/DDC VSYNC 30
P4.1/DDC SCL 31
PA2 32
P4.0/DDC SDA 33
PA1 34
PA0 35
AD0/P0.0 36
AD1/P0.1 37
AD2/P0.2 38
AD3/P0.3 39
P3.4/T0 40
AI08886
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AN1787 Figure 4. uPSD3400 80-pin TQFP pin definition
61 P1.6/SPITXD(2)/ADC6 64 P1.7/SPISEL(2)/ADC7 79 P3.2/EXINT0/TG0
Pin definitions
68 RESET_IN_
75 P3.0/RXD0
77 P3.1/TXD0
72 AV VCC
63 PSEN
70 VREF 69 GND
80 PB0
78 PB1
76 PB2
74 PB3
73 PB4
71 PB5
67 PB6
66 PB7
62 WR
65 RD
PD2 1 P3.3/TG1/EXINT1 2 PD1 3 ALE 4 PC7 5 JTAG TDO 6 JTAG TDI 7 DEBUG 8 PC4/TERR 9 3.3V VCC 10 USB+ 11 VDD(1) 12 GND 13 USB 14 PC3/TSTAT 15 PC2/VSTBY 16 JTAG TCK 17 SPISEL_(2)/PCACLK1/P4.7 18 SPITXD(2)/TCM5/P4.6 19 JTAG TMS 20
60 P1.5/SPIRXD(2)/ADC5 59 P1.4/SPICLK(2)/ADC4 58 P1.3/TXD1(IrDA)(2)/ADC3 57 NC 56 P1.2/RXD1(IrDA)(2)/ADC2 55 NC 54 P1.1/T2X(2)/ADC1 53 NC 52 P1.0/T2(2)/ADC0 51 NC 50 VDD(1) 49 XTAL2 48 XTAL1 47 MCU AD7 46 P3.7/I2CSCL 45 MCU AD6 44 P3.6/I2CSDA 43 MCU AD5 42 P3.5/C1 41 MCU AD4
uPSD34XX 80-pin TQFP
PA7 21
PA6 22
SPIRXD(2)/TCM4/P4.5 23
PA5 24
SPICLK(2)/TCM3/P4.4 25
PA4 26
TXD1(IrDA)(2)/PCACLK0/P4.3 27
PA3 28
GND 29
RXD1(IrDA)(2)/TCM2/P4.2 30
T2X(2)/TCM1/P4.1 31
PA2 32
T2(2)/TCM0/P4.0 33
PA1 34
PA0 35
MCU AD0 36
MCU AD1 37
MCU AD2 38
MCU AD3 39
P3.4/C0 40
AI08888
1. For 5V applications, VDD must be connected to 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port 1.
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Mandatory pin changes
AN1787
3
Mandatory pin changes
There are some pin changes (see Table 1 and Table 2) that are absolutely required when migrating from the 3200. These changes are a result of the additional voltage source required by the 3400 MCU core and the reassignment of USB pins, which are highlighted as dark colored pins in Figure 1 though Figure 4. It is assumed that USB was used in the 3200 and will be used in the 3400 design.
Note:
5V 3200 devices support USB while the 3.3V 3200 devices do NOT support USB.
3.1
52-pin Devices
Refer to Figure 1 and Figure 2.
Pin 5 Pin 5 (USB) on the 3200 must be pulled up to VCC, regardless of whether USB is used or not. The pull-up resistor value for 3.3V 3200 devices is 2K; the pull-up value for 5V 3200 devices is 7.5K. Pin 5 on the 3400 device functions as a Debug input/output, and does not need a pullup to VCC.
Pins 6 and 10 The functions of pin 6 (PC4/TERR) and pin 10 (PC3/TSTAT) on 3200 devices have been eliminated on the 52-pin 3400 devices to accommodate some pin function reassignments. These two signals on the 3200 were used as general purpose I/O or as optional JTAG ISP pins that reduce programming time. Pin 6 on the 3400 is VCC and must always be connected to a 3.3V VCC supply. Pin 10 on the 3400 is USB and is connected to the USB bus for 3400 applications (with no pull-up resistor).
Pin 7 Pin 7 on both the 3200 and the 3400 is the USB+ signal and has not changed. However, the 3200 supports low-speed USB, while the 3400 supports full-speed USB. Low-speed USB requires a pull-up resistor on the USB signal whereas the full-speed USB requires a pull-up resistor on the USB+ signal for identification purposes. Since 3400 is full-speed, a pull-up resistor (1.5K) to 3.3VCC is required. This pull-up resistor should be in place on 3400 designs even if USB is not used.
Pins 46 and 47 The functions of pins 46 and 47 have been swapped. Pin 47 on the 3400 must always be connected to AVCC/VREF. The ADC VREF (voltage reference) input was on pin 46 for the 3200, but is now on pin 47 for the 3400.
VCC and VDD In a 3.3V system using a 3.3V 3400 device, pins 6, 8, 33, 47 must be connected to a 3.3V VCC source. In a 5V system, using a 5V 3400 device, pins 6 and 47 should be connected to a 3.3V VCC source, and pins 8 and 33 should be connected to a 5.0V VDD source.
Pin 47 is dedicated to A/D Converter on the 3400 devices
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AN1787 Table 1. 52-pin device changes
Pin 5 3200 3400 USB (pullup) DEBUG Pin 6 PC4/TERR 3.3V VCC Pin 7 USB+ USB+ (pullup) Pin 10 PC3/TSTAT
Mandatory pin changes
Pin 46 ADC VREF PB5
Pin 47 PB5 AVCC/VREF
3.2
80-pin devices
Refer to Figure 3 and Figure 4. Table 2 summarizes the mandatory pin changes for 80-pin devices.
Pins 8 Pin 8 (USB) on the 3200 must be pulled up to VCC, regardless of whether USB is used or not. The pull-up resistor value for 3.3V 3200 devices is 2K, the pull-up value for 5V 3200 devices is 7.5K. Pin 8 on 3400 devices functions as a Debug input/output, and does not need a pull up to VCC.
Pin 10 Pin 10 is the USB+ signal on 3200 devices, but on 3400 it must always be connected to 3.3V VCC.
Pin 11 Pin 11 on 3200 is not used, but on 3400 devices it is the USB+ signal and must be pulled up to 3.3V VCC (with 1.5K) for USB identification purposes.
Pin 14 Pin 14 on 3200 is PC3/TSTAT which can be a general purpose I/O signal or an optional JTAG ISP signal used to reduce programming time. If this signal was used in the 3200 design, you can connect it to pin 15 on the 3400 (not a mandatory signal). Pin 14 on the 3400 is the USB signal and is connected to USB bus (with no pull-up resistor).
Pins 16 and 17 Pin 16 on the 3200 is JTAG CLK used for ISP. Pin 16 on the 3400 is PC2/VSTBY used for general purpose I/O or for the battery input for SRAM backup. You will need to reroute JTAG CLK to pin 17 on the 3400. JTAG CLK is a mandatory signal. If PC2/VSTBY was used in the 3200 design, you can connect it to pin 16 on the 3400. PC2/VSTBY is not a mandatory signal.
Pins 71 and 72 The functions of pins 71 and 72 have been swapped. Pin 72 on the 3400 must always be connected to AVCC/VREF.
VCC and VDD In a 3.3V system using a 3.3V 3400 device, pins 10, 12, 50 must connect to 3.3V VCC source. In a 5V system, using a 5V 3400 device, pin 10 should be connected to a 3.3V VCC source, and pins 12 and 50 should be connected to a 5.0V VDD source.
Pin 72 is dedicated to A/D Converter on 3400 devices.
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PC layout suggestions
AN1787
Pin 51, 53, 55 and 57 are No Connect on 3400 devices. Address A8-A11 can be brought out on PLD pins. 80-pin device changes
Pin 8 USB (pull-up) DEBUG Pin 10 Pin 11 No Connect USB+ (pull-up) Pin 14 PC3/ TSTAT USB Pin 16 JTAG TCK PC2/VS
TBY
Table 2.
Pin 17
Pin 51, 53, 55, 57
Pin 71
Pin 72
3200 3400
USB+ 3.3V VCC
No No A8-A11 Connect Connect JTAG TCK No Connect PB5
PB5 AVCC
4
PC layout suggestions
You can plan your printed circuit board layout in anticipation of migrating from the 3200 to the 3400 by using simple and low cost techniques. One method involves the use of zeroohm resistors (either surface mount or thru-hole) and multiple circuit traces on the printed circuit board. The idea is to install or not install these zero-ohm resistors at the time of board manufacture, depending on which uPSD is installed. For example, Figure 5 shows how you can use this method to handle the swapped functions of pins 46 and 47 on the 52-pin uPSD. In this example, resistors are installed at some locations, and no resistors are installed at other locations as specified in Table 3. A similar method can be used for an 80-pin device, using pins 71 and 72 instead of pins 46 and 47, respectively.
Figure 5.
PC layout example for pin swapping
uPSD (52-pin) R1
R2 Pin 47
R3 Pin 46 R5
PB5
3.3V VCC R4
VREF R6
AI08892
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AN1787 Table 3. 52-pin uPSD (0) resistor installation example
R1 3200 3400 0 Blank R2 Blank 0 R3 Blank 0 R4 0 Blank
PC layout suggestions
R5 Blank 0
R6 0 Blank
Figure 6 illustrates one way to handle the differing functions of Pins 5 through 10 on the 52pin uPSD. For this example, resistors are installed at some locations, and no resistors are installed at other locations as specified in Table 4. Note: The Debug signal is only for laboratory use and typically will be routed to a test point on the circuit board. PC Layout Example for 52-pin Devices
R1 PC3 / TSTAT
Figure 6.
uPSD (52-pin) Pin 10 3.3V for 3400, 5.0V for 3200 Pin 9
R2 GND R3 R4 USB 1.5K 7.5K R6 USB+ R5
Pin 8
Pin 7
Pin 6 R7 Pin 5
PC4 / TERR
DEBUG
AI08891
Table 4.
52-pin uPSD Resistor Installation Example (for Pins 5 through 10)
R1 R2 Blank 0 R3 0 1.5K R4 7.5K Blank R5 Blank 0 R6 0 Blank R7 0 Blank
3200 3400
0 Blank
Figure 7 illustrates one way to handle the differing functions of pins 5 through 17 on the 80pin uPSD. For this example, resistors are installed at some locations, and no resistors are installed at other locations as specified in the following Table 5. Note: The Debug signal is only for laboratory use and typically will be routed to a test point on the circuit board.
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PC layout suggestions Figure 7. PC layout example for 80-pin devices
AN1787
uPSD (80-pin) Pin 17 R1 JTAG TCK
Pin 16 R3 Pin 15 R5
R2 PC2 / VSTBY R4 PC3 / TSTAT R6 R7 USB
Pin 14
Pin 13
GND
3.3V for 3400, 5.0V for 3200 R8, 7.5K
Pin 12 R9 1.5K Pin 11 R10 R11 USB+
Pin 10
R12
R13 Pin 9 PC4/TERR
Pin 8
DEBUG
AI08890
Table 5.
R1 3200 Blank 3400 0
80-pin uPSD resistor installation example (for pins 5 through 17)
R2 0 Blank R3 Blank 0 R4 7.5 K Blank R5 Blank 0 R6 0 Blank R7 Blank 0 R8 0 Blank R9 R10 R11 R12 0 R13 0
Blank Blank Blank 1.5 K 0 0
Blank Blank
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AN1787
Conditional pin changes
5
Conditional pin changes
There are some pin changes that may or may not apply to your design, depending on your application. These changes must be considered when migrating to the 3400 and you have used the PWM or ADC peripherals of the 3200. There is also a conditional change regarding the use of the Low-Voltage Detect (LVD) feature in 5V 3400 devices.
5.1
PWM
There are five PWM outputs on the 3200, and six PWM outputs on the 3400. If you have used any of PWM outputs PWM1, PWM2, or PWM3, on the 3200 then there are no pin changes when migrating to the 3400. However, if you have used PWM outputs PWM0 or PWM4 on the 3200, then you will have to connect to different pins on the 3400. The Programmable Counter Array (PCA) on the 3400 has six Timer/Counter I/O pins, labeled TCM0 through TCM5, that can be used for PWM outputs, and the PCA also has two clock input pins labeled PCACLK0 and PCACLK1. These eight PCA pins are all on Port 4. It is the two PCA clock input pins of the 3400 that conflict with the PWM0 and PMW4 pin assignments of the 3200.
5.2
52-pin devices
Refer to Figure 1 and Figure 2. If you are using up to three of the five PWM outputs on the 3200, do not use outputs PMW0 or PWM4. Instead, use outputs PWM1, PWM2, or PWM3 and there will be no pin conflicts when migrating to the 3400. If you are using four or more PWM outputs on the 3200, then PWM0 on pin 18, or PWM4 on pin 14, they will have to be moved to one of the following pins on the 3400: pins 15, 16, 17, 20, 21, or 22.
5.3
80-pin devices
Refer to Figure 3 and Figure 4. If you are using up to three of the five PWM outputs on the 3200, do not use outputs PMW0 or PWM4. instead, use outputs PWM1, PWM2, or PWM3 and there will be no pin conflicts when migrating to the 3400. If you are using four or more PWM outputs on the 3200, then PWM0 on pin 27, or PWM4 on pin 18, they will have to be moved to one of the following pins on the 3400: pins 19, 23, 25, 30, 31, or 33.
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Conditional pin changes
AN1787
5.4
PC Layout Suggestion for PWM
Figure 8 is an example of how to move PWM output PWM0 on a 3200 device to the PCA output TCM2 on a 3400 device (52-pin). When a 3200 is installed, R1 is populated with a zero-ohm resistor and R2 is blank. When a 3400 is installed, only R2 is populated. A similar method can be used for an 80-pin device using pins 27 and 30 instead of pins 18 and 20, respectively.
Figure 8.
PC layout example to swap PWM outputs
uPSD (52-pin)
R2 Pin 20
R1 PWM_out Pin 18
AI08889
5.5
ADC, reassigned ADC channel numbers
The 3200 has four ADC inputs (8-bit resolution), and the 3400 has eight ADC inputs (10-bit resolution). The physical ADC input pin numbers have not been changed, but the logical ADC channel numbers change when migrating from 3200 to 3400. This means no changes to the PC board are required, but MCU firmware must change to account for different channel numbers. Firmware changes must occur anyway because there are SFR changes, identified in the next section. Table 6 refers to 52-pin uPSD devices and Table 7 refers to 80pin uPSD devices. Table 6. Reassigned ADC Channel Numbers, 52-pin uPSD
3200 Device ADC Channel 0 ADC Channel 1 ADC Channel 2 ADC Channel 3 3400 Device ADC Channel 4 ADC Channel 5 ADC Channel 6 ADC Channel 7
Pin Number on 52-pin TQFP 38 39 40 41
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AN1787 Table 7. Reassigned ADC Channel Number, 80-pin uPSD
3200 Device ADC Channel 0 ADC Channel 1 ADC Channel 2 ADC Channel 3
Conditional pin changes
Pin Number on 80-pin TQFP 59 60 61 64
3400 Device ADC Channel 4 ADC Channel 5 ADC Channel 6 ADC Channel 7
5.6
ADC voltage scaling
For all 3400 devices, both 3.3V and 5V, the maximum input voltage level on any of the eight ADC inputs is the MCU core voltage, VCC (3.6V maximum). This means that if 5V signals are to be sampled in a 5V 3400 system, they must be scaled down to 3.3V VCC. In contrast, for 5V 3200 devices, if 5V signals are sampled, they do not have to be scaled down because the maximum ADC input voltage is 5V Vcc (5.5V max). Figure 9 illustrates one way to scale a 0-5V analog signal down to 0-3.3V when a 3400 device is used. For example, if a 3400 device is installed, resistor R1 is populated with a 332K resistor, and R2 is populated with a 665K resistor. Precision 1% resistors are recommended. Alternately, if a 3200 is installed, R1 is populated with a zero-ohm resistor and R2 is left blank because no scaling is needed. Figure 9. Scaling 5V signal for 3.3V ADC Input
ANALOG INPUT, 0-5V Range uPSD R1
ADC Input
R2 GND
AI08882
5.7
ADC reference voltage
The maximum ADC Reference Voltage (VREF) allowed on the 3400 is the MCU core voltage, VCC (3.6V max), for both 3.3V and 5V 3400 devices. In contrast, for 5V 3200 devices the maximum ADC reference voltage is 5V VCC (5.5V max). Figure 10 shows one method to switch the source for VREF during manufacturing if needed. If a 5V 3200 is installed, R1 populated with a zero-ohm resistor and R2 is blank. If a 5V 3400 is installed, only R2 gets
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Conditional pin changes
AN1787
the zero-ohm resistor. This ONLY applies to 80-pin uPSD devices because 52-pin 3400 devices do not have a VREF input as discussed in the MANDATORY PIN CHANGE section and in Figure 5. Figure 10. Switching sources of VREF in 80-pin uPSD devices
5.0V VCC for 3200 uPSD (80-pin) R1
Pin 70 ADC VREF
R2 3.3V VCC for 3300
AI08883
5.8
LVD
The Low Voltage Detect (LVD) circuitry on all 3400 devices (both 3.3V and 5V) will generate an internal reset signal whenever the MCU 3.3V VCC voltage level dips below 2.5V. This is fine for 3.3V systems using a 3.3V 3400 device. However, for 5V systems using a 5V 3400 device, it is recommended to use an external LVD circuit to drive the RESET_IN_ pin if it is desired to monitor the 5.0V VDD system supply in addition to the 3.3V VCC supply. Regarding the 3200, there is no problem with 5V devices because the LVD circuitry has an internal trip point at 4.0V. RESET_IN_ is an active-low, open-drain, 5V tolerant input. RESET_IN_ is located at pin 44 on 52-pin devices, or pin 68 on 80-pin devices. Figure 11 illustrates a scheme that may be used when migrating from a 5V 3200 device to a 5V 3400 device. In this example, R1 is populated with a zero-ohm resistor only when a 3400 is installed, but R1 is left blank when a 3200 is used (supervisor device is optional when 3200 is used). R2 is always populated with a 10K resistor. Since the pin RESET_IN_ is open-drain, it may be driven by multiple open-drain sources. Suggestion: If a real-time clock (RTC) is needed in the system, choose an RTC that also has an LVD reset output so you can use it as shown in Figure 11. There are many types of these devices available from ST at www.st.com/nvram.
Note:
An external LVD circuit is not needed for 3.3V 3400 devices in a 3.3V system.
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AN1787 Figure 11. Applying External LVD Circuit to 3400 5V System
R2 10K 5V
Conditional pin changes
uPSD
RESET_J_ from JTAG connector
RESET_B_ from Push-button
RESET_IN_
R1 RESET_S_
Super visor Device or discrete LVD circuit
AI08884
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Special function register (SFR) differences
AN1787
6
Special function register (SFR) differences
The are a number of SFRs in the 3200 that have changed compared to the 3400. There are also a number of new SFRs in the 3400 to control new peripherals and features. None of the standard 8032 SFRs have changed (those defined in standard Intel 8032 architecture). Please see the full 3400 data sheet for a detailed description of new and changed SFRs. Below is a summary of the differences for those SFRs that have changed function or location (the SFRs with black background in Table 8). Please adjust your firmware for these changes.
87: PCON New POR Bit to determine source of last reset. 91: P3SF1 Used to be P1SF1. P1SF1, but it now has new meaning since it is linked to P4SF1 (please see the full 3400 data sheet).
96: ADAT1 Now different because 3400 has a 10-bit ADC, not an 8-bit ADC. 97: ACON New bits to control ADC interrupt. New bit to access eight ADC channels instead of four channels.
A7/A8: ICA/IA New Interrupt Enable bits for Debug, ADC, SPI, and PCA. B7/B8: IPA/IP New Interrupt priority bits for Debug, ADC, SPI, and PCA. D8/D9: SCON1/SBUF1 2nd UART control and data buffer. Same function as 3200, but new SFR address location in 3400.
DC: S1CON STO and STA Bits do not have to be cleared by software as they did in 3200. The 3400 has hardware (silicon) to assist, which improves I2C performance and reduces software overhead.
DD: S1STA More efficient use of INTR and ACK_REP_ Bits for I2C. MANY USB SFRS There are 19 new SFRs related to the Full-Speed USB interface, all of which start with the letter "U" and the CCON1 SFR.
Table 8 shows all the 3400 SFRs. Those with a black background and white letters indicate 3400 SFRs that have changed from the 3200 definition. Those with a gray background and black letters are new SFRs in the 3400.
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AN1787 Table 8.
SFR Addr F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 B UIF0
(1)
Special function register (SFR) differences SFRs in the 3400
SFR Register Name CCON0 UCON UIF1
(1)
SFR Addr FF USCI
(1) (1)
CCON1(1) USIZE UIF2
(1)
CCON2 UBASEH UIF3
(1)
CCON3 UBASEL UCTL
(1)
USCV
(1)
F7 USEL
(1)
(1)
(1)
(1)
(1)
USTA
EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
ACC SCON1 PSW T2CON P4 IP(2) P3 IE(2) P2 SCON0 P1 TCON P0 SBUF0 P3SFS(2) TMOD SP CAP COMH1 TCM MODE0 CAP COML3
(2)
UADDR(1) SBUF1
(2)
UPAIR(1) S1SETUP
UIE0(1) S1CON
(2)
UIE1((1) S1STA
(2)
UIE2(1) S1DAT SPICON0 IRDACON CAP COMH5 TCM MODE4
UIE3(1) S1ADR SPICON1 DSTAT PWMF1 TCM MODE5 IPA(2)
SPICLKD RCAP2L CAP COMH3 PCACL1 CAP COML2 TCM MODE1 PCACL0
SPISTAT RCAP2H CAP COML4 PCACH1 CAP COMH2 TCM MODE2 PCACH0
SPITDR TL2 CAP COMH4 PCACON1 PWMF0 CAP COML0 PCACON0
SPIRDR TH2 CAP COML5 TCM MODE3
CAP COMH0 PCASTA BUSCON
WDTKEY WDRST DIR ADAT1(2) P1SFS0 DPTM
CAP COML1 IEA(2) DVR ACON(2) P1SFS1 PCON(2)
P4SFS0 TL0 DPL
P4SFS1 TL1 DPH
ADCPS TH0
ADAT0 TH1 DPTC
1. New SFRs in uPSD3400 2. SFRs changed in uPSD3400
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Interrupt vector differences
AN1787
7
Interrupt vector differences
There are new interrupt vectors for the 3400, and some interrupt priority levels have changed. See Table 9 for comparison of interrupt vectors of 3200 and 3400 and their relative priorities. Please adjust your firmware accordingly. Table 9. interrupt vector tables and priority
3400 Priority 0 (high) 1 2 3 4 5 6 7 8 9 10 11 12 (low) N/A 3400 Vector Address (hex) 0063 0003 000B 0013 001B 0023 002B 0053 0033 0043 003B 005B 004B N/A 3200 Priority N/A 0 2 4 6 8 9 N/A 7 3 N/A N/A 1 5 3200 Vector Address (hex) N/A 0003 000B 0013 001B 0023 002B N/A 0033 0043 N/A N/A 004B 003B
Interrupt Source JTAG Debug External INT0 Timer 0 External INT1 Timer 1 UART0 Timer 2 + EXF2 SPI USB I
2C
ADC PCA UART1 DDC
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AN1787
Conclusion
8
Conclusion
The suggestions for methods to easily migrate designs from the uPSD3200 series to uPSD3400 allow the user to implement firmware and software settings, as well as simple techniques on the printed circuit board to accept either a uPSD3200 or a uPSD3400 during manufacturing. For current information on ST Flash uPSD products, please consult our pages on the world wide web: www.st.com/micropsd For application support: apps.psd@st.com (please include your name, company, location, telephone number, and fax number)
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Revision history
AN1787
9
Revision history
Table 10.
Date 26-Apr-2004 14 -May-2007
Document revision history
Revision 1 2 First Issue Document reformatted. Updated page 4, 6, 8,10, 11 and 12. Changes
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AN1787
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