ST V82x7
Digital Audio Decoder/Processor for A2 and NICAM Television/Video Recorders
DATASHEET
Key Features
Full-Automatic Multi-Standard Demodulation
B / G / I / L / M / N / D / K Standards Mono AM and FM FM 2-Carrier (German and Korean Zweiton) and NICAM
The STV82x7 family, based on audio digital signal processors (DSP), performs high quality and advanced dedicated digital audio processing.These devices provide all of the necessary resources for automatic detection and demodulation of analog audio transmissions for European and Asian terrestrial TV broadcasts. Vir tual or true, multi-channel capabilities and easy digital links make them ideal for digital audio low cost consumer applications. Starting from enhanced stereo up to independent control of 5 loudspeakers and a subwoofer (5.1 channels), the STV82x7 family offers standard and advanced features plus sound enhancements, spatial and virtual effects to enhance television viewer comfort and entertainment.
Multi-Channel Capability
3 I²S digital inputs, S/PDIF (pass-thru/out) 1 I²S digital output (shared with one of the I²S digital inputs) 5.1 analog outputs Dolby Pro Logic Dolby Pro Logic II
Sound Processing: Loudspeaker
ST royalty-free processing: ST WideSurround, ST OmniSurround (Virtual Dolby Surround and Virtual Dolby Digital compliant) and ST Dynamic Bass SRS WOWTM, SRS TruSurround XTTM (Virtual Dolby Surround and Virtual Dolby Digital compliant) Inde penden t Volume / Balance Smar t Volume Control (SVC), 5-band equalizer and loudness
Sound Processing: Headphone
Smar t Volume Control (SVC), Bass-Treble, Loudness and SRS TruBassTM Inde penden t Volume / Balance
Analog Audio Matrix
4 stereo inputs 3 stereo outputs THRU mode 2 V RMS capability
Audio Delay for Audio Video Synchronization
Embedded stereo delay up to 90 ms when processing at 32KHz (demodulator input mode) and up to 60 ms when processing at 48KHz (SCART only input mode) Inde penden t delay on headphone and loudspeaker channels
January 2006
Typical Applications
Analog and digital TV with virtual surround sound Ana log and digital TV with multi-channel surround sound DVD and HDD recorders "Pa lm size" portable TV
ST
x7 82 V
2004 SRS Labs, Inc. All rights reserved, SRS and the SRS logo are registered trademarks of SRS Labs, Inc.
"Dolby", "Pro Logic", and the double-D symbol are trademarks of Dolby Laboratories.
Rev. 4.1 1/156
CL K_SEL
XTAL IN
XTALOU T
2/ 156
I²S Inputs/Output
IRQ Headphone Detection Sound IF SIF
Headphone Digital Audio Processing
Control Logic Volume Balance Mute Matrix
Stereo Audio DAC
PCM_ CLK Loudspeakers
Stereo Audio DAC
DATA_0 DATA_1 DATA_2 LR _CLK LS_L LS_R LS_C LS_SUB Headphone / Surround HP_LSS_L HP_LSS_R S/PDIF Out S/PDIF In
Stereo Audio DAC Loudspeakers Digital Audio Processing Volume, Equalizer, Balance, Dolby Pro Logic Dolby Pro Logic II , ST WideSurround, ST Dynamic Bass, ST OmniSurround, Loudness,Smart Volume Control, Bass Management, Beeper SRS WOWTM or TruSurround XTTM
Stereo Audio DAC
Block Diagram
I²S Interface
P re-scaler
Digital Audio Matrix
AGC
Volume, Balance, Loudness, Smart Volume Control, Bass/Treble, SRS TrubassTM
A/D
S_ CLK
Digital FM/AM NICAM FM 2-carrier Demodulation
Mono Input MONO_IN Audio A/D
SC1_IN_L SC1_IN_R
SC2_IN_L SC2_IN_R
2 VRMS
SC1_OUT_L SC1_OUT_R
SC3_IN_L SC3_IN_R Clock Generator
Input Analog Audio Matrix
Output Analog Audio Matrix
2 VRMS
SC2_OUT_L SC2_OUT_R
SC4_IN_L SC4_IN_R
I²C Interface
2 VRMS
SC3_OUT_L SC3_OUT_R SCART Outputs
SCART Inputs SDA
SCL I²C
STV82x7
STV82x7
Table of Contents
Chapter 1
1.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
STV82x7 Overview . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 9
1.1.1 Core Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .9 1.1.2 Software Information . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...10 1.1.3 Device Input Modes . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....10 1.1.4 Electrical Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..11
1.2 1.3
Typical Applications . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 11 Pin Descriptions and Application Diagrams . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 15
Chapter 2 Chapter 3
3.1 3.2
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Digital Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Sound IF Signal . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 22 Dem odulation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 23
Chapter 4
4.1 4.2 4.3 4.4 4.5 4.6
Dedicated Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Back-end Processing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 25 Audio Processing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 26 ST WideSurround . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 30 ST OmniSurround . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 30 Dolby Pro Logic II Decoder . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 30 Bass Management . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 30
4.6.1 Bass Management Configuration 0 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .31 4.6.2 Bass Management Configuration 1 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .32 4.6.3 Bass Management Configuration 2 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .33 4.6.4 Bass Management Configuration 3 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .34 4.6.5 Bass Management Configuration 4 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .35
4.7
SR S WOW and TruSurround XT . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 35
4.7.1 SRS TruSurround . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...35 4.7.2 SRS WOW . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....36
4.8 4.9 4.10 4.11 4.12 4.13 4.14
Sm art Volume Control (SVC) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 36 ST Dynamic Bass . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 37 5-Band Audio Equalizer . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 37 Bass/Treble Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 37 Automatic Loudness Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 38 Volume/Balance Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 38 Soft Mute Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 39
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4.15 4.16 Beeper . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 39 Internal Audio/Video Delay (Lip Sync) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 40
Chapter 5 Chapter 6
6.1 6.2
Analog Audio Matrix (In / Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 I²S Interface (In / Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
I²S Inputs . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 42 I²S Output . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 44
Chapter 7 Chapter 8
8.1 8.2
S/PDIF Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Power Supply Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Standby Mode (Loop-through mode) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 47 Power on Reset . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 47
Chapter 9
9.1 9.2 9.3
Additional Controls and Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Headphone Detection . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 48 IRQ Generation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 48 I²C Bus Expander . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 48
Chapter 10 Chapter 11
11.1 11.2 11.3 11.4
STV82x7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 I²C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
I²C Address and Protocol . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 50 Start-up and Configuration Change Procedure . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 51 Process Flow during Patch Loading and DSP Initialization . . .. . .. . .. . .. . .. . .. . .. . .. . ... 53 Input Configuration Change . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 54
Chapter 12
12.1 12.2 12.3 12.4 12.5 12.6 12.7
Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
I²C Register Map . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 56 STV82x7 General Control Registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 62 Clocking 1 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 64 Dem odulator . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 66 Dem odulator Channel 1 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 69 Dem odulator Channel 2 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 73 NICAM Registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 78
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12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15 12.16 12.17 12.18 12.19 12.20 12.21 12.22 12.23 12.24 Stereo Mode . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 80 Analog Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 81 Clocking 2 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 83 DSP Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 84 Automatic Standard Recognition . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 88 Audio Preprocessing and Selection Registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 92 Matrixing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 100 Audio Processing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 105 5-Band Equalizer / Bass-Treble for Loudspeakers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 117 Headphone Bass-Treble . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 119 Volume . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 122 Beeper . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 132 Mute . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 133 S/PDIF . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 134 Headphone Configuration . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 134 DAC Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 135 AutoStandard Coefficients Settings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 137
Chapter 13
13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 13.12 13.13 13.14
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Absolute Maximum Ratings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 140 Thermal Data . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 140 Power Supply Data . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 140 Crystal Oscillator . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 141 Analog Sound IF Signal . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 141 SIF to I²S Output Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 142 SC ART to SCART Analog Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 142 SC ART and MONO IN to I²S Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 143 I2S to LS/HP/SUB/C Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 143 I²S to SCART Path Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 144 MUTE Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 144 Digital I/Os Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 144 I²C Bus Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 145
I2S Bus Interface . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 146
Chapter 14
Input/Output Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
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STV82x7 Chapter 15 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
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STV82x7
General Description
1
General Description
The STV82x7 is a multistandard TV sound demodulator and audio processor which integrates SRS WOWTM, SRS TruSurround XTTM, Dolby Pro Logic, Dolby Pro Logic II,Virtual Dolby Surround (VDS) and Virtual Dolby Digital (VDD) capability. ST advanced algorithms such as ST OmniSurround, ST WideSurround, ST Dynamic Bass are also available in this audio sound processor. ST OmniSurround is a certified Dolby algorithm for the Virtual Dolby Digital (VDD) and the Virtual Dolby Surround (VDS). When using VDD or VDS, either a Dolby Digital or a Pro Logic (or Pro Logic II) decoder is mandatory respectively. This chip performs automatic multistandard analog TV stereo sound identification and demodulation (no specific I²C programming is required). It offers various audio processing functions such as equalization, loudness, beeper, volume, balance, and surround effects. It provides a cost-effective solution for analog and digital TV designs. The STV82x7 is perfectly suited to current and future digital TV platforms, based on audio/video digital chips (STD2000, DTV100 platform) which include an internal digital decoder (MPEG, Dolby Digital...). In the case where a Dolby Digital decoder is embedded in the audio/video digital chip, Virtual Dolby Digital can be obtained. For the CTV100/120 platforms, this device is offered as an alternative solution to the first-generation chassis that uses the STV82x6.
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Table 1: STV82x7 Version List
STV8247 S T V 8 2 1 7 S T V 8 2 3 7 S T V 8 2 4 7 D S X S T V 8 2 5 7 D STV8257 S T V 8 2 5 7 D S X S T V 8 2 5 7 S X STV8267 S T V 8 2 6 7 D S X STV8277 S T V 8 2 7 7 D S X STV8287 S T V 8 2 8 7 D S X
S T V 8 2 4 7 D
S T V 8 2 6 7 D
S T V 8 2 7 7 D
S T V 8 2 8 7 D
Demodulation FM 2 Carrier and NICAM Multi-Channel Capabilities Analog loudspeakers output number I²S In (exclusive with I²S Out) S/PDIF (Pass-thru or Output) Vir tual Dolby Surround
2.1 1 1 2.1 1 1 2.1 1 1 X 2.1 1 1 X 2.1 3 1 X 2.1 3 1 X 2.1 3 1 5.1 1 1 X 5.1 1 1 X 5.1 3 1 X 5.1 3 1 X 5.1 3 1 VDS PLII X 5.1 3 1 VDS PLII X X X X X X X X X X X X X X
capability1
Dolby Pro Logic (DPLI) or Dolby Pro Logic II (DPLII) Audio Processing
SRS
ST Voice, ST Dynamic Bass ST WideSurround, ST OmniSurround2
1. Dolby Digital Bypass capability or Virtual Dolby Digital are obtained with the use of an external Dolby Digital decoder (for example STD2000). 2. When using Virtual Dolby Digital or Virtual Dolby Surround with ST OmniSurround or SRS TruSurround XT a Dolby Digital or a Pro Logic (or Pro Logic II) decoder is mandatory.
Figure 1: Package Ordering Information
Order Code: STV82x7 (Tray) STV82x7/T (Tape & Reel)
For Example: STV8257DSX/T will be delivered in Tape & Reel conditioning
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TM
SRS
WOWTM (WOW) TruSurround XTTM
X X
Vir tual Dolby
Digital
X
X
X
X
X
DPLI DPLI DPLI D PLI (internal) (internal) (internal) (internal)
DPLI
DPLI
DPLI
DPLI
DPLII
DPLII
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
FP TQ
80
STV82x7
General Description
1.1
1.1.1
STV82x7 Overview
Core Features
Single audio source processing: -- IF source and/or analog stereo input (SCART) -- one digital source with a maximum of 6 synchronous channels (5.1 is obtained across three I²S)
SIF input signal with Automatic Gain Control (AGC) Digital Demodulator with automatic standard detection and demodulation for AM, FM mono, FM 2 carriers (German or Korean FM 2-carrier) and NICAM Audio processor working at 32 kHz, 44.1 kHz or 48 kHz with specific features: -- For Loudspeakers (L, R, LS, R S, SubW, C): Dolby Pro Logic II Decoder with Bass Management SR S WOWTM or TruSurround XTTM including Virtual Dolby Surround and Virtual Dolby Digital ST WideSurround ST OmniSurround ST Dynamic Bass 5-band Equalizer or Bass-Treble Loudness Sm ar t Volume Control Volume/Balance/Soft-mute Beeper Video Processing Delay Compensation -- For Headphone: SR S TruBassTM Sm ar t Volume Control Bass-Treble Loudness Volume/Balance/Soft-mute Beeper Video Processing Delay Compensation
Shared outputs for headphone and loudspeakers surround channels: Analog matrix with: -- five external inputs: four SCART inputs (2 VRMS capable) one analog mono input (0.5 VRMS) -- one internal input from a digital matrix via a DAC -- three external outputs (2 VRMS capable) -- one internal output for the digital matrix (using an internal ADC)
Digital matrix with: -- three input modes (Demodulator/SCART, SCART only and I²S) -- three stereo outputs (Loudspeakers, Headphone and SCART)
High-end audio DAC S/PDIF pass-thru/output for connection with an external amplifier/decoder Inter nal multiplexer for the S/PDIF output (to share the internal S/PDIF output and the S/PDIF output generated by the external decoder of the digital broadcast)
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Specific stand-by mode (Loop-through) Control by I²C bus (two I²C addresses) System PLL and Clock Generation using either a single quartz oscillator or a differential clock input
1.1.2
Software Information
The different software combinations are listed in Table 2.
Table 2: Input/Output Software Configurations
Output (Number of Channels)
Input (Number of Channels) 2 (+1) 1 2 (L and R) ST WideSurround or SRS WOWTM ST WideSurround or SRS WOWTM ST WideSurround or SRS TruSurround XTTM or ST OmniSurround or Dolby Pro Logic + SRS TruSurround XTTM or Dolby Pro Logic + ST OmniSurround SRS TruSurround XTTM or ST OmniSurround or Downmix SRS TruSurround XTTMor ST OmniSurround or Downmix 4 (+1) 5 (+1)
4 (+1)
No processing
5 (+1)
Downm ix
Note: 1 In addition to the above sound processing, it is always possible to add ST Voice and also ST Dynamic Bass algorithms. 2 The SRS TruSurround and ST OmniSurround are approved by Dolby as Virtual Dolby Surround (VDS) and Virtual Dolby Digital (VDD). The SRS TruSurround XTTM system is composed of: SRS
The SRS WOWTM system includes: SRS SRS
1.1.3
Device Input Modes
Dem odulator only mode (with output fS = 32 kHz) Dem odulator and SCART mode (with output fS = 32 kHz) SCART only mode (with output fS = 48 kH z)
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SRS
SRS
TruSurround WOWTM
3D Mono/StereoTM Dialog ClarityTM TruBassTM
2 (LT and RT)
D olby
Pro Logic
No processing
STV82x7
General Description
I²S mode (with output fS = 32, 44.1 or 48 kHz) -- External audio input interface using 3 x I²S (for decoded streams such as Dolby Digital and/or standard stereo streams)
1.1.4
Electrical Features
Multi Power Supply: 1.8 V, 3.3 V and 8 V. Power Consumption:
lower than 1 W in Functional mode (full features) 200 mW in Loop-through mode corresponding to Switch-off of all digital blocks
1.2
Typical Applications
The STV82x7 is specified to enable flexible, analog and digital TV chassis design (refer to Figure 2, Figure 3, Figure 4 and Figure 5). The main considerations are:
all necessary connections between devices can be provided through the TV set, pseudo stand-by mode used to copy to VCR or the DVD sources when the TV set is OFF, possible application compatibility with STV82x6 (TQFP80 package) TV design, pin-to-pin compatibility with STV82x8 (TQFP80 package) TV design.
The STV82x7 is used to process a single audio source (analog or digital). However, it is possible to process two audio sources simultaneously using an STV82x7 interconnection (two chips can be easily connected). In the case of a single audio source, it is possible to hear and record in the same time: the same audio stream can be simultaneously output on headphone, loudspeakers, S/PDIF and the SCART connectors.
Note:
Headphone and loudspeakers can be used simultaneously for dual-language purposes or for different sound settings (e.g. volume). In this case, certain restrictions occur (see Section 4.2: Audio Processing).
For more connections, the SCART-to-SCART path can be used. The use of these full analog paths implies that the sound is not digitally processed.
11/156
General Description
STV82x7
Figure 2: STV8237 Typical Application (Enhanced Stereo)
Tuner
R
STV8237
or Multistandard Demodulation - FM 2-carrier and NICAM Sound Processing - Volume, Balance, 5-Band Equalizer - ST WideSurround - SRS WOWTM
SubW
L
Left Right
Figure 3: STV8247 Typical Application (Analog Virtual Sound)
Tuner
R
STV8247DSX
or Multistandard Demodulation - FM 2-carrier and NICAM Sound Processing - Volume, Balance, 5-Band Equalizer - SRS TruSurround XTTM - ST OmniSurround - Virtual Dolby Surround1 SubW
L
Left Right
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, a Pro Logic decoder is mandatory.
12/156
STV82x7
Figure 4: STV8257 Typical Application (Digital: Virtual Sound)
General Description
Multi-Channel Digital Decoder
Tuner
or
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, a Pro Logic decoder is mandatory. 2. When using VDD with ST OmniSurround or SRS TruSurround XTTM, a Dolby Digital decoder is mandatory.
Figure 5: STV8277 Typical Application (Digital TV: Multi-Channel and Virtual Sound)
Multi-Channel Digital Decoder
Tuner
or
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, a Pro Logic decoder is mandatory. 2. When using VDD with ST OmniSurround or SRS TruSurround XTTM, a Dolby Digital decoder is mandatory.
(Dolby
(Dolby
Digital)
R S/PDIF Pass-thru SubW
I²S
STV8257DSX
Multistandard Demodulation - FM 2-carrier and NICAM Audio Processing - Volume, Balance, 5-Band Equalizer - SRS TruSurround XTTM - ST OmniSurround - Virtual Dolby Surround1 - Virtual Dolby Digital2
L
Left Right
Digital)
R RS S/PDIF Pass-thru
SubW
I²S
STV8287DSX
Multistandard Demodulation - FM 2-carrier and NICAM Audio Processing - Volume, Balance, 5-Band Equalizer - Dolby Pro Logic II - 5.1 Analog Outputs - SRS TruSurround XTTM - ST OmniSurround - Virtual Dolby Surround1 - Virtual Dolby Digital2
C LS L
Left Right
Shared with surround LS/RS
13/156
General Description
Figure 6: STV8217 Typical Application (Digital Recorder)
STV82x7
MPEG Codec
Tuner
I ²S
or
STV8217
Multistandard Demodulation - FM 2-carrier and NICAM
Left Right
14/156
STV82x7
General Description
1.3
Pin Descriptions and Application Diagrams
AP DP I O OD B A
= Analog Power = Digital Power = Input = Output = Open-Drain = Bi-Directional = Analog
Table 3: TQFP80 Pin Description (Sheet 1 of 3)
Pin No.
1 2 3 4 5 6 7 8 9 10
STV82x7 Pin Name
SC1_O UT_L SC1_O UT_R VCC_H GN D _ H SC3_O UT_L SC3_O UT_R VCC33_SC GND33_SC SC1_IN_L SC1_IN_R
Type (STV82x7)
A A AP AP A A AP AP A A
Function for STV82x7 (Function for STV82x6 in italic characters)
SCART1 Audio Output Left SCART1 Audio Output Right 8 V Power for Audio I/O & ESD High Current Ground for Audio Outputs SCART3 Audio Output Left SCART3 Audio Output Right 3.3 V Power for Audio Buffers & DAC / ADC Ground for Audio Buffers & DAC / ADC SCART1 Audio Input Left SCART1 Audio Input Right Audio Bias Voltage Decoupling 1.55 V (Switched VREF decoupling pin for Audio Converters (VMCP)) Ground for DACs Bandgap Voltage Reference Decoupling 1.2 V (V REF decoupling pin for Audio Converters (VMC)) SCART2 Audio Input Left SCART2 Audio Input Right 3.3 V Power for Audio DACs (3.3 V Power Supply for Audio Buffers and SCART) Ground for Audio DACs (G round for Audio Buffers and SCART) SCART2 Audio Output Left SCART2 Audio Output Right Polarization of the NISO (connected to 3.3 V) (8 V / 5 V Power supply for SCART & Audio buffers) Ground for DAC 1.8 to 3.3 V Converters 3.3 V Power for DAC 1.8 to 3.3 V Converters (Voltage Reference for Audio buffers) AO1L
STV82x6 Pin Name
AO1R
Not connected Connected to Ground Not connected Not connected
VDDC GN D C AI1L AI1R
11
VREFA
A
VMC1
12 13 14 15 16 17 18 19 20 21 22
GN D _ S A VBG SC2_IN_L SC2_IN_R VCC33_LS GND33_LS SC2_O UT_L SC2_O UT_R VCC_NISO VSS33_CONV VDD33_CONV
AP A A A AP AP A A AP AP AP
Connected to Ground
VMC2 AI2L AI2R VDDA GNDAH AO2L AO2R VDDH
Connected to Ground
VREFA
15/156
General Description
Table 3: TQFP80 Pin Description (Sheet 2 of 3) Pin No.
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
STV82x7
STV82x7 Pin Name
SC3_IN_L SC3_IN_R SCL_FLT SCR_FLT LS_C LS_L LS_R LS_SUB HP_LSS_L HP_LSS_R VSS18_CONV VDD18_CONV HP_DET ADR_SEL VSS18 VDD18 SCL SDA VSS18 VDD18 RST S/PDIF_IN S/PDIF_OUT VDD33_IO1 VSS33_IO1 CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN_CLKXTP
Type (STV82x7)
A A A A A A A A A A DP DP I I DP DP OD OD DP DP I I O DP DP D DP DP I I
Function for STV82x7 (Function for STV82x6 in italic characters)
SCART3 Audio Input Left SCART3 Audio Input Right SCART Filtering Left SCART Filtering Right (Bandgap Voltage Source Decoupling) Center Output Left Loudspeaker Output Right Loudspeaker Output Subwoofer Output Left Headphone Output or Left Surround Output Right Headphone Output or Right Surround Output Ground for Digital part of the DAC/ADC (Substrate Analog/Digital Shield) 1.8 V Power for Digital part of the DAC/ADC Headphone Detection Hardware Address selection for I²C Bus Ground for Digital part 1.8 V Power for Digital part I²C Clock Input I²C Data I/O Ground for Digital part 1.8 V Power for Digital part (5 V Power Regulator Control) Main Reset Input Serial Audio Data Input (System Clock output) Serial Audio Data Output (I²S Master Clock output) 3.3 V Power for Digital part Ground for Digital part To be Grounded Ground for Digital part 1.8 V Power for Digital part Clock Input Format Selection Cr ystal Oscillator Input or Differential Input Positive (Cr ystal Oscillator Input) AI3L AI3R
STV82x6 Pin Name
Not connected
BGAP
Not connected
LSL LSR SW HPL HPR GNDSA
Not connected
HP D ADR
Connected to Ground Not connected
SCL SDA
Connected to Ground
REG RESET SYSCK MCK VDD1 GND1
Not connected
GNDSP
Not connected Not connected
XTI
16/156
STV82x7
Table 3: TQFP80 Pin Description (Sheet 3 of 3) Pin No.
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
General Description
STV82x7 Pin Name
XTALOUT_CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO2 VDD33_IO2 I2S_PCM_CLK I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GN D _ P S U B VDD18_ADC VSS18_ADC SIF_P SIF_N GNDPW_IF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R
Type (STV82x7)
O AP AP DP DP DP DP I/O I/O I/O I/O I I DP DP O O AP DP DP A A AP AP AP A A A
Function for STV82x7 (Function for STV82x6 in italic characters)
Cr ystal Oscillator Output or Differential Input Negative (Cr ystal Oscillator Output) XTO
STV82x6 Pin Name
1.8 V Power for Clock PLL Analog & Crystal Oscillator 1/2 VDDP (3.3 V Power supply for Analog PLL Clock) Ground for Clock PLL Analog & Crystal Oscillator 1/2 Ground for Clock PLL Digital 1/2 1.8 V Power for Clock PLL Digital 1/2 (3.3 V Power supply for Digital core, DSPs & IO Cells) Ground for Digital IO pins 60 to 69 3.3 V power for Digital IO pins 60 to 69 I²S Slave Clock Input/Output Channel 1, 2 & 3 I²S Clock Input/Output Channel 1, 2 & 3 (I²S bus data output) I²S Word Select Input/Output Channel 1,2 & 3 (Stereo Detection output / I²S Bus Data input) I²S Data Input/Output Stereo Channel 1 (I²S Bus Word Select output) I²S Data Input Stereo Channel 2 (I²S Bus Clock output) I²S Data Input Stereo Channel 3 (Bus Expander Output 1) 1.8 V Power for Digital Core & I/O Cells Pin Ground for Digital Core & I/O Cells Pin Bus Expander Function (Bus Expander Output 2) Interrupt Request to Microprocessor Ground Substrate Connection VDD 1.8 V for ADC (Digital Part) Ground to Complement 1.8 V VDD for ADC Sound IF input (positive) Sound IF input (negative) (ADC VTOP Decoupling pin) Polarization for the IF block (Voltage Reference for AGC Decoupling pin) 1.8 V Power for IF AGC & ADC Ground for IF AGC & ADC Mono Input (for AM Mono) SCART4 Audio Input Left SCART4 Audio Input Right GN D P GN D 2 VDD2
Connected to Ground Not connected Not connected
SDO ST/SDI WS SCK BUS1
Not connected Connected to Ground
BUS0 IR Q
Connected to Ground Not connected Connected to Ground
SIF VTO P VREFIF VDDI F GN D I F MONO IN
Not connected Not connected
17/156
+1 .8 V 10H + C9 330F L18 C10 1 0 0 nF L15 100H L14 1
1
L2 C69 3 3 nF C68 100H 3 3 nF C67 3 3 nF C66 3 3 nF C65 3 3 nF C64 3 3 nF
L17
100H
L16 100H
He ad p ho ne detection 100H SL1 100H 2 3
3
+3 .3 V 1 0 0 nF C12 Address select C13 1 0 0 nF
+
L13
C63 3 3 nF C62 3 3 nF
+
SCL
SDA
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
C14 1 0 0 nF C15 C75 220 C58 1 0 0 nF C74 220 C57 1 0 0 nF 330pF R8 330pF 1 0 0 nF + L1 10H +3 .3 V R9
R1
+3 .3 V
+
470K
C16 4 7 0 nF
Reset
+
S P D I F IN
SDA SCL VDD18 VSS18 ADR_SEL HP_DET VDD18_CONV VSS18_CONV HL_LSS_R HP_LSS_L LS_SUB LS_R LS_L LS_C SCR_FLT SCL_FLT SC3_IN_R SC3_IN_L VDD33_CONV VSS33_CONV
+
S P D I F OUT
+
L4 C18 1 0 0 nF TQFP80 C19 1 0 0 nF IC1 STV82x7
+3 .3 V
+
10H
+ C17 10F
+
C46 1F
+
10F C45 1F S C 1 IN Right C73 C47 330pF
+
R7 R6 220 C72 330pF + C41 10F
C25 1 0 0 nF
220 C44 1 0 0 nF 10F
+
+
+1 .8 V C42 1 0 0 nF R 5 220 330pF R4 220 C26 1 0 0 nF C27 1 0 0 nF
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
C21
1 .8 V
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS18 VDD18 RST_N SPDIF_IN S P D I F _ O UT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL X T A L I N/C L K X T P X T A L O UT /C L K X T M VCC18_CLK1 G ND 1 8 _ C L K 1 G ND 1 8 _ C L K 2 VCC18_CLK2 VSS33_IO VDD33_IO I 2 S _ P C M_ C L K 10H L12 C71 330pF C70 +8 V V C C _ NI S O S C 2 _ O UT _ R S C 2 _ O UT _ L G ND 3 3 _ L S VCC33_LS S C 2 _ I N_ R S C 2 _ I N_ L VBG G ND _ S A VREFA S C 1 _ I N_ R S C 1 _ I N_ L G ND 3 3 _ S C VCC33_SC S C 3 _ O UT _ R S C 3 _ O UT _ L G ND _ H VCC_H S C 1 _ O UT _ R S C 1 _ O UT _ L
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
27pF
+
+
I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GND_PWIF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R
C22
XT1 2 7 MHz CRYSTAL
+
1 .8 V
Figure 7: STV82x7 Application Diagram
27pF
C37
+
+
C33 1 0 0 nF + C43 47F L10 10H C34 2 2 nF
L6
1 .8 V
C32 2 2 0 nF
10H
+ C23
47F
R3
560
10H
C29 1 0 0 nF C30 1 0 0 nF
L11
+
+
+
+
+
+
18/156
C8 1F C7 1F C6 1F C5 1F C4 1F C3 1F SC3 IN Right S C 3 IN Left C61 1F C60 1F C59 47F S C 2 OUT Right S C 2 OUT Left C56 10F C55 10F S C 2 IN Right S C 2 IN Left 1 0 0 nF C51 10F C50 1 0 0 nF C49 C53 1F C54 1F C52 S C 1 IN Left S C 3 OUT Right 10F C48 S C 3 OUT Left S C 1 OUT Right S C 1 OUT Left 1F 1F C36 1F C38 S C 4 IN Right S C 4 IN Left Mo no IN C40 10F C39 10F +1 .8 V C35 IRQ 100pF B US EXPANDER I 2 S DATA 2 I 2 S DATA 1 I 2 S DATA 0 I 2 S LR CLK I 2 S SCLK I 2 S PCM CLK SIF
L S Center
L S Left
L S Right
S ub wo o f e r
HP Left/LS surround Left
General Description
HP Right/LS surround Right
STV82x7
STV82x7
with
LS Center
LS Left
LS Right
Subwoofer
HP Left/LS surround Left
HP Right/LS surround Right
L17
+1.8V + C9 330F L18 C69 33nF 100H C68 33nF C67 33nF C66 33nF C65 33nF C64 33nF
L8
*
10H
*
L16 100H
C10 100nF L15
100H
* *
L14
Headphone detection 100H 1
1
*
L13
+3.3V SL1 100H 2 C63 10F C13 100nF C62 33nF + C78 3 Address select
3
100H
*
100nF C12
+
+
SCL
SDA
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
C14 100nF +3.3V 0 R13 220 C58 100nF + C77 10F C57 100nF 0 + R19 C76 10F 0 R11 R8 220 C74 330pF R9
L2 10H
+8V
R1
+3.3V
+
470K
Reset
C16 470nF C15 R14 0 100nF
330pF
+
SPDIF IN
+
SDA SCL VDD1 8 VSS1 8 ADR_ SEL HP_ DET VDD1 8 _ CO NV VSS1 8 _ CO NV HL _ L SS_ R HP_ L SS_ L L S_ SUB L S_ R L S_ L L S_ C SCR_ FL T SCL _ FL T SC3 _ IN_ R SC3 _ IN_ L VDD3 3 _ CO NV VSS3 3 _ CO NV
SPDIF OUT
R10 330
+8V
+
L7
+3.3V C18 100nF TQFP80 C19 100nF IC1 STV82x6 / STV82x7
10H
+
+ C17 10F
R18
0
+
C46 1F
+
10F C45 1F SC1 IN Right R7 220
+1.8V C25 100nF R6
+
1
+1.8V
220 C72 330pF
C73 330pF + C43 10F 10H L3 +8V
SL2 C42 100nF
C21 C26 100nF C27 R15 0
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
C44 100nF
+
+
2
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS18 VDD18 RST_N SPDIF_IN SPDIF_OUT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN/CLKXTP XTALOUT/CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO VDD33_IO I2S_PCM_CLK VCC_NISO SC2_OUT_R SC2_OUT_L GND33_LS VCC33_LS SC2_IN_R SC2_IN_L VBG GND_SA VREFA SC1_IN_R SC1_IN_L GND33_SC VCC33_SC SC3_OUT_R SC3_OUT_L GND_H VCC_H SC1_OUT_R SC1_OUT_L R5 220 330pF R4 220 330pF C71
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3
+
I2 S_ SCL K I2 S_ L R_ CL K I2 S_ DATA0 I2 S_ DATA1 I2 S_ DATA2 VDD1 8 VSS1 8 BUS_ EXP IRQ G ND_ PSUB VDD1 8 _ ADC VSS1 8 _ ADC SIF_ P SIF_ N G ND_ PWIF VCC1 8 _ IF G ND1 8 _ IF MO NO _ IN SC4 _ IN_ L SC4 _ IN_ R
XT1 27MHz CRYSTAL 100nF
R2
+
C40 10F C39 10F C70
1
+1.8V
+
SL3
270k
C37
+
+
2 R16 C36 0 C33 100nF C32 220nF + C79 47F L4 10H L5 10H C34 C35 +3.3V +1.8V 1F
C22
1.8V
10H
3
L6
+ C23
47F
Figure 8: STV82x6/STV82x7 Compatible Application Electrical Diagram
560
10H
C29 100nF
L11
22nF R17 C30 100nF C31 100nF 0
R3
100pF
General Description
19/156
Note :
components with * are only mandatory
in case of DOLBY certification
+
+
+ C61 1F C60 1F C59 47F L1 10H C75 C56 10F C55 10F C53 1F C54 1F C52 100nF C51 10F C41 10F R12 82 +8V C47 10F C48 10F C38 1F 1F
+
+
+
+
C8 1F
C7 1F
C6 1F
C5 1F
C4 1F
C3 1F
+
Part L1 L2 L3 L4 L5,L6 L8 L13,L14 L15,L16 L17,L18 R2 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 C3 C9 C10,C13 C15,C18 C21,C22 C23 C27,C29 C30 C31 C41 C42 C43 C59 C63 C64,C65 C66,C67 C68,C69 C70,C71 C72,C73 C74,C75 C76,C77 C78 C79 SL2 SL3
with STV82x6 Not Connected 10H Not Connected 10H Not Connected Not Connected strap strap strap 270K 330 Not Connected 82 Not Connected 0 ohm 0 ohm Not Connected Not Connected 0 ohm Not Connected Not Connected Not Connected Not Connected Not Connected 22 pF Not Connected Not Connected Not Connected 100 nF 10 F Not Connected Not Connected 10 F 100 nF Not Connected Not Connected Not Connected Not Connected Not Connected Not Connected 10 F 10 F 10 F between 2-3 between 2-3
STV82x7 10H Not Connected 10H Not Connected 10H 10H 100H * 100H * 100H * Not Connected Not Connected 0 ohm Not Connected 0 ohm Not Connected Not Connected 0 ohm 0 ohm Not Connected 0 ohm 1 F 330 F 100 nF 100 nF 27 pF 47 F 100 nF 100 nF Not Connected Not Connected 100 nF 10 F 47 F 33 nF 33 nF 33 nF 33 nF 330 pF 330 pF 330 pF Not Connected Not Connected 47 F between 1-2 between 1-2
SC3 IN Right SC3 IN Left
SC2 OUT Right SC2 OUT Left
SC2 IN Right SC2 IN Left C50 100nF C49
SC1 IN Left SC3 OUT Right SC3 OUT Left SC1 OUT Right SC1 OUT Left SC4 IN Right SC4 IN Left Mono IN
SIF IRQ BUS EXPANDER / BUS I2S DATA 2 / BUS1 I2S DATA 1 / SCK I2S DATA 0 / WS I2S LR CLK / SDI I2S SCLK / SDO I2S PCM CLK
General Description
L17 * + C9 330F L18 * C10 100nF 100H L14 * 100H L13 * 100H 1 L15 * 100H L16 * 100H C69 33nF 100H C68 33nF C67 33nF C66 33nF C65 33nF C64 33nF
+1.8V
L2
10H
Headphone detection
1
+3.3V SL1 100nF C12
2
3 Address select C13 C62 33nF C63 33nF
3
+
+
SCL
100nF
SDA +3.3V
C14 100nF
R1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
3
+3.3V C75 C58 100nF 100nF
470K
C15
R9 220 330pF SL1 ( see Table 1) R8 C74 220 C57 100nF 330pF
+
C16 470nF
Reset
2
+
SPDIF IN
1
+
SDA SCL VDD18 VSS18 ADR_SEL HP_DET VDD18_CONV VSS18_CONV HL_LSS_R HP_LSS_L LS_SUB LS_R LS_L LS_C SCR_FLT SCL_FLT SC3_IN_R SC3_IN_L VDD33_CONV VSS33_CONV
SPDIF OUT
+
L4 C19 100nF TQFP80 IC1 STV82x7 or STV82x8
+3.3V
+ +
10H
+ C17 10F
C18 100nF
+
C46 1F
10F
+
+
R7 220 R6 220 C72 330pF C42 100nF R5 220 330pF R4 220 C71 + 10H L12 +8V C41 10F
C25 100nF
330pF
C44 100nF
+ +
+1.8V C26 100nF C27 100nF
C21
+
1.8V
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
C73
VSS18 VDD18 RST_N SPDIF_IN SPDIF_OUT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN/CLKXTP XTALOUT/CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO VDD33_IO I2S_PCM_CLK
+
VCC_NISO SC2_OUT_R SC2_OUT_L GND33_LS VCC33_LS SC2_IN_R SC2_IN_L VBG GND_SA VREFA SC1_IN_R SC1_IN_L GND33_SC VCC33_SC SC3_OUT_R SC3_OUT_L GND_H VCC_H SC1_OUT_R SC1_OUT_L
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
27pF
+
I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GND_PWIF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R
C22
XT1 27MHz CRYSTAL
C70 330pF C37 1F
+
1.8V
27pF
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
+ +
+
R 11
L6 100nF 10H + + L10
1.8V
C32 220nF C43 47F
10H
+ C23
+1.8V SIF C34 22nF C35 IRQ
47F
10K
C33
R3
560
10H
C29 100nF C30 100nF
L11 L11
Figure 9: STV82x7/STV82x8 Compatible Application Electrical Diagram (TQFP80)
Note 1 : components with * are only mandatory in case of Dolby certification
STV82x7
Note 2 : C35 value is 100 pF for STV82x7 and 150pF for STV82x8
+ +
+
+
+
+
+
+
20/156
Table 1 : SL1 configuration STV82x7 : between 2 and 3 (pin 20 connected to 3.3V) STV82x8 : between 1 and 2 (pin 20 connected to ground)
C8 1F C7 1F C6 1F C5 1F C4 1F C3 1F SC3 IN Right SC3 IN Left C61 1F C60 1F C59 47F L1 10H SC2 OUT Right SC2 OUT Left C56 10F C55 10F SC2 IN Right SC2 IN Left 100nF C51 10F C50 100nF C49 C53 1F C54 1F C52 C45 1F SC1 IN Right C47 10F C48 10F SC1 IN Left SC3 OUT Right SC3 OUT Left SC1 OUT Right SC1 OUT Left C38 1F R12 10K C36 1F SC4 IN Right SC4 IN Left Mono IN C40 10F C39 10F BUS EXPANDER I2S DATA 2 I2S DATA 1 I2S DATA 0 I2S LR CLK I2S SCLK I2S PCM CLK
LS Center
LS Left
LS Right
Subwoofer
HP Left/LS surround Left
HP Right/LS surround Right
STV82x7
System Clock
2
System Clock
The System Clock integrates 2 independent frequency synthesizers. The first frequency synthesizer can be used in one of two modes:
In Mode 1, it is used by the demodulator, and the frequecy is 49.152 MHz. In Mode 2, it is used by the I²S input and is synchronous with the input frequency (fS = 32, 44.1 or 48 kHz) and the frequency is 49.152 MHz (for fS = 32 or 48 kHz) or 45.1584 MHz (for fS = 44.1 kHz).
The second frequency synthesizer is used by the DSP core and can be adjusted between 100 and 150 MHz depending on the application (around 106 MHz at reset value). In I²S output mode, clocks are generated by synthesizer 1. The default values are designed for a standard 27 MHz reference frequency provided by a stable single crystal or an external differential clock signal (for example, from the STV35x0) depending on the CLK_SEL pin configuration (CLK_SEL = 1 means a single crystal, 0 means an external differential clock). The 27 MHz value is the recommended frequency for minimizing potential RF interference in the application. The sinusoidal clock frequency, and any harmonic products, remain outside the TV picture and sound IFs (PIF/SIF) and Band-I RF.
Note:
A change in the reference frequency is compatible with other default I²C programming values, including those of the built-in Automatic Standard Recognition System.
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Digital Demodulator
STV82x7
3
Digital Demodulator
The Digital Demodulator (see Figure 10) is composed of two channels. The first channel demodulates an FM or an AM signal. The second channel demodulates FM 2-carrier or NICAM signals (stereo demodulation). All channel parameters are programmed automatically by the built-in Automatic Standard Recognition System (Autostandard) in order to find the correct sound standard. Channels can also be programmed manually via the I²C interface for very specific standards not included among the known standards.
Figure 10: Demodulator Block Diagram
Chann el 1 = Mono Left AM Demodulator DCO1+ Mixer CAROFFSET1 (22h) Chan nel Filter FIR1 FM Demodulator AM
AM/FM Mono (To Sound Preprocessing) FML
AUTOSTD_STATUS (8Eh) SIF AGC Amp A/D AUTOSTD AGC Con tro l AGC_CTRL (0Eh) AGC_GAIN (0Fh) AUTOSTD_ TIMERS (8Dh) AUTOSTD_ CTRL (8Ah) AUTOSTD_ STANDARD_DETECT (8Bh) AUTOSTD_ STEREO_D ETECT (8Ch) FM Demodulator DC O2 + Mixer C hannel Filter FIR2 CAROFFSET2 (3Ah) Channe l 2 = Stereo/Mono Right DQPSK Demodulator NICAM Deco der Zweiton Decoder DEMOD_ STAT(0D h) ZWT_STAT (42h) NICAM_STAT(3 Fh)
FM Stereo (To Sound Preprocessing)
NICAM L NICAM R (To Sound Preprocessing)
3.1
Sound IF Signal
The Analog Sound Carrier IF is connected to the STV82x7 via the SIF pin. Before Analog-to-Digital Conversion (ADC), an Automatic Gain Control (AGC) is performed to adjust the incoming IF signal to the full scale of the ADC. A preliminary video rejection is recommended to optimize conversion and demodulation performances. The AGC system provides a gain value allowing for a wide range of SIF input levels and is activated for all standards, except L/L'. In this particular case, the sound carrier is AM-modulated and an automatic level adjustment would only damage the transmitted audio signal. A preset I²C parameter is provided to define the gain of the AGC used in Manual mode (Registers AGC_CTRL and AGC_GAIN).
Note:
For optimum AM demodulation performance, it is recommended to use the MONO Input.
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STV82x7
Digital Demodulator
3.2
Demodulation
The demodulation system operates by default in Automatic mode. In this mode, the STV82x7 is able to identify and demodulate any TV sound standard including NICAM and A2 systems (see Table 4) without any external control via the I²C interface. It consists of the two demodulation channels (Channel 1 = Mono Left and Channel 2 = Mono Right/Stereo) to simultaneously process two sound carriers in order to handle all transmission modes (stereo and up to three mono languages). The built-in Automatic Standard Recognition System (Autostandard) automatically programs the appropriate bits in the I²C registers which are forced to Read-only mode for users (see Section 12.1). The programming is optimized for each standard to be identified and demodulated. Each mono and stereo standard can be removed (or added) from the List of Standards to be recognized by programming registers AUTOSTD_STANDARD_DETECT and AUTOSTD_STEREO_DETECT, respectively. The identified standard is displayed in register AUTOSTD_STATUS and any change to standard is flagged to the host system via pin IRQ. This flag must be reset by re-programming the MSBs of register AUTOSTD_CTRL while checking the detected standard status by reading registers AUTOSTD_STATUS, NICAM_STAT and ZWT_STAT. Moreover, the detection of Stereo mode during demodulation is also flagged in register AUTOSTD_STATUS. Important: L/L' and D/K standards cannot be automatically processed because the same frequency is used for the MONO carrier. An exclusive L/DK selection must programmed in register AUTOSTD_CTRL. This may be externally controlled by detecting the RF modulation sign, which is negative for all TV standards except L/L'. To recover out-of standard FM deviations or the Sound Carrier Frequency Offset, additional I²C controls are provided without interfering with the Automatic Standard Recognition System (Autostandard). DK-NICAM Overmodulation Recovery: Four different FM deviation ranges can be selected (via register AUTOSTD_CTRL) for the DK standard while the Autostandard system remains active. The maximum FM deviation is 500 kHz in DK Mono mode and 350 kHz in DK NICAM mode (limited by overlapping FM and NICAM spectrum values). The demodulated signal peak level (proportional to the FM deviation) is detected by the Peak Detector and written to registers PEAK_DET_L and PEAK_DET_R. This value is used to implement Automatic Overmodulation Detection via an external I²C control. Important: Only the selection of the 50 kHz FM deviation standard is compatible with the other DKA2* standards (DK1, DK2 or DK3). These standards must be removed from the list of standards (registers AUTOSTD_STANDARD_DETECT and AUTOSTD_STEREO_DETECT) when programming larger FM deviations reserved only for DK-NICAM standards.
Table 4: Recognized Standards Type Name C a rri er 1 (M Hz) 5. 5 5. 5 A2 5. 5 6. 5 6. 5 A2* 6. 5 5.850 6.258 27 50 80 J 17 50 s 40 54. 6875 23/156 5.850 5.742 27 27 50 50 80 80 J 17 50 s 40 54. 6875 Carrier 2 (M Hz) Roll Pilot De-off Frequency emphasis (%) (kHz) Nom. Max. Over FM Deviation
S yst em
Sound Type
FM Mono B/G FM/NICAM FM 2-Carrier FM Mono D/K FM/NICAM D/K1 FM 2-Carrier
Digital Demodulator
Table 4: Recognized Standards (Continued) Type Name A2* A2* C a rri er 1 (M Hz) 6. 5 6. 5 6. 0 6. 0 6. 5 4. 5 A2+ 4. 5 4.724 6.552 5.850 15 15 27 27 50 50 27 50 80 J 17 J 17 75 s 75 s 100 40 Carrier 2 (M Hz) 6.742 5.742
STV82x7
S yst em
Sound Type
Roll Pilot De-off Frequency emphasis (%) (kHz) Nom. Max. Over 50 s 50 s 54. 6875 54. 6875
FM Deviation
D/K2 D/K3 I
FM 2-Carrier FM 2-Carrier FM Mono FM/NICAM
L M/N
AM/NICAM FM Mono FM 2-Carrier
55.069
For Chinese TV transmissions (DK-NICAM) which are subject to overmodulation, different FM deviations are proposed for sound demodulation. Sound Carrier Frequency Offset Recovery: Both Mono and Stereo IF Carrier frequencies can be adjusted independently (registers CAROFFSET1 and CAROFFSET2) within a large range (up to 120 kHz for standard mono FM deviations) while the Automatic Standard Recognition System remains active. The frequency offset estimation is written in registers DC_REMOVAL_L and DC_REMOVAL_R (Mono Left / Channel 1 and Mono Right / Channel 2, respectively) and can be used to implement the Automatic Frequency Control (AFC) via an external I²C control. Manual Mode: If required, the Automatic Standard Recognition System system can be disabled (Manual mode) and the user can control all registers including those only controlled by the Automatic Standard Recognition System function when active. Manual mode is selected in register AUTOSTD_STANDARD_DETECT (bit LDK_SCK, I_SCK, BG_SCK and MN_SCK set to 0).
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STV82x7
Dedicated Digital Signal Processor (DSP)
4
Dedicated Digital Signal Processor (DSP)
A dedicated Digital Signal Processor (DSP) takes charge of all audio processing features and the low frequency signal processing features of the demodulator. The internal 24-bit architecture will ensure a high quality signal treatment and an excellent dynamic.
4.1
Back-end Processing
The "back-end" processing corresponds to the low frequency signal processing (32 kHz or higher frequencies) of the demodulator and other inputs (I²S, ADC). Figure 11 shows a flowchart of the back-end processing tasks. However, the figure shows that the processing is only a SINGLE SOURCE PROCESSING flow (no processing is possible with "Demod + SCART" and I²S inputs simultaneously) and that the selection of a headphone output restricts the loudspeakers configuration to 2+1 instead of 5+1.
Figure 11: Back-end Audio Processing
"Demod + SCART" or "SCART only" Input Modes
Autostandard
FM Channel1 FM Channel2
DC Removal Ste re o Peak Detector: 9D, bit 7 = 1
FM De-emph asis
FM Prescale
FM De matrix Stereo Peak Detector: 9D, bit 7 = 0
2
LS
Digital Audio Matrix
(L and R)
NI CAM L NICAM R
DC Removal
NICAM De-emph asis
NICAM Presca le
NICAM Dematrix
2
HP
(L and R)
2
SC ART
(L and R)
SCART L SCART R
DC Removal
SCART Prescale
Ste reo Peak Detector: 9D, bit 7 = 1
Stereo Peak Detector: 9D, bit 7 = 0
"I2S" Input Mode
I2S in 1 I2S in 2 I2S in 3
2 to 6
LS
(L,R,C,LFE,Ls, Rs)
SRC X2/X4
I ²S Prescale
DownMix
2
HP
(L and R)
2
SC ART
(L and R)
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Dedicated Digital Signal Processor (DSP)
The main features depend on the path:
STV82x7
FM Channel -- DC Removal -- Prescaling -- De-emphasis (50 or 75 us) -- Stereo Dematrix
NICAM Channel -- DC Removal -- Prescaling -- De-emphasis (J17) -- Dem atrix
Input SCART Channel -- DC Removal -- Prescaling
Input I²S Channel -- I²S Prescaling Digital Audio Matrix -- Audio Channel Multiplexer between the different sources (IF, I²S, SCART) towards all outputs (S/PDIF, LS, HP or SCART).
Autostandard management -- device configuration depending on the standard to be detected -- freeze the device when a standard is detected -- once a standard detected, check that there is no change in the detection status -- set the correct action depending on any change in the detection status (mono backup or mute setup and new standard detection)
SCART -- Downmixing: LT / RT or L0 / R0 (see AC-3 specification) -- Soft Mute
4.2
Audio Processing
The following software is provided for main loudspeakers (L, R, C, LS, RS, SubW):
Downmix ST WideSurround, ST OmniSurround, SRS WOWTM or SRS TruSurround XT (certified
Virtual Dolby Surround and Virtual Dolby Digital)
ST Dynamic Bass Sm ar t Volume Control (SVC) 5-band Equalizer or Bass-Treble Loudness Volume with independent channels (Smooth Volume Control) Master Volume Control Mute/soft-mute
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Dolby
Pro Logic II Decoder (LT, RT L, R, C, Ls, Rs, SubW) with Bass Management
STV82x7
Dedicated Digital Signal Processor (DSP)
Balance Beeper Pink Noise Generator (used to position the loudspeakers) Programm able Delay for each loudspeaker Adjustable Delay for "lip sync" to compensate audio/video latency up to 60 ms in SCART Only Mode (processing at 48 KHz) and up to 90 ms in Demodulator and SCART Mode (processing at 32 KHz)
The following software is provided for the headphone or auxiliary output:
Downmix Sm ar t Volume Control (SVC) Bass/Treble Loudness Independent Volume for each channel (Smooth Volume Control) Soft Mute Balance Beeper Adjustable Delay for "lip sync" up to 120 ms (to compensate audio/video latency) in SCART Only Mode and up to 180 ms in Demodulator and SCART Mode
The following software is provided for SCART or S/PDIF outputs:
Downmix Soft Mute
SRS
TruBassTM
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IF
I2S
Audio Matrix for Demod/SCART input DownMix for I2S inputs L 90ms / R 60ms C LFE Ls Rs Decoder 2 to N Dolby Prologic I
SCART
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AutoStd L SCART FM Dematrix R SCART DC Removal FM FM Deemphasis Prescale DC Removal NICAM NICAM Deemphasis Prescale NICAM Dematrix SRC x2 x4 I2S Prescale L R C LFE Ls Rs L R C Ls Rs Virtualiser N to 2 L R C Ls Rs L HP L SRS TruSurround XT R ST Wide Surround L HP 90ms / R HP 60ms R HP DC Removal SCART Prescale
Dedicated Digital Signal Processor (DSP)
Figure 12: STV82x7 Audio Processing Flowchart (Front End)
Peak Detector Noise Generator
L R C LFE Ls Rs
STV82x7
STV82x7
S/PDIF Copy
Digital Soft Mute S/PDIF Output
L SCART Volume Digital Balance Soft Mute SCART Output L R TruBass XT Bass / Treble or 5 bands Equalizer Volume Digital Balance Soft Mute
R SCART
S
LS Output
C Loudness Bass Mgmt Volume
Volume
Digital Soft Mute
Center Output
LFE
2/0 and 3/2 SVC
Digital Soft Mute
Subwoofer Output
Ls Rs
L HP R HP TruBass XT SVC Bass/ Treble
Loudness
Digital Volume Soft Balance Mute
S
Beeper
Figure 13: STV82x7 Audio Processing Flowchart (Back End)
Headphone Output
Output Select I2S Out Select
Dedicated Digital Signal Processor (DSP)
Digital Volume Soft Balance Mute
Surround Output
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Dedicated Digital Signal Processor (DSP)
STV82x7
4.3
ST WideSurround
STV82x7 offers three preset ST WideSurround Sound effects on the Loudspeakers path:
Music, a concert hall effect Movie, for films on TV Simulated Stereo, which generates a pseudo-stereo effect from mono source
"ST WideSurround Sound" is an extension of the conventional stereo concept which improves the spatial characteristics of the sound. This could be done simply by adding more speakers and coding more channels into the source signal as is done in the cinema, but this approach is too costly for normal home use. The ST WideSurround system exploits a method of phase shifting to achieve a similar result using only two speakers. It restores spatiality by adding artificial phase differences. The Surround/Pseudo-stereo mode is automatically selected by the Automatic Standard Recognition System (Autostandard) depending on the detected stereo or mono source. By default, "Movie" is selected for Surround mode. This value may be changed to "Music" by the STSRND_MODE bit in the STSRND_CONTROL register. Additional user controls are provided to better adapt the spatial effect to the source. The ST WideSurround Gain (STSRND_LEVEL) and ST WideSurround Frequency (STSRND_FREQ) registers can be used to enhance Music Predominancy in Music mode and Theater effect and Voice Predominancy in Movie mode.
4.4
ST OmniSurround
STV82x7 offers a spatial virtualizer to output any multi-channel input in stereo on the Loudspeakers path: "ST OmniSurround" will recreate a multi-channel spatial sound environment using only the Left and Right front speakers. It can be adapted to any input configuration (OMNISRND_INPUT_MODE). ST Voice will allow you to enhance the voice content of your program to increase the intellegibility and the presence of the sound.
4.5
Dolby Pro Logic II Decoder
Dolby Pro Logic II is a matrix decoder that decodes the five channels of surround sound that have been encoded onto the stereo sound tracks of Dolby Surround program material such as DVD movies and TV shows. It is even possible to decode standard stereo signals like music or non encoded movies. Furthermore, it is an active process designed to enhance sound localization through the use of very high-separation decoding techniques. The Dolby Pro Logic II decoder is also able to emulate the former Dolby Pro Logic decoder in a specific mode.
4.6
Bass Management
This processing will generate the subwoofer signal and adjust all loudspeakers channels gain and bandwidth. Speakers capable of reproducing the entire frequency range will be referred to as "full range speakers", then signals sent to full range speaker will be full bandwidth (no filtering).
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STV82x7
Dedicated Digital Signal Processor (DSP)
Speakers that have limited bass handling capabilities will be referred to as "satellite speakers", then signals sent to satellite speaker will be high-pass filtered to remove bass information below 100 Hz. In the STV82x7, five output configuration modes have been implemented according to "Dolby Digital Consumer Decoder" specifications. They are described below.
4.6.1
Bass Management Configuration 0
In some cases, the bass management filters are available in the decoder itself, so there is no need to reproduce these filters. The output configuration shown in Figure 14 offers this possibility.
Figure 14: Bass Management Configuration 0 (with Pro Logic switch indicating its reset state) L L
R
R
C Pro Logic OFF Switch Ls
C
Ls
Rs -15 dB LF E -5 dB +
Rs
S ub W
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Dedicated Digital Signal Processor (DSP) 4.6.2 Bass Management Configuration 1
STV82x7
Configuration 1, shown in Figure 15, assumes that all five speakers are not full range and that all of the bass information will be redirected to and reproduced by a single subwoofer. This configuration is intended for use with 5 satellite speakers. To prevent signal overload, the five main channels are attenuated by 15 dB, while the LFE channel is attenuated by 5 dB to maintain the proper mixing ratio.
Figure 15: Bass Management Configuration 1 (with Pro Logic switch indicating its reset state) L
L
R
R
C Pro Logic OFF Switch Ls
C
Ls
Rs -15 dB LFE -5 dB +
Rs
S ubW
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STV82x7 4.6.3 Bass Management Configuration 2
Dedicated Digital Signal Processor (DSP)
Configuration 2 assumes that the left and right speakers, are full range while the center and surround speakers are smaller speakers. Also, all bass data is redirected to the left and right speakers. This configuration include output level adjustment that allows 12 dB attenuation for the 3 smaller speakers (C, Ls, Rs). When the level adjustment will be disabled the decoder boosts by 12 dB the full range speakers (Left, Right).
Figure 16: Bass Management Configuration 2 (all switches indicate their reset state)
Level Adjustment OFF Switch L -12 dB + -1.5 dB C -12 dB C R +12 dB -1.5 dB -12 dB Ls + -12 dB Rs -15 dB LFE -5 dB + S ubW Rs Subwoofer ON Switch Ls L +12 dB
R Pro Logic OFF Switch
-12 dB
+
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Dedicated Digital Signal Processor (DSP) 4.6.4 Bass Management Configuration 3
STV82x7
The third configuration, shown in Figure 17, assumes that all speakers except the center are full range, then all bass information will be directed to and reproduced by the front left and front right and both surround speakers. In order to provide more flexibility to this configuration, a switch will offer an option which will produce a subwoofer channel by the LFE channel. When the Subwoofer Switch is OFF, the input channels will be attenuated by 8 dB. Configuration 3 is required in certain high-end products.
Figure 17: Bass Management Configuration 3 (all switches indicate their reset state) Level Adjustment OFF Switch + L
L
-8dB -4dB
+
+ 8dB + 4dB + 8dB +4dB
C
C
-8dB -4dB -4.5 dB
R
-8dB -4dB
+
+
R +8 dB + 4dB + +8 dB + 4dB + +8d B + 4dB Rs Ls
Ls
-8dB -4dB -8d B -4d B
Rs
LFE
-8dB -4dB Subwoofer ON Switch Subwoofer ON Switch +10dB SubW
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STV82x7 4.6.5 Bass Management Configuration 4
Dedicated Digital Signal Processor (DSP)
This configuration implements the Simplified Dolby configuration. The center, left surround and right surround channels are summed and then filtered by the LPF. The composite bass information is either summed back into the left and right channels or summed with the LFE channel and sent to the subwoofer output, see Figure 18.
Figure 18: Implementation of the Bass Management Configuration 4 (Simplified Configuration)
L
+
L
C
C
R Pro Logic OFF Switch Ls
+
R
Ls
Rs -4.5dB Subwoofer ON Switch
Rs
+
-10.5dB -5dB +
LF E
S ubW
4.7
SRS WOW and TruSurround XT
The SRS TruSurround XTTM is a processing system that can accept from 1 to 6 channels on input and that will generate a 2-channel output signal. This processing system includes the latest SRS algorithms:
SRS
4.7.1
SRS TruSurround
The SRS TruSurround is a processing that can accept from 2 to 5 channels on input and that will generate a 2-channel output signal. SRS TruSurround uses Head-Related Transfer Function (HRTF) -based frequency tailoring of (L/R) difference signals to extend the sound image out past the physical boundaries of the speaker placements to surround channel information. These rear channel HRTF curves have much greater peak to valley differences at center frequencies. These were chosen to cause rear channel difference signals to virtualize farther behind the listener and directed to a different virtual position as compared to front channel signals. Information that is equal (L+R) in the rear surround channels
SRS
WOWTM TruSurround (Multi-channel signal virtualizer)
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Dedicated Digital Signal Processor (DSP)
STV82x7
is processed by an identical HRTF curve but mixed in at a much lower amount. This HRTF processing of equal (L/R) signals was again used to virtualize information to the rear of the listener. The SRS TruSurround is certified by Dolby Laboratories to be a Virtual Dolby Digital and Virtual Dolby Surround.
4.7.2
SRS WOW
The SRS WOWTM is an a sound processing system including:
SRS SRS
4.7.2.1 SRS 3D Mono/Stereo This system is used to create a pseudo-stereo signal for mono inputs or a three-dimensional spatial signal for stereo inputs. 4.7.2.2 SRS Dialog Clarity This system is used to enhance dialog perception. 4.7.2.3 SRS TruBass The SRS TruBassTM audio enhancement technology provides deep, rich bass to small speaker systems without the need for a subwoofer or additional extra physical components. For systems with a subwoofer, TruBassTM complements and enhances bass performance. Psycho-acoustically, when the human ear is presented with a low frequency sound signal that is missing the fundamental harmonic, it will fill in the fundamental frequency based on the higher harmonics that are present. By accentuating the second and higher frequency harmonics of the bass portion of a signal, TruBassTM gives the perception of greatly improved bass response.
4.8
Smart Volume Control (SVC)
The Smart Volume Control regulates the audio signal level before audio processing. This regulation is necessary in order for the signal level to be independent from the source (terrestrial channels, I2S or SCART), its modulation (AM, FM or NICAM) and annoying volume changes (advertising, etc.). The Smart Volume Control works as an audio compressor/expander; i.e. when the input signal exceeds the threshold level, a very rapid attenuation (-2 dB/ms) is applied to rescale the signal down to the threshold value. When the input signal is below the threshold level, the previous attenuation is reduced slowly in order to retrieve the original input level (0 dB gain). If the input signal is too low, an addition gain of 6 dB can be provided. To personalize the action of the SVC, five parameters are available: 1. Threshold: Maximum quasi-peak level that can be expected on output 2. Peak measurement mode: Select the channel on which the peak measurement must be performed (Left, Right, Center...) 3. Release time: Gain slope applied to the amplification phase 4. Expander switch: To allow a +6dB amplification of small signals in order to reduce the output dynamic range 5. Make up gain: Allows compensation of the signal amplitude limitation thanks to a 0 to 24 dB adjustable gain.
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S RS
TruBassTM is implemented on loudspeakers path, headphone path or on both in parallel.
SRS
3D Mono/StereoTM Dialog ClarityTM TruBassTM
STV82x7
Dedicated Digital Signal Processor (DSP)
The SVC is implemented on the loudspeakers path, headphone path or on both in parallel (independent settings). Also, the SVC can be applied in six-channel mode (L, R, LS, RS, C and SubW).
4.9
ST Dynamic Bass
STV82x7 offers dynamic bass boost processing on the Loudspeakers path: ST Dynamic Bass is a bass boost process that can dramatically increase the bass content of any program without any output level saturation. 3 cutoff frequencies (BASS_FREQ) can be chosen, 100 Hz, 150 Hz and 200 Hz to adapt the effect to your loudspeakers. The amount of bass (BASS_LEVEL) can also be fine tuned in order to adapt the effect loudness.
4.10
5-Band Audio Equalizer
The loudspeakers audio spectrum is split into 5 frequency bands and the gain of each of band can be adjusted within a range from -12 dB to +12 dB in steps of 0.25 dB. The Audio Equalizer may be used to pre-define frequency band enhancement features dedicated to various kinds of music or to attenuate frequency resonances of loudspeakers or the listening environment. The Equalizer is enabled by the LS_EQ_ON bit in the LS_EQ_BT_CTRL register. The gain value for Band X is programmed in register EQ_BANDX_GAIN. The 5-Band Audio Equalizer is exclusive with Bass-Treble control. Bit LS_EQ_BT_SW in register LS_EQ_BT_CTRL is used to select either the 5-Band Audio Equalizer or the Bass-Treble control for the Loudspeakers path. Depending on the LS Equalizer or LS Bass-Treble value, the volume level can be clamped to the LS output to prevent any possible signal clipping from occuring using the ANTICLIP_LS_VOL_CLAMP bit in the VOLUME_MODES (D7h) register.
Figure 19: Equalizer f1 = 100 Hz, f2 = 330 Hz, f3 = 1 kHz, f4 = 3.3 kHz and f5 = 10 kHz
4.11
Bass/Treble Control
The gain of bass and treble frequency bands for Headphone can be also tuned within a range from -12 dB to +12 dB in steps of 0.25 dB. It may be used to pre-define frequency band enhancement features dedicated to various kinds of music. The Headphone Bass/Treble feature is enabled by setting the HP_BT_ON bit in the HP_BT_CONTROL register. The Bass and Treble gain values are adjusted in registers HP_BASS_GAIN and HP_TREBLE_GAIN, respectively. Depending on the HP Bass-Treble value, the volume level can be clamped to the HP output to prevent any possible signal clipping from occuring using the ANTICLIP_HP_VOL_CLAMP bit in the VOLUME_MODES (D7h) register.
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Dedicated Digital Signal Processor (DSP)
STV82x7
4.12
Automatic Loudness Control
As the human ear does not hear the audio frequency range the same way depending on the power of the audio source, the Loudness Control corrects this effect by sensing the volume level and then boosting bass and treble frequencies proportionally to middle frequencies at lower volume. While maintaining the amplitude of the 1 kHz components at an approximately constant value, the gain values of lower and higher frequencies are automatically progressively amplified up to +18 dB when the audio volume level decreases.The maximum treble amplification can be adjusted from 0 dB (first order loudness) to +18 dB (second order loudness) in steps of 3 dB. As the volume is proportional to the external audio amplification power, the loudness amplification threshold is programmable in order to tune the absolute level. The Loudspeakers Loudness function is enabled by setting the LS_LOUD_ON bit in register LS_LOUDNESS. The Loudspeakers Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The Headphone Loudness function is enabled by setting the HP_LOUD_ON bit in register HP_LOUDNESS. The Headphone Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The loudness cut-off frequency is 100 Hz.
4.13
Volume/Balance Control
The STV82x7 provides a Volume/Balance Control for all output channels configuration (except for S/PDIF) with different volume level per channel (L, R, C, LS, R S, SubW, SCART). Its wide range (from +11.875 to -116 dB, in a dB linear scale with a 0.125 dB step) largely covers typical home applications (approx. 60 dB) while maintaining a good S/N ratio.
Figure 20: Volume Control
Output Gain
+11.875 dB
-116 dB M ut e 00h I²C Control 3FFh
An extra Master Volume Control can apply an extra gain/attenuation on L, R, C, LS, R S and SubW channels. The Volume/Balance Control can operate in one of two different modes:
In Differential mode (default value), the volume control is a common volume value for both the Left and Right Loudspeakers or Headphone channels (see Figure 20) and complimentary balance control is used (see Figure 21).
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STV82x7
Dedicated Digital Signal Processor (DSP)
In Independent mode, the volume for the Left and Right channels for Loudspeakers or Headphone is controlled independently.
Figure 21: Differential Balance
Output Gain
10 0%
nn el Le ha C ft tC
ha
ig h
nn
R
el
Mute 200h 000 h I²C Control (10 bits) 1FFh
Note:
Each step is 0.25 dB
4.14
Soft Mute Control
The Digital Soft Mute is applied smoothly (20 ms for 120 dB range) to avoid any switch noise on output. It is available on all output channels pairs:
S/PDIF channel (Left/Right) SCART channels (Left/Right) Loudspeakers channels (Left/Right) Center Subwoofer Headphone/Surround channels (Left/Right)
Another soft mute (analog) is also available on each DAC output.
4.15
Beeper
The beeper is used to generate a tone on the Loudspeakers or/and Headphone outputs. The beeper sound (square wave) is added to the audio signal which is attenuated by 20 dB. The beep sound amplitude includes a smooth attack and decay to avoid any parasitic noise when starting and stopping. It can be used for various applications such as beep sounds for remote control, alarm clock or other features. The Beeper operates in one of two modes:
Pulse mode (beep applications): A tone with a programmable short duration (0.1, 0.25, 0.5 and 1.0 s) is generated. Afterwards, the beeper is automatically disabled and the output is switched back to the audio signal, see Figure 22. Continuous mode (alarm application): A tone with a programmable long duration is generated. Its start and stop controls must be programmed by I²C, see Figure 23.
The Beeper function is enabled by setting the BEEPER_ON bit in register BEEPER_ON. Beeper parameters are controlled in register BEEPER_MODE.
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Dedicated Digital Signal Processor (DSP)
STV82x7
The beeper tone level and frequency are programmed in register BEEPER_FREQ_VOL. The level (or volume) ranges between 0 dB and -93 dB in steps of 3 dB and the tone frequency ranges between 62.5 Hz and 8 kHz in steps of 1 octave. A beep generator is shared only by the Loudspeakers or Headphone outputs. Therefore, in the event of simultaneous beeps when in Pulse mode, only the first beep will define the effective duration that will be the same for both outputs.
Figure 22: Pulse Mode
BEEP_ON = 1
BEEP_ON = 0
0.1, 0.25, 0.5 and 1.0 s T predefined
62.5 H z < f < 8 kHz
Figure 23: Continuous Mode
BEEP_ON = 1 T defined by I²C write
BEEP_ON = 0
62.5 Hz < F < 8 kHz
4.16
Internal Audio/Video Delay (Lip Sync)
Since increasing processing on the video signal implies more delay compared to the audio signal, there is a possibility inside the device of compensating by inserting a delay on the audio path in order to resynchronize the two signals:
60ms with 48 KHz sampling frequency (SCART only input mode) 90ms with 32 KHz sampling frequency (demodulator input mode)
The same delay is available for the LS path and/or the HP path.
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STV82x7
Analog Audio Matrix (In / Out)
5
Analog Audio Matrix (In / Out)
The analog part of the audio matrix can be divided into two parts: the SCART input matrix and the SCART output matrix.
Figure 24: SCART Input Matrix
S1in S2in S3in S 4i n MONO_in Select
Audio ADC 2
Digital Matrix
The SCART input matrix is an input for the digital matrix (after the ADC) which select which source will be sent to the DSP.
Figure 25: SCART1/2/3 Output Matrix
S1in S2in S3in S4in Stereo DAC MONO_in
2 Soft mute S 1out
Select or Mute
The SCART output matrix selects the sound to output, which can be directly a SCART input or the output of the DSP. A mute function is provided to switch off the outputs. A soft-mute function is provided to avoid all spurious sounds when switching from one position to another position. The SCART 2 and 3 output matrices have the same functions as the SCART 1 output matrix. The particularity of the matrix is to accept input signal of 2 VRMS and to have the capability to output such level. In this case, the power supply must be 8 V. The Mono audio input is able to accept signals with a 0.5 VRMS amplitude.
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I²S Interface (In / Out)
STV82x7
6
I²S Interface (In / Out)
The STV82x7 offers three input/output choices: one I²S input, three I²S inputs or one I²S output.
6.1
I²S Inputs
The STV82x7 can interface with a digital sound decoder. In this case, the digital data can be input at a speed of 0.384 Mbytes/s (3.072 MHz for a 48 kHz sampling frequency with 32 bits of data).In compliance with Dolby specifications, only the sampling frequency is subject to restrictions. All other requirements are extracted from other various specifications.
Table 5: I²S Characteristics
Sampling Frequency (kHz) Data Size PCMCLK 8, 11.025, 12,16, 22.05, 24, 32, 44.1 and 48 16, 18*, 20*, 24*, 32 512 x fS1 2
1. means that the number is the number of effective bits but the transmission is with 32 bits. 2. 512 x fs is used by the DACs if 512 x fs is present.
The PCMCLK (possible clock for upsampling) is provided by the master which is the digital sound decoder. A sample rate conversion (SRC) will be necessary in the second case (STV82x7 slave) in order to have a fixed frequency output from this block (either 32 kHz, 44.1 kHz or 48 kHz).
Note:
The SRC function is only available in single I²S input mode.
The I²S interface is used in two ways depending on the package: 1. The interface with one I²S (I²S_DATA0) connection (only stereo or stereo-coded Dolby Pro Logic); 2. One interface with three I²S connections connected to the DSP to allow the processing of a multi-channel signal (maximum of 6 channels).
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STV82x7
I²S Interface (In / Out)
Figure 26: I²S Block Diagram
I²S_DATA0 fS Input = 8 to 48 kHz
SRC x 2
SRC x 4
I²S_DATA1 fS Input = 32 to 48 kHz I²S_DATA2 fS Input = 32 to 48 kHz I2S_SCLK fS Input * 64 I2S_LR_CLK fS Input = 32 to 48 kHz
Audio Processing
Note: 1 The I²S input and output modes are exclusive (this means that the I2S_DATA0 can be used as input or as output). 2 Simultaneous processing of I²S inputs and SIF inputs and/or ADC inputs (SCART or MONO inputs) is NOT possible with the device. 3 I2S_PCM_CLK is not needed for the device.
Table 6: I²S Frequency Configuration I²S (Max. Number of Channels)
1 (I²S_DATA0) 1 (I²S_DATA0) 3 1 (I²S_DATA0) 1 (I²S_DATA0) 3 1 (I²S_DATA0) 1 (I²S_DATA0) 3
fS Input (kHz)
8 16 32 11.025 22.05 44.1 12 24 48
fS Output (kHz) after SRC
32.0 32.0 32.0 44.1 44.1 44.1 48.0 48.0 48.0
SRC Use
x4 x2 No x4 x2 No x4 x2 No
Both standard and non-standard modes are available, see Figure 29.
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I²S Interface (In / Out)
STV82x7
6.2
I²S Output
A digital stereo output (I²S compatible) is also available for routing the demodulated signal or a converted input audio signal to an external device. In this case, the I2S_DATA0 signal and all clock signals are set as outputs by setting bit D6 in register RESET to 1. The STV82x7 I²S drives the serial bus (SCLK, LR_CLK, I²S_DATA0) in master mode in 64.fs format with a sampling frequency (fs) of 32 kHz. The I²S_PCM_CLK signal can be used as a master clock in 512.fs format if required for the slave interface. Both standard and non-standard modes are available, see Figure 29.
Figure 27: TQFP 80 I²S Output Block Diagram
I2S_DATA0 fS Output = 32 kHz I 2S _S C LK fS Output * 64 I2S_LR_CLK fS Output = 32 kHz I2S_PCM_CLK fS Output * 512 Audio Processing
48 kHz DSP
Processing
Note:
The I²S input and output modes are exclusive (this means that the I2S_DATA0 can be used as input or as output).
Figure 28: I²S Output Selection
LS Output C/Sub Output I2S_DATA0 Sr nd/HP Output SCART Output Register 56h: Bits[7:6]
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STV82x7
I²S Interface (In / Out)
Figure 29: I²S Data Format: Lch = LOW, Rch = HIGH (I²S Input or Output mode)
1/f s L ch
I²S_LR_ CLK
Rc h
I²S_SCLK (= 64fs)
I²S_DATAx (stand ard mode)
1
2
3
22
23
24
1
2
3
22
23
24
1
2
MSB I²S_DATAx (n on-sta ndard mode) 1 2 3 22 23 24
LSB 1 2
MSB 3 22 23 24
L SB 1 2 3
MSB
LSB
MSB
L SB
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S/PDIF Input/Output
STV82x7
7
S/PDIF Input/Output
An S/PDIF output is available for connection with an external A/V decoder/amplifier. The signal on this S/PDIF output is selected by an on chip Multiplexer between the internal signal and an external signal present on S/PDIF bypass input (Pin 44) with SPDIF_MUX bit in the DAC_CONTROL register. The outputted internal signal can be selected from:
L/R C/Subwoofer HP or Surround L/R SCART L/R
The external signal is for example the signal provided by an external Dolby Digital decoder (STD2000). Mute facility is also provided on the S/PDIF output.
Note:
The S/PDIF_IN pin (Pin 44) is a CMOS digital pin and input signals on this pin must fulfill the characteristics as mentioned in Section 13.12: Digital I/Os Characteristics on page 144 (0.5 VPP standard S/PDIF input level is not directly supported by the device and needs external circuitry).
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STV82x7
Power Supply Management
8
Power Supply Management
A mixed supply voltage environment requires the following voltages:
3.3 V capable inputs/outputs for digital pins; 1.8 V digital core; 8 V capable inputs/outputs for analog audio interfaces (capability to output 2 V RMS for SCART requirements); 3.3 V for stereo ADC and DAC (analog part); 1.8 V for stereo ADC and DAC (digital part); 1.8 V for IF ADC and AGC.
These voltages will be delivered by the application with an accuracy of 5%. For more information, refer to Section 13.3: Power Supply Data. Other specific DC voltages or features are provided:
Voltage Reference and Biasing Generation (AGC, ADCs, DACs), Bandgap reference.
8.1
Standby Mode (Loop-through mode)
The STV82x7 provides a Loop-through mode configuration that bypasses IC functions via a SCART I/O pin (Full Analog Path only). In this case, only a minimum power of 200 mW is required. In Standby mode, the digital and analog power supplies are switched off, except for pins VCC_H, VCC33_LS, VCC33_SC, and VCC_NISO which are used to maintain the SCART path with the last configuration programmed by analog matrixing (register SCART1_2_OUTPUT_CTRL and SCART3_OUTPUT_CTRL). When switching back to normal Full Power mode, all I²C registers are reset except for those used in Standby mode to maintain the original configuration. In Standby mode, the I²C bus does not operate. However, the bus can still be used by other ICs since the I²C I/O pins (SDA and SCL) of the STV82x7 are forced into a high-impedance configuration.
8.2
Power on Reset
The following supply voltages are involved for Power on Reset for the STV82x7:
for 1.8 V: VDD18 on pins 38, 42, 50 and 66, VCC18_CLK1 on pin 54 and VCC18_CLK2 on pin 57. for 3.3 V: VDD33_IOI on pin 46 and VDD33_IO2 on pin 59.
The first condition for a valid reset is that all 1.8 V supply voltages involved have reached a minimum valid voltage of 1.7 V and that all 3.3 V supply voltages involved have reached a minimum valid voltage of 3.1 V. When this is the case and starting from this point, the reset must be maintained at a low level (<1 V) for at least 100 s then put to a high level.
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Additional Controls and Flag
STV82x7
9
Additional Controls and Flag
This logic contains:
the headphone detection, the IRQ generation, signal to be output to the MCU, the I²C bus expander output pin.
9.1
Headphone Detection
For headphone, the HP_DET input can be used to automatically mute the Loudspeakers and Subwoofer outputs when the HP_LS_MUTE bit is set in register HEADPHONE_CONFIG (active low). When a headphone is detected (the HP_DET pin is set to 0) and the Mute function is enabled. Each change on the HP_DET pin generates an IRQ request to the microprocessor on the IRQ pin.
9.2
IRQ Generation
Four IRQs are generated by the STV82x7. On each IRQ generation, the IRQ pin is set to 1. The pending IRQ status must be read at the I²2S address 81h and the acknowledge is done by writing 0 to this register. The four availables IRQs are: IRQ0: The identified TV sound standard is displayed in register AUTOSTD_STATUS. Each change in the detected standard is flagged to the host system via hardware pin IRQ. The flag must be reset by re-programming the IRQ bit in register AUTOSTD_CTRL and then checking the detected standard status by reading registers AUTOSTD_STATUS, NICAM_STAT, and ZWT_STAT. IRQ1: This IRQ is enabled only in digital input mode. In case of I2S synchronisation loss, this IRQ is set to 1. IRQ2: This IRQ is set to 1 when the device detects any change on the HP Detection pin (Headphone connection or deconnection). IRQ3: On the STV82x7, same pins are used for both Headphone and Surround loudspeaker signal output. A change in the Headphone configuration (HP active or not active) will lead to a signal switch on those hardware pins. In order to ensure a smooth audio transition, the output is soft muted before the signal is switched. The IRQ3 is then set to 1 to advise the master processor that the signal has been switched and to request a HP/Srnd Ouput Un-Mute.
9.3
I²C Bus Expander
Pin BUS_EXP can be used to control external switchable IF SAW filters or audio switches. This pin can be directly programmed by register RESET.
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STV82x7
STV82x7 Reset
10
STV82x7 Reset
All STV82x7 features are controlled via the I²C bus. The STV82x7 can be "reset" in 2 ways: 1. By Software via the I²C bus: This clears all synchronous logic, except for the I²C bus registers. 2. By Hardware via the RESET pin: In addition to clearing all synchronous logic, the RESET input (active on the low level) resets all the I²C bus registers to the default values listed below.
Table 7: RESET Default Values Function
Demodulation Auto-standard Scanned Standards FM Deviation Audio Outputs Automatic Mute Mode Loudspeaker Source Loudspeaker Volume Loudspeaker L/R Balance Subwoofer Headphone Source Headphone Automatic Detection Headphone Volume Headphone L/R Balance SCART-1 out SCART-2 out SCART Volume I²S out Audio Processing Loudspeaker/Headphone SVC Loudspeaker Surround Loudspeaker 5-Band Equalizer Loudspeaker Loudness Headphone Bass/Treble Loudspeaker/Headphone Beeper OFF, 0 dB Reference Value OF F OFF, 0 dB (Flat Band) OFF OFF, 0 dB (Flat Band) -40 dB / OFF ON Demodulated Sound -40 dB, differential mode, muted L/R = 100% -40 dB / OFF Demodulated Sound ON -40 dB, differential mode, muted L/R = 100% Demodulated Sound SCART1 Source -5.5 dB, independent mode, muted OF F ON M/N, B/G, I, L/L' 125 kHz (Max.)
Default mode
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I²C Interface
STV82x7
11
11.1
I²C Interface
I²C Address and Protocol
The STV82x7 I²C interface works in Slave mode and is fully compliant with I²C standards in Fast mode (maximum frequency of 400 kHz). Two pairs of I²C chip addresses are used to connect two STV82x7 chips to the same I²C serial bus. The device address pairs are defined by the polarity of the ADR_SEL pin and are listed in the following table:
Table 8: I²C Read/Write Addresses ADR
LOW (connected to GND1) HIGH (connected to VDD1)
Write Address (W)
80h 84h
Read Address (R)
81h 85h
Protocol Description
Write Protocol
Star t W A Sub-address A Data A .... A Dat a A St o p
Read Protocol
Star t W A Sub-address A Stop Star t R A Data A .... A Da t a N
W = Write address, R = Read address, A = Acknowledge, N = No acknowledge, Sub-address is the register address pointer; this value auto-increments for both write and read.
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STV82x7
I²C Interface
11.2
Start-up and Configuration Change Procedure
The DSP running loop is:
Read IC registers and update internal structures (memory variables) Process sound samples Write I²C registers with new updated values
The step "process sound sample" duration is 1ms. This is shown in Figure 30.
Figure 30: Simplified DSP Processing Flow
Load Patch File
HW_RESET bit = 1 (bit 2 in HOST_CMD register)
(DSP RUN)
INIT_MEM bit status? ( bit 0 in DSP_STATUS register
0 (D SP Initialization)
1
HOST_RUN bit = 1 (bit 0 in DSP_RUN register) I²C Registers (HW space) 80h 81h 82h 83h 84h ... ... FEh FFh Update I²C Registers DSP Processing Read I²C Registers , Update internal Structures
(Start DSP Processing)
(Simultaneously read the 128 I²C registers)
(D SP processing time = 1ms)
(Simultaneously write the 128 I²C registers)
When programming I²C read/write register with addresses between 80h and FFh this flow has to be taken into account. For example, if two different values are written in the same register in less than 2 ms, it is possible that the DSP doesn't see the first value (because the second value over-writes the first one during the "DSP processing" phase, before DSP can read the registers again). In the same way, when waiting for a register value change, the software programme must wait for at least 2 ms in order to allow sufficient time for the DSP to update the register values.
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I²C Interface
STV82x7
Figure 31: Initialization Procedure at Startup
Power ON Hardware Reset Pin LOW Delay > 100 us Hardware Reset Pin HIGH Clock PLL programmation (Note 1) Load Patch File see Figure 32 Note 2 INIT_MEM bit ? (bit 0 in DSP_STATUS register) =1 Check Patch version (FFh register) =1 Device Input Configuration Set-up (if needed) see Figure 33 (If input configuration has to be changed, it has to be done here) (Duration of init phase < 1ms) =0
(HW_RESET bit = 1 is done by patch file at the end of patch loading)
=0
HOST_RUN bit = 1 (bit 0 in DSP_RUN register) Delay 2 ms Initialization Procedure
(Start DSP processing)
NOTE 1: Only when the crystal frequency is not 27 MHz. NOTE 2: The customer can also set bit HW_RESET = 1 here.
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STV82x7
I²C Interface
11.3
Process Flow during Patch Loading and DSP Initialization
Patch loading and DSP firmware initialization are shown in Figure 32
Figure 32: Patch Loading and DSP Initialization
(Software launch patch loading) Patch Loading HW_RESET bit = 0 (bit 2 in HOST_CMD register)
(DSP STOP)
Load patch file in memory
HW_RESET bit = 1 (bit 2 in HOST_CMD register)
(This action is included in the Patch load file)
NOTE 1
Firmware Initialization
Firmware Init phase
(Duration of Firmware initialization is less than 1ms)
Write patch version (reg FFh = xxh)
Firmware Initialization finished (INIT_MEM = 1)
(Firmware set INIT_MEM = 1 (done inside patch file) (bit 0 in DSP_STATUS register)) (Software must test INIT_MEM = 1 before continuing)
NOTE 1: The customer can also set HW_RESET = 1 here. (bit 2 in HOST_CMD register)
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I²C Interface
STV82x7
11.4
Input Configuration Change
The input configuration change must be programmed as shown in Figure 33:
Figure 33: Input Configuration change
Configuration Change
DACs Mute & Wait 50 ms for complete mute
Set bit INIT_MEM = 0 & Stop DSP Firmware (HOST_RUN bit = 0 in DSP_RUN register) & Wait 5 ms
INIT_MEM bit ? (bit 0 in DSP_STATUS register) =0
=1
Change input configuration
Restart DSP Firmware (HOST_RUN bit = 1 in DSP_RUN register)
DACs Unmute
END
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STV82x7
Register List
12
Note:
Register List
The unused bits (defined as `Reserved') in the I²C registers must be kept to zero.
The system clock registers (from address 08h to 0Bh and from address 5Ah to 5Dh) do not need to be modified if a standard 27 MHz quartz crystal oscillator is used. The default values of the demodulator registers (from address 0Ch to 55h) are for optimum performances and any change is not recommended, except for:
AGC_GAIN (0Fh) to adjust AGC gain for AM carrier in L/L' standard (AGC used in open loop). CAROFFSET1 (22h) and CAROFFSET2 (3Ah) to compensate IF carrier frequency with an out-of-standard offset. Soundlevel Prescaling PRESCALE_AM (94h), PRESCALE_FM (95h), PRESCALE_NICAM (96h) and PRESCALE_SCART (97h) to equalize demodulated or external audio signal before audio processing. Peak detector registers PEAK_DET_INPUT (9Dh), PEAK_DET_L (9Eh), PEAK_DET_R (9Fh), PEAK_DET_L_R (A0h) can be used to measure internal sound level.
Sound source selection for each audio output channel Loudspeakers, Headphone and SCART to be done using AUDIO_MATRIX_INPUT (A2h). In Multi-lingual mode, AUDIO_MATRIX_LANGUAGE (A4h) selects separately the language for each audio output channel. Register AUTOSTD_CTRL (8Ah) is used to select between L/L' or D/K/K1/K2/K3 standard which can be discriminated automatically. To be used also to change maximum FM deviation (125 kHz, by default) in case of wide overmodulation. AUTOSTD_STANDARD_DETECT (8Bh) and AUTOSTD_STEREO_DETECT (8Ch) to define the list of mono and stereo standards to be recognized automatically.
Note:
() used in reset value column means that the bit or the byte is read-only. (S) symbol indicates that the field value is represented in signed binary format. (*) The field AGC_ERR[4:0] (AGC_GAIN) can be written by user if the bit AGC_CMD (AGC_CTRL) is set to one (by default controlled by Automatic Standard Recognition System). To be used to adjust manually the input gain of analog AGC amplifier for AM carrier (L/L').
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Register List
STV82x7
12.1
I²C Register Map
By default, all I²C registers controlled by Automatic Standard Recognition System (Autostandard) are forced to Read-only mode for the user. These registers and bits are shaded in Table 9.
Table 9: List of I²C Registers (Sheet 1 of 6)
Nam e
IC General Control
CUT_ID RESET I2S_CTRL I2S_STAT I2S_SYNC_OFFSET
Addr.
Reset
Bit 7
Bit 6
Bi t 5
Bit 4
Bi t 3
Bit 2
Bi t 1
Bi t 0
00 h 01 h 04 h 05 h 06 h
(0000 0001) 0000 0000 0000 0000 (0000 0000) 0000 0000
0 BUS_EXP SYNC_OFF 0
0 I²S_OUTPUT SYNC_SIGN 0 0 0 0 EN_STBY
CUT_NUMBER[5:0] 0 SOFT_ L RST2 LOCK_MODE 0 SOFT_ LRST1 SOFT_RST
LOCK_TH[1 :0] 0 0 I 2S_SFO[7: 0]
SYNC_CST[ 1:0] L R_OFF LOCK_ FLAG
Clocking 1
SYS_ CONFIG FS1 _DIV FS1 _MD FS1 _PE_H FS1 _PE_L 07 h 08 h 09 h 0Ah 0Bh 0000 0000 0001 0010 0001 0001 0011 0110 0000 0000 I2S_CH_NB[1:0] EN_PROG 0 0 0 0 PE_H1[ 7:0] PE_ L1[7:0 ] NDIV1 [1:0] INPUT_FREQ[3: 0] 0 MD1[4 :0] IN PUT_CONFI G[1: 0] SDIV1[2 :0]
Demodulator
DEMOD _CTRL DEMOD _STAT AGC_ CTRL AGC_ GAIN DC_ERR_IF 0Ch 0Dh 0Eh 0 Fh 10 h 0000 0110 (0000 0000) 0001 0001 (0000 0000) (0000 0000) 0 0 AGC_ CMD 0 0 0 0 FAR_MODE GAP_MODE 0 0 QPSK_ LK AM_SEL FM2 _CAR AGC_REF[2:0 ] AGC_ERR[4:0] DC _ERR[7: 0] FM2 _SQ DEMOD_MODE[2: 0] FM1_ CAR FM1_SQ
AGC_CST[1: 0] SIG_OVER SIG_ UNDE R
Demodulator Channel 1
CARFQ1H CARFQ1M CARFQ1L FIR1C0 FIR1C1 FIR1C2 FIR1C3 FIR1C4 FIR1C5 FIR1C6 FIR1C7 ACOEFF1 BCOEFF1 CRF 1 CETH1 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1Ah 1Bh 1Ch 1Dh 1Eh 1 Fh 20 h 0011 1110 1000 0000 0000 0000 0000 0000 1111 1110 1111 1100 1111 1101 0000 0010 0000 1101 0001 1000 0001 1111 0010 0011 0001 0010 (0000 0000) 0010 0000 CARFQ1[23 :16] CARFQ1[1 5:8] CARFQ1[7 :0] FI R1C0[7:0 ] (S) FI R1C1[7:0 ] (S) FI R1C2[7:0 ] (S) FI R1C3[7:0 ] (S) FI R1C4[7:0 ] (S) FI R1C5[7:0 ] (S) FIR 1C6[7:0] 6 (S) FI R1C7[7:0 ] (S) ACOEFF1[7:0 ] BCOEFF1[ 7:0] CRF1[7:0] (S) CETH1[7:0 ]
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STV82x7
Table 9: List of I²C Registers (Sheet 2 of 6) Nam e
SQTH1 CAROFFSET1
Register List
Addr.
21 h 22 h
Reset
0011 1100 0000 0000
Bit 7
Bit 6
Bi t 5
Bit 4
Bi t 3
Bit 2
Bi t 1
Bi t 0
SQTH1[7:0] CAROFFSET1[7:0] (S)
Demodulator Channel 2
IAGCR IAGCC IAGCS CARFQ2H CARFQ2M CARFQ2L FIR2C0 FIR2C1 FIR2C2 FIR2C3 FIR2C4 FIR2C5 FIR2C6 FIR2C7 ACOEFF2 BCOEFF2 SCOEFF S RF CRF 2 CAROFFSET2 25 h 26 h 27 h 28 h 29 h 2Ah 2Bh 2Ch 2Dh 2Eh 2 Fh 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 3Ah 1000 1000 0000 0011 (0000 0000) 0100 0100 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0100 0001 0100 0010 0101 1001 0000 1010 1100 0001 1100 (0000 0000) (0000 0000) 0000 0000 IAGC_ OFF FAR_FLT_EN MONO_FLT _EN IAGC_REF[7:0] BG_SEL MONO_ PRO G IAGC_CST[2:0]
IAGC_ CTRL [7:0] CARFQ2[23 :16] CARFQ2[1 5.8] CARFQ2[7 :0] FI R2C0[7:0 ] (S) FI R2C1[7:0 ] (S) FI R2C2[7:0 ] (S) FI R2C3[7:0 ] (S) FI R2C4[7:0 ] (S) FI R2C5[7:0 ] (S) FI R2C6[7:0 ] (S) FI R2C7[7:0 ] (S) ACOEFF2[7:0 ] BCOEFF2[ 7:0] SCOEFF[7 :0] SRF[7:0 ] (S) CRF2[7:0] (S) CAROFFSET2[7:0] (S)
NI CAM
NICAM_CTRL NICAM_BER NICAM_STAT 3Dh 3Eh 3 Fh 0000 0000 (0000 0000) (0000 0000) NIC_DET F_ MUTE LOA 0 0 0 0 0 ERROR[7:0] CBI[3:0 ] NIC_MUTE DIF_POL E CT MAE
Stereo FM
ZWT_CTRL ZWT_TIME ZWT_STAT 40 h 41 h 42 h 0011 0001 0000 0100 (0000 0000) LRST_ TONE_OFF 0 0 STD_MODE 0 0 0 0 0 0 THRESH[3:0] 0 ZW_ STAT_ RDY ZW_DET TSCTRL[ 1:0] ZWT_TIME[2:0] ZW_ST ZW_DM
Analog Control
ADC_CTRL SCART1_2 _OUTPUT_ CTRL SCART3_OUTPUT_CTRL 56 h 57 h 58 h 0000 1000 1010 1000 0000 1011 I2S_DATA0_CTRL[1 :0] SC2_ MUTE 0 0 0 0 ADC_ POWER_UP SC1_ MUTE 0 SC3_ MUTE ADC _INPUT_SEL[2 :0] SC1_OUTPUT_SEL[2:0 ] SC3_OUTPUT_SEL[2:0 ]
SC2_OUTPUT_SEL[2: 0] 0
Clocking 2
FS2 _DIV 5Ah 0001 0001 0 NDI V2[1: 0] 0 SDIV2[2 :0]
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Register List
Table 9: List of I²C Registers (Sheet 3 of 6) Nam e
FS2_MD FS2 _PE_H FS2 _PE_L
STV82x7
Addr.
5Bh 5Ch 5Dh
Reset
0001 0001 0101 1100 0010 1001
Bit 7
0
Bit 6
0
Bi t 5
0
Bit 4
Bi t 3
Bit 2
MD2[4 :0]
Bi t 1
Bi t 0
PE_H2[ 7:0] PE_ L2[7:0 ]
DSP Control
HOST_CMD 80 h 0000 0000 IT_IN_DSP 0 0 0 0 I RQ3 (HP/Srnd unmute ready) HW_R ESET 0 0
IRQ_STATUS
81 h
0000 0000
0
0
0
0
IRQ2 IRQ1 (HP detected) (I2S sync lost)
IRQ0 (au tostd)
SOFT_VERSION ONCHIP_ ALGOS DSP_STATUS DSP_RUN
82 h 83 h 84 h 85 h
(0000 0002) (0000 0000) 0000 0000 0000 0000 0 0 0 LOCK_ MODE_EN PRO_LOGI C _SELECT 0 0 NICA M 0 0
SOFT_VERSION[7:0] I2S_INPUT 0 0 LRCL K_STA RT TRUBASS 0 0 L RCLK_ POL ARITY TRU SURROUND 0 0 SCLK_ POLARITY PRO _LOGIC 0 HOST_ NO_ INIT DATA_CFG MULTICHANE L I NIT_ MEM HOST_ RU N
I2S_IN_CONFIG AV_DELAY
86 h 89 h
100 0 1110 0000 0000
0
SYNC
I 2S_MODE DELAY_ ON
DELAY_TIME[6:0]
Automatic Standard Recognition System
AUTOSTD_CTRL 8Ah 0000 0001 0 0 NICAM_ C4_OFF LDK_ ZWT2 0 NICAM_GA P_MODE LDK_SWT1 FORCE_ SQUELCH NICAM_ MONO_ IN L DK_ NICAM SINGLE_ SHOT LDK_SCK DK_ DEV[1:0] LDK_SW
AUTOSTD_STANDARD_ DETECT
8Bh
0010 1111
0
I_SCK
BG_SCK
MN_SCK
AUTOSTD_STEREO_DETECT AUTOSTD_TIMERS AUTOSTD_STATUS
8Ch 8Dh 8Eh
0001 1111 1010 0100 (0000 0000)
L DK_ZWT3
I_ NICAM
BG_ZWT
BG_NI CAM ZWEI TON_TIME[2:0]
MN_ZWT
FM_TIME[1 :0] STEREO_ ID STEREO_ OK MONO_ OK
NICAM_ TIME[2: 0] AUTOSTD_O N STEREO_SID[1:0]
MONO_SID[ 1:0]
Audio Preprocessing & Selection
DC_REMOVAL_INPUT DC_REMOVAL_L DC_REMOVAL_R PRESCALE_ SELECT PRESCALE_ AM PRESCALE_ FM PRESCALE_ NICAM PRESCALE_ SCART PRESCALE_ I2S_ 0 PRESCALE_ I2S_ 1 PRESCALE_ I2S_ 2 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h 98 h 99 h 9Ah 0000 0111 (0000 0000) (0000 0000) 0000 0000 0000 0000 0000 1100 0001 1010 0000 0000 0000 0000 0000 0000 0000 0000 0 0 0 0 0 0 0 0 0 0 0 0 NICAM_ DEMATRIX NICAM_ DEEMPH_ BYPASS 0 0 0 0 0 0 0 DC_SCART DC_NI CAM DC_ DEMOD
DC_R EMOVAL_L[ 7:0] (S) DC_REMOVAL _R[7:0] (S) 0 0 PRESCALE_AM[6:0] (S) PRESCALE_ FM[6:0] (S) PRESCALE_NICAM[6:0] (S) PRESCAL E_SCART[5:0 ] (S) PRESCALE_I2S_0[5: 0] (S) PRESCALE_I2S_1[5: 0] (S) PRESCALE_I2S_2[5: 0] (S) FM_DEEMPH FM_DEEMPH _BYPASS _ SW 0 0 AM_FM_ SELECT
DEEMPHASIS_DEMATRIX
9Bh
0000 0000
0
0
FM_DEMATRIX[1 :0]
PEAK_DET_I NPUT
9Dh
0000 0000
PEAK_ LOCATION
0
PEAK_ L_R_RANGE
PEAK_DET_INPUT[1:0]
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STV82x7
Table 9: List of I²C Registers (Sheet 4 of 6) Nam e
PEAK_DET_L
Register List
Addr.
9Eh
Reset
0(0000 0000) 0(0000 0000) 0(0000 0000)
Bit 7
OVERL OAD_L [7:0 ] OVERL OAD_ R[7:0] OVERL OAD_L _ R[7:0]
Bit 6
Bi t 5
Bit 4
Bi t 3
PEAK_L[ 6:0]
Bit 2
Bi t 1
Bi t 0
PEAK_DET_R
9 Fh
PEAK_R[6:0]
PEAK_DET_L _R
A0h
PEAK_ L_R[6:0
Matrixing
AUDIO_MATRIX_INPUT A2h 0000 0000 0 0 0 0 0 SCART_ INPUT_ SOUR CE HP_INPUT_ SOURCE L S_INPUT_ SOURCE
AUDIO_MATRIX_CON FIG
A3h
0000 0000
0 MUTE_ STEREO 0 0 0 0
0 MUTE_ AL L 0
0
SCART_ MATRIX
DEMOD_ MATRIX[3:0 ]
AUDIO_MATRIX_LANGUAGE DOWNMIX_I N_MODE DOWNMIX_OUT_MODE DOWNMIX_DUAL_MODE DOWNMIX_CONFIG
A4h A6h A7h A8h A9h
0000 0000 0000 0010 0100 1010 0000 0000 0000 0001
SCART_LANGUAGE[1:0] 0 0
HP_LANGUAGE[1:0] LFE_ IN
LS_LANGUAGE[1:0] MIX_IN_MODE[ 2:0] MIX_ OUT_MODE[2:0] H P_DUAL _SELECT[1:0 ] L R_UPMIX NORMAL IZE
HP_MODE[1 :0] DUAL_ON 0
SCART_MODE[1:0]
LS_ DUAL_SELECT[1:0] SRND_FACTOR[1:0]
SCART_DUAL _SELECT [1:0] CENTER_FACTOR[1 :0]
Audio Processing
PRO_LOGIC2 _CONTROL PCM_SRND _DELAY PCM_CENTER_DEL AY PRO_LOGIC2 _CONFIG PRO_LOGIC2 _DIMENSION PRO_LOGIC2 _LEVEL NOISE_GENERATOR AAh ABh ACh ADh AEh AFh B0h 0011 1010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 10_DB_ ATTENUATE SRIGHT_ NOISE TRUSRND_ MONO_ SRND SLEFT_ NOI SE PL2 _LFE 0 0 0 0 PL2 _OUTPUT_ DOWNMIX[2:0] 0 0 0 0 0 0 PL2_C_WIDTH 0 PL2_ SRND_FILTER 0 PL2_L EVEL SUB_ NOISE CENTER_ NOISE RIGHT_ NOISE LEFT_ NOISE TRUSRND_ MODE NOI SE_ ON PL2_MODES[2:0 ] SNRD_ DELAY[4 :0] CENTER_DELAY[3:0] PL2_RS_ POLARITY PL2_ PANORAMA PL 2_DIMENSION PL 2_AUTO BALANCE PL 2_ACTIVE
TRUSRND_C ONTROL
B1h
0000 0000
0
TRU SRND_INPUT_MODE[3:0 ]
TRUSRN D_ ON
TRUSRND_I NPUT_GAIN TRUSRND_H P_DCL TRUSRND_D C_ELEVATION TRUBASS_ LS_C ONTROL TRUBASS_ LS_L EVEL TRUBASS_ HP_CONTROL TRUBASS_ HP_L EVEL SVC_LS_CONTROL SVC_LS_TIME_TH SVC_HP_CONTROL SVC_HP_TIME_ TH
B6h B7h B8h BAh BBh B Ch B Dh BEh BFh C0h C1h
0000 0000 0000 0000 0000 1100 0000 0110 0 0001 1001 0000 0110 0000 1001 0000 0010 1001 1000 0000 0010 1001 1000 0 0 0 SVC_ LS_TIME[2:0 ] 0 SVC_HP_TIME[ 2:0] 0 0 0 0 0 0 0 0 0 0 0
TRUSRND_ INPUT_GAIN[7 :0] 0 0 DIALOG_ HEADPHONE CLARITY_ON _ON 0
TRUSRND_DC_ELEVATION[7:0 ] TRUBASS_LS_SIZE[3 :0] TRUBASS_L S_LEVEL[7:0] TRUBASS_HP_SIZE[3:0] TRUBASS_HP_ LEVEL[7 :0] 0 SVC_LS_INPUT[1 :0] SVC_ LS_ AMP SVC_ LS_ON TRUBASS_ HP_ ON TRUBASS_ LS_ON
SVC_L S_THRESHOLD[4:0] (S) 0 0 0 SVC_ LHP_AMP SVC_ HP_ ON
SVC_HP_THRESHOLD[4 :0] (S)
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Register List
Table 9: List of I²C Registers (Sheet 5 of 6) Nam e
SVC_LS_GAIN SVC_HP_GAIN STSRND_CONTROL STSRND_FREQ STSRND_LEVEL OMNISURROUND_CONTROL
STV82x7
Addr.
C2h C3h C4h C5h C6h C7h
Reset
0000 0000 0000 0000 0000 0000 0001 0101 1000 0000 0000 0000
Bit 7
0 0
Bit 6
0 0
Bi t 5
0 0
Bit 4
Bi t 3
Bit 2
Bi t 1
Bi t 0
SVC_L S_MAKE_UP_GAIN[4:0] SVC_HP_MAKE_UP_ GAIN[4 :0] STSRND_ STEREO STSRND_ MODE STSRND_ ON
0
0
STSRND_BASS[ 1:0]
STSRND_ MEDIUM[1:0]
STSRND_TREBLE[1 :0]
STSRND_ GAIN[7:0] ST_ VOICE OMNISRND_INPUT_MODE OMNISRND_ ON DYN_ BASS_ ON LS_EQ_ON
ST_ DYNAMIC_BASS
C8h
0000 0000
BASS_LEVEL
BASS_FREQ L S_EQ_ BT_ SW
LS_EQ_BT_ CTRL LS_EQ_BAND1 LS_EQ_BAND2 LS_EQ_BAND3 LS_EQ_BAND4 LS_EQ_BAND5 LS_BASS_GAIN LS_TREBLE_GAI N HP_BT_CONTROL HP_BASS_ GAIN HP_TREBL E_GAIN OUTPUT_BASS_MNGT
C9h CA h CB h CCh CDh CE h CF h D0h D1h D2h D3h D4h
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0
0
0
0
0
0
EQ_BAND1 [7:0] (S) EQ_BAND2 [7:0] (S) EQ_BAND3 [7:0] (S) EQ_BAND4 [7:0] (S) EQ_BAND5 [7:0] (S) LS_BASS[7:0] (S) L S_TREBLE[7 :0] (S) 0 0 0 0 0 0 0 HP_BT_ON
HP_BASS[7:0 ] (S) HP_ TREBLE[7:0] (S) BASS_ MAN AGE_ON 0 0 SUB_ ACTIVE GAIN_ SWITCH 0 OCFG_NUM[ 2:0] LS_ LOUD_ON HP_ LOUD_ON
LS_LOUDNESS
D5h
0000 0100
LS_LOUD_THRESHOLD [2:0]
L S_LOUD_GAIN _HR[2:0]
HP_LOUDNESS
D6h
0000 0100
0
HP_LOUD_THRESHOLD[2:0]
HP_ LOUD_GAIN_HR[2: 0]
Volume
VOLUME_MODES D7h 1100 0111 ANTCLIP_HP _ VOL_CLAMP ANTICLIP_ L S_VOL_ CLAMP 0 0 SCART_ VOLU ME_ MODE S RND_ VOLUME_ MODE HP_ VOLUME_ MODE LS_ VOLUME_ MODE
LS_L_VOLUME_MSB LS_L_VOLUME_L SB LS_R_VOLUME_MSB LS_R_VOLUME_LSB LS_C_VOLUME_MSB LS_C_VOLUME_LSB LS_SUB_VOLUME_MSB LS_SUB_VOLUME_LSB LS_SL _VOLUME_MSB LS_SL _VOLUME_LSB LS_SR_ VOL UME_ MSB LS_SR_ VOL UME_ LSB
D8h D9h DAh DB h DCh DDh DE h DF h E0h E1h E2h E3h
1001 1000 0000 0000 0000 0000 0000 0000 1001 1000 0000 0000 1001 1000 0000 0000 1001 1000 0000 0000 0000 0000 0000 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LS_L _VOLUME_MSB[7:0 ] 0 0 0 LS_L_VOLUME_L SB[ 1:0]
LS_R_VOLUME_MSB[7 :0] 0 0 0 LS_ R_VOLUME_LSB[1:0]
LS_C_VOLUME_MSB[7 :0] 0 0 0 LS_ C_VOLUME_LSB[1:0]
LS_ SUB_VOLUME_MSB[7:0] 0 0 0 L S_SUB_VOLUME_LSB[1 :0]
LS_SL_ VOL UME_ MSB[7:0] 0 0 0 L S_SL_VOLUME_LSB[1: 0]
LS_SR_VOLUME_MSB[7:0 ] 0 0 0 LS_SR_VOL UME_L SB[1:0]
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STV82x7
Table 9: List of I²C Registers (Sheet 6 of 6) Nam e
LS_MASTER_VOL UME_MSB LS_MASTER_VOL UME_L SB HP_L_VOLUME_MSB HP_L_VOLUME_LSB HP_R_VOLUME_MSB HP_R_VOLUME_LSB SCART_L_ VOL UME_ MSB SCART_L_ VOL UME_ LSB SCART_R_VOLUME_MSB SCART_R_VOLUME_L SB
Register List
Addr.
E4h E5h E6h E7h E8h E9h EAh EBh E Ch E Dh
Reset
1110 1000 0000 0000 1001 1000 0000 0000 0000 0000 0000 0000 1101 1101 0000 0000 1101 1101 0000 0000
Bit 7
Bit 6
Bi t 5
Bit 4
Bi t 3
Bit 2
Bi t 1
Bi t 0
LS_MASTER_VOL UME_MSB[7:0] 0 0 0 0 0 0 L S_MASTER_VOLUME_ LSB[1 :0]
HP_L_VOLUME_MSB[7 :0] 0 0 0 0 0 0 HP_L _VOLUME_LSB[1:0]
HP_R_ VOLUME_ MSB[7:0] 0 0 0 0 0 0 HP_R_VOLUME_ LSB[1 :0]
SCART_ L_VOLUME_MSB[7:0 ] 0 0 0 0 0 0 SCART_L_VOLUME_ LSB[1 :0]
SCART_R_VOLU ME_MSB[ 7:0] 0 0 0 0 0 0 SCART_ R_VOLUME_ LSB[1 :0]
Beeper
BEEPER_ON EEh 0000 0000 0 0 0 0 0 0 BEEPER_ PUL SE 0 BEEPER_ ON
BEEPER_MODE BEEPER_FREQ_ VOL
EFh F0h
0000 0011 0111 0000
0
0 BEEPER_FREQ[2:0]
0
BEEPER_DURATION[1:0]
BEEPER_ PATH[1 :0]
BEEPER_VOLUME[4:0]
Mu t e
MUTE_DIGITAL F1h 1001 1111 AUTOSTD_ MUTE_ON 0 0 SCART_ D_MUTE SRND_HP_ D_MUTE SUB_ D_MUTE C_ D_ MUTE LS_ D_MUTE
S/PD IF
S/PDIF_OUT_CONFIG F2h 0000 0100 0 0 0 0 0 SPDIF_OUT_ MUTE S/PDIF_OUT_SELECT[2 :0]
Headphone Configuration
HEADPHONE_CONFIG F3h 0000 001(0) 0 0 0 0 HP_FORCE HP_LS_ MUTE HP_DET_ ACTI VE HP_ DETECTED
DAC Control
DAC_CONTROL DAC_SW_CHANNELS SPDIF_SW_CHANNELS SPDIF_CHANNEL_STATUS F4h F5h F6h F9h 0001 1111 0000 0000 0000 0000 0000 0000 0 SUR_HP_ SW 0 0 0 0 S/PDIF_ MUX DAC_SCART _MUTE DAC_SHP_ MUTE DAC_CSUB_ MUTE DAC_ LSLR_ MUTE POWER_ UP
C_SUB_SW 0 EMPHASI S 0
LS_ L_R_SW 0 COPYRIGHT
SCART_ SW SPFI_SW NON_AUDIO PRO_CON
CHANNEL_ STATUS
AutoStandard Coefficients Settings
AUTOSTD_COEFF_CTRL FBh 0000 0001 0 0 0 0 0 0 AUTOSTD_COEFF_ CTRL[1:0] AUTOSTD_ COEFF_ INDEX_MSB
AUTOSTD_COEFF_INDEX_MSB
F Ch
0000 0000
0
0
0
0
0
0
0
AUTOSTD_COEFF_INDEX_LSB AUTOSTD_COEFF_VALUE PATCH_VERSION
F Dh FEh FFh
0000 0000 0000 0000 0000 0000
AUTOSTD_COEFF_INDEX_LSB[7 :0] AUTOSTD_ COEFF_ VALUE[7:0] PATC H_VERSION[7:0]
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Register List
STV82x7
12.2
STV82x7 General Control Registers
CUT_ID Version Identification
Address: 00h Type: R Bi t 7 0 Bit 6 0 Bi t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi t 0
CUT_NUMBER[5:0]
Bit Name
Bits[7:6] CU T_NUMBER[5:0]
Re set
00 Reser ved
Function
0 0 01 Dice Version Identification
RESET
Address: 01h Type: R/W Bi t 7 BUS_EXP Bit 6 I²S_O UTPU T Bi t 5 0
Software Reset Register
Bit 4 EN_STBY
Bit 3 0 |
