STV3550
LCD and Matrix Display TV Processor
DATASHEET
STV3550
2D Block Move OSD
YCRCB[7:0] CLK_DATA HSYNC VSYNC
Standard Definition Input (SDIN)
H/V Filter Temporal Noise Reduction Film Mode Detection
Video Di splay Pipe line
PSI/CTI
Picture Compositor
Cursor Plane Background Plane
Digital Video Output
Gamma Correction Perfect Color Engine
4 to 10-bit RGB Digital Video Outputs
27 M Hz CLKXTP CLKXTM R e set
Clock Generator
ST20 32-bit CPU Core
100 MHz, 8 kB SRAM 4 kB I-Cache 4 kB D-Cache Diagnostic Controller Interrupt Controller
RTC, ADC, I²C Bus, I/O Ports, 4 Timers, UART, WDT, PWM and Infrared Digital Preprocessor
Timebase Generator
TV Peripherals
External Memo r y Interface
Flash SDRAM
Main Features
Fully-programmable Digital Video Output Stage for direct RGB interface to Flat Display Panel with 4- to 10-bit color resolution and pixel resolution from VGA to WXGA including HDTV2.
Picture Compositor to provide Transparency mode between Video and Graphic planes
High-Performance 8-bit Bitmap OSD Generator
Versatile Integrated Up-Converter
50/60-Hz Progressive output with Line-Interpolation (A + A*), Field-Merging (A + B) or with Motion-adaptive De-interlacing based on median f(A, B) Advanced Still Picture modes: AA*AA* and ABAB interlaced or AAAA non-interlaced Automatic Movie mode detection and scanning
Standard Definition Input
ITU-R BT.656/601 Video Input Separate H/V inputs synchronous with input clock 3D Temporal Noise Reduction with Comet-effect Correction Movie Mode Detection with Motion Phase Recovery Scene-change Detector for Contrast Enhancer and Upconversion Control Letterbox Format Detection and Auto-Format Correction
High-Quality Video Display
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Pixel-based resolution with 10-bit RGB outputs Programmable Resolution up to WXGA, all standard displays are supported: - Teletext 1.5 (480x520) and 2.5 (672x520) - Double-page Teletext (960x520) with Picture-and-Text - TeleWeb (640x480) 4 graphic planes with full alpha-blending capabilities: - 24-bit Background Plane - 10-bit RGB Video Plane - Bitmap OSD Plane with Color Map - Up to 128 x 128 pixel Cursor Plane 2D Graphics Accelerator
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DCLK DE H100 V100 Output C l o ck
Embedded 32-bit ST20 CPU Core Peripherals and I/Os for TV Chassis Control:
Picture Structure Improvement including Color Transition Improvement, Luma Peaking/Coring and Luma Contrast Enhancer H/V format conversion with Zoom In/Out (4x to 1/8x) with H/V decimation Letterbox and 4:3 to 16:9 format conversion with programmable 5-segment Panoramic mode Very flexible Sync Generator for Master and Slave modes by Vsync and Hsync signals generation Progressive Display mode (60 Hz, 50 Hz) for full-screen graphic planes Mosaic mode with up to 16 pictures displayed
30 fully-programmable I/Os (5V tolerant) 4 external interrupts 8-bit programmable PWM with 4 inputs/outputs Infrared Digital Preprocessor Real Time Clock and Watchdog Timer 4 16-bit standard timers 10-bit ADC with 6 inputs and wake-up capability 2 Master/Slave I²C Bus Interfaces UART and support for IrDA interfaces
Teletext 1.5 and 2.5, Closed-Caption, VPS and WSS VBI Data Decoding, TeleWeb Compliant Embedded Emulation Resources with In-Situ Flash Programming Capabilities 1.8V and 3.3V Power supplies Eco Standby mode 27-MHz Crystal Oscillator PC input compatible 1/144
February 2004
Revision 1.3
DMS No. 03688M
This is preliminary information on a new product now in development. Details are subject to change without notice.
STV3550 Chapter 1
1.1 1.2 1.3
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Introduction . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 7 Software . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 8 Related Documentation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 10
1.3.1 1.3.2 1.3.3 General Introduction Manual . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...10 User Guides . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....10 Reference Guide . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .11
Chapter 2
2.1 2.2 2.3
STV3550 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Pinout . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 12 Pin Description . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 13
Parallel I/O Pins and Alternate Functions . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 19
Chapter 3
3.1 3.2
Video Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Standard Definition Input (SDIN) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 20
3.1.1 System Description . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...20
Video Timebase Generator (VTG) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 22
3.2.1 3.2.2 3.2.3 Synchronization Modes . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .22 Deinterlacing Modes and Progressive Scan Output . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...22 Regulation Modes . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....23
3.3
Video Display Pipeline . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 24
3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 Main Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .25 Horizontal and Vertical Rescaling . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....25 Image Improvement . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..27 Brightness Estimator . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....28 Histogram . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..28 Contrast Enhancer . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....28 Spectral Processing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..35
Chapter 4
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4.1.1 4.1.2 4.1.3 4.1.4 4.1.5
Graphics Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
General Information . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..37 Main Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .37 Functional Description . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...37 Programming OSD Display Regions . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .38 Mixing OSD and Video Signals . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....48
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Color Transient Improvement . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..36
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On-Screen Display Generator (OSD) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 37
2D Graphics Accelerator . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 49 Graphic Application Examples . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 50
4.3.1 4.3.2 4.3.3 Teletext 1.5 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....50 Teletext Level 2.5 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .51 TeleWeb . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....51
4.4
Picture Compositor . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 53
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4.4.1 4.4.2 4.4.3 4.4.4 Background Color Plane . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....54 Video Plane . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....54 Cursor Plane . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...54 Graphics Plane . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....54
Chapter 5
5.1
Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Color Space Adaptor (CSA) and Interpolator . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 56
5.1.1 5.1.2 5.1.3 5.1.4 Main Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .56 General Description . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..56 Up-sampling . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...56 GFX_ACTIVE Signal . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....57
5.2 5.3 5.4
Gamma Correction . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 59 Perfect Color Engine . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 59 Digital Video Output Stage . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 59
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 Introduction . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....59 Vsync Output Capability . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....60 Hsync Output Capability . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....60 Csync Output Capability . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....60 RGB Output . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....60 Data Enable Output . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..64 Data Clock Output . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....65 Pad Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....65 Register . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....65
Chapter 6
6.1
CPU and System Management Functional Description . . . . . . . . . . . . . . . . . .66
ST20 C2C200 CPU Core . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 66
6.1.1 6.1.2 General Information . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..66 Main Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .66
6.2 6.3
ST Bus Interconnect Overview . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 66 STV3550 Memory Interface . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 66
6.3.1
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6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12
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Memory Devices . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..66 Configuring the STV3550 Memory Interface during Boot . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....67
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Address Format . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...67 Control Registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .67 Memory Configurations . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .68 Clock Management and Timing Issues . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...68 STV3550 Memory Interfaces . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...68 STV3550 Memory Interface Capabilities Regarding Flash Device . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .69 STV3550 Memory Interface Capabilities Regarding SDRAM Device . . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..71
SDRAM Low Power Mode . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..75 Memory Configurations . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .76 STV3550 External and Internal Memory Mapping . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .81
6.4
Reset Strategy . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 81
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6.4.1 6.4.2 6.4.3 External Hard Reset . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .81 Internal Reset Generated by the Watchdog . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....82 Internal Soft Reset . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....82
6.5
Booting the STV3550 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 82
6.5.1 6.5.2 Typical Boot Sequence . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..82 Starting The Main Application Program . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..83
6.6 6.7 6.8
Standby Mode . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 83 Interrupt Management . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 84 Clock Generator . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 85
Chapter 7
7.1
TV Chassis Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
PWM and Counter Module . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 86
7.1.1 7.1.2 7.1.3 External Interface . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....86 PWM Functions . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...86 Counter Functions . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....87
7.2 7.3
Infrared Receiver Preprocessor . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 88 Watchdog Timer (WDT) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 89
7.3.1 7.3.2 Clearing the Counter . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....89 Generation of Internal Watchdog Reset Signal . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....90
7.4 7.5
Real Time Clock (RTC) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 91
7.4.1 Real Time Clock (RTC) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..91
Basic Timer . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 92
7.5.1 7.5.2 Functional Description . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...92 Interrupt Selection . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....93
7.6
Analog to Digital Converter . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 94
7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 Introduction . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....94 Main Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .94 General Description . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..94
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Inter Integrated Circuit Bus (I²C) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 97
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Low Power Modes . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....96
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7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7 7.7.8 7.7.9 7.7.10 7.7.11 7.7.12 7.7.13 7.7.14 7.7.15 7.7.16 7.7.17 7.7.18 7.7.19 7.7.20 7.7.21 7.7.22 7.7.23 7.7.24 7.7.25 Basic Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....97 Functional Description . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...97 PIO Pad Connection & Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....98 Clock Generation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .99 Clock Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..99 Shift Register . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....101 Clock Edge Detection . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..102 Receive Data Sampling . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....103 Transmit & Receive Buffers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...104 Loopback Mode . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .104 Enabling Operation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .104 Master/Slave Operation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....104 Error Detection . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..105 Interrupt Mechanism . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....106 Software Reset . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..106 I²C Operation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....107 Clock Period In I²C Mode . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .109 Clock Synchronization . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .110 START/STOP Condition Detection . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 111 Slave Address Comparison . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 111 Clock Stretching . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .112 START/STOP Condition Generation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....112 Acknowledge Bit Generation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .113 Arbitration Checking . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....113 I²C Timing Specification . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....114
7.8
Asynchronous Serial Controller (ASC) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 116
7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.8.6 Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....116 Data Frames . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .117 Transmission . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....118 Reception . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....119 Baud Rate Generation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .121 Interrupt Control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .123
7.9
IrDA Encoder/Decoder . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 126
7.9.1 7.9.2
Chapter 8
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Encoding Scheme . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..126
Decoding Scheme . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..126
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Register . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...127
General Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Package Mechanical Data . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 128
Chapter 9
9.1 9.2 9.3 9.4 9.5
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Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Absolute Maximum Ratings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 130 Thermal Data . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 131 DC Electrical Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 131 Supply Current Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 132 H/V Synchronization Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 132
STV3550
9.6 9.7 9.8 Clock Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 132 ADC Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 133 I²C Bus Characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 135
Chapter 10
10.1 10.2 10.3 10.4 10.5 10.6
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
PIO Timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 137 Reset Timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 137 Clock Timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 138
10.3.1 XTALIN Timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....138
TAP Timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 139 Input Video Stream Timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 139
10.5.1 SDIN Interface . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..139
Output Video Port Interface (AC Electrical Characteristics) . . .. . .. . .. . .. . .. . .. . .. . .. . . 140
10.6.1 10.6.2 Normal Mode (single edge clock output) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...140 Multiplexed Mode (dual edge clock output) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....140
Chapter 11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
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1
1. 1
General Information
Introduction
This integrated circuit (IC) is dedicated to flat panel display TV chassis. Combined with a digital multi-standard video decoder (STV2310) delivering an ITU-R BT.601/656 video stream, it provides a cost-effective, high-performance solution for plasma or LCD TV applications. The STV3550 includes an up-converter, a 32-bit ST20 CPU core with all peripherals required for controlling the TV chassis. Teletext data is extracted from the incoming stream and decoded by the CPU. An embedded On-Screen Display (OSD) generator delivers the text and graphics. The Video Display Pipeline performs feature box image processing such as picture improvement, horizontal and vertical rescaling and Temporal Noise Reduction. The chip operates with an external SDRAM that is used for the field-rate up-conversion and text and graphic generations.The external SDRAM can be configured as a single bank of 16/64/128 Mb (16-bit configuration) or a dual bank of 16/64 or 128 Mb (32-bit configuration). Application program codes are stored in an external Flash memory. The STV3550 is designed using an 0.18 micron CMOS process and delivered in a 208-pin PQFP (0.5 mm pitch) package. The STV3550 completes the Digital IC Core family (STi5xxx, STi7xxx) which offers common CPU and software platforms based on STMicroelectronics' 32-bit ST20 CPU core. This device, which is specifically designed for plasma or LCD TV applications, is completely compatible with the architecture and software of the STV3500 CTV100-CRT platform that targets CRT-based TV chassis.
Figure 1: Top Level Diagram
NRESET
Build-Up Counter
Video Pipeline
YCRCB[7:0] CLK_DATA HSYNC VSYNC
8
Fast Blanking
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HV Filter TNR SDIN Block Cloc k Generator
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YSI CTI
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Digital Video Output
Gamma Correction Perfect Color Engine
4- to 10-bit G RGB Digital Video Outputs B
R
SDRAM EMI4 2D Block Move 16/32 Flash Time Base Generator 30 I/Os H100 V100
ST20 Core
27 MHz Crystal
TV Peripherals TV Chassis Control
CLKXTM
CLKXTP
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CLK_DFL
STV3550
Figure 2: CTV100-LCD Platform Diagram Example
General Information
RGB
CVBS
RGB
CVBS
CVBS
Y/C OTP or Flash Memory SDRAM 16 to 128* Mbits R
SCART
SCART
TEA6415C Bus-controlled Video Matrix
STV2310 Digital Video Decoder and Output Scaler
STV3550 Integrated Up-Converter
G B H/V
with 32-bit CPU Core and DE High-Performance OSD DLCK
Tuner
Picture/Sound Intermediate Frequency
A/D
STV8206/8207 Multi-Standard TV Sound and Audio Processor
L
D/A
* one or two banks
1.2
Software
The layering model adopted for the CTV100-LCD Software Stack is based on certain non-functional requirements:
Re-usable Portable Modular Reliable and robust
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R
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General Information
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Readable and maintainable
Figure 3: Global Software Architecture
Real-Time Embedded Operating System
Application Level Chassis Control Services
Graphics, Remote Control, Zapper
D ecoders
Drivers
I²C, OSD, SDIN, Audio, Video
STV3550
The CTV100-LCD application software consists of 4 main layers based on these non-functional requirements:
System Layer provides certain general-purpose components such as Handle or Link List Managers. This layer also contains the Operating System Abstraction Layer (OSAL) components which enable other layers to be OS-independent. Driver Layer provides a hardware abstraction to the upper layers making them hardwareindependent. Service Layer contains the components that provide the Application layer with high level interfaces in order to manage the TV set. The set of Service components included in the demonstration application are very useful for developing applications.
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General Information
Application Layer which contains the software that defines the "Look & Feel" of the TV set. This layer, for instance, contains the components that are responsible for the following features: interpretation of user inputs, display and navigation functions and Teletext applications.
Figure 4: Software Architecture Example
STV API OS Toolkit Chassis Co ntrol Audio Video Switch
STV2310 Tuner Switch
User Interface Teletext Channel Select
Keyboard Audio OSD
Electronic Program Guide Graphics Data Server
H/V & SRC Video
TeleWeb User Input
GAMMA
Resident Applications Services
Install
Infrared
SDIN
VTG
DVOS
PCE
I²C
Drivers
Hardware Layer
1.3
Related Documentation
There are several documents available that explain the various software capabilities. There are three different types of documents: 1. General Introduction Manual 2. User Guides 3. Reference Guide
1.3.1
General Introduction Manual
This document describes the general architecture of the features listed in Section 1.2: Software. It also describes the relationships between the various service, driver, system and application modules. It lists all the available modules and their version number. A brief description of each function is also provided.
1.3.2
User Guides
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A user guide is provided for each set of selected features. These documents will enable the user to get started with the relevant features. An example code is also included as well as a troubleshooting section. A list (non-exhaustive) of existing user guides is given below. 1. CTV100-LCD: STV3550 User Controls User Guide
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The Remote Control Service is responsible for the byte assembly of infrared frames
coming from a Remote Control device. It provides the client with a high-level interface to manage Remote Control inputs.
The User Interface Service provides the client with a high-level interface to manage both
Remote Control and Keyboard inputs. The client provides its own code, with which it will be notified. 2. CTV100-LCD: STV3550 Video and Sync User Guide
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The Video Service provides the client with a high-level interface for managing the Video.
This service is responsible for the complete management of the video buffers and the video display, according to client configuration, in terms of the video mode (Up-conversion, Proscan...). It also offers video-related features, such as zoom or freeze frame, among others.
The Synchronization Service is responsible for programming the field polarity. It provides
the client with a high level interface for managing the Field Polarity sequences. 3. CTV100-LCD: STV3550 Source Selection User Guide
The Audio/Video Switch service is responsible for managing the connections between
audio and video inputs and outputs by using drivers that provide audio/video switching functions. The Audio/Video Switch component is also responsible for detecting changes in the Slow Blanking Level (available on SCART connections) by using the ADC driver.
The Front End service is responsible for the tuning and the scanning operations. It
provides the client with a high level interface working in the frequency domain. 4. CTV100-LCD: STV3550 Graphics User Guide
It provides the necessary software for creating cursors and graphic planes using
respectively the Cursor Driver (DV_GAM) and the On-Screen Display Driver (STOSD).
It also includes the Two Dimensional Block Move Driver (DV_BME) in order to improve
graphical applications which often require moving blocks of data. This document will describe the CTV100-LCD Basic Graphics Stack and also provide a guide for the implementation and configuration of a graphical user interface (GUI) stack based on the OSD.
1.3.3
Reference Guide
There is one reference guide for each component (service, driver, etc.). This document includes the API as well as an Example of Use. This document specifically targets design engineers.
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STV3550 Pin List
2
2.1
STV3550 Pin List
Pinout
Figure 5: Pinout Diagram
PORTC0 PORTA0 PORTD4 PORTA1 PORTD7 PORTA4 VDD33_IO PORTA5 PORTA6 PORTA7 VDD33_IO VSS_IO PORTD5 PORTC7 PORTC6 PORTC5 PORTC4 PORTD0 PORTD1 PORTD2 PORTD3 VDD33_IO PORTD6 PORTA2 PORTA3 VSS_IO P O R TB 5 P O R TB 4 P O R TB 3 P O R TB 2 P O R TB 1 P O R TB 0 VDD33_IO VC C 3 3 _ AD C G N D _ AD C SHIELD_ADCDAC V100 H100 C L K _ D FL DCLK DE VD D 1 8 _ C O R E VSS_IO VSS_IO VDD33_IO P_VIDEO0 P_VIDEO1 P_VIDEO2 P_VIDEO3 P_VIDEO4 VDD33_IO P_VIDEO5
156 157
PORTC1 PORTC2 PO R T C 3 VS S_ IO VDD18_CORE VD D 3 3 _ IO YC R C B7 YC R C B6 YC R C B 5 YC R C B4 YC R C B3 YC R C B2 YC R C B1 YC R C B0 CLK _DATA H SYN C VSY N C SHIELD_PLL VDD18_IO VSS_PLL C L K X TP C LK X TM G N D _ PL L 1 VC C 1 8 _ PL L 1 XTALOUT XTALIN G N D _ PL L 3 VCC18_PLL3 GND_IO VCC18_IO VD D 1 8 _ C O R E VS S_ IO VDD33_IO N R ES ET TR S T TD I TD O TC K TM S VDD18_CORE VSS_IO VD D 3 3 _ IO FL A S H _ D 0 FL A S H _ D 8 FL A S H _ D 1 FL A S H _ D 9 FL A S H _ D 2 FL A S H _ D 1 0 FL A S H _ D 3 FLASH_D11 VD D 3 3 _ IO VS S_ IO
105 104
PQFP 280 Package
STV3550
P_ VID EO 6 P_VIDEO7 P_VIDEO8 P_VIDEO9 VSS_IO P_VIDEO10 P_VIDEO11 P_ VID EO 1 2 P_ VID EO 1 3 P_ VID EO 1 4 VDD33_IO P_ VID EO 1 5 P_ VID EO 1 6 P_ VID EO 1 7 P_VIDEO18 P_VIDEO19 VSS_IO P_VIDEO20 P_VIDEO21 P_ VID EO 2 2 P_ VID EO 2 3 P_ VID EO 2 4 VDD 18_CORE VS S VDD33_IO P_ VID EO 2 5 P_ VID EO 2 6 P_ VID EO 2 7 P_ VID EO 2 8 P_ VID EO 2 9 VSS_ IO VDD33_IO VS S VDD 18_CORE SD RAM_D7 SD RAM_D6 S D R A M_ D 5 S D R A M_ D 4 S D R A M_ D 3 S D R A M_ D 2 SD RAM_D1 SD RAM_D0 VSS_IO VDD33_IO SDRAM_D15 SDRAM_D14 SDRAM_D13 SDRAM_D12 SDRAM_D11 SDRAM_D10 SD RAM_D9 SD RAM_D8
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FL A S H _ D 4 NC FLASH_D12 NC FL A S H _ D 5 FLASH_D13 FL A S H _ D 6 VDD33_IO FLASH_D14 FL A S H _ D 7 FLASH_D15 VSS VD D 1 8 _ C O R E AD D R _ 1 4 AD D R _ 1 9 AD D R _ 1 8 AD D R _ 1 7 N O T_ C S _ F L A S H VSS_IO VDD33_IO VSS VD D 1 8 _ C O R E N O T_ B E 0 R D 8 N O TW R N O T_ C A S N O T_ R A S N O T_ C S _ S D R A M AD D R _ 1 5 VDD33_IO AD D R _ 1 6 AD D R _ 1 0 AD D R _ 0 AD D R _ 1 AD D R _ 2 AD D R _ 3 C KI N _ SD R A M VSS_IO VDD33_IO CKOUT_SDRAM AD D R _ 4 AD D R _ 5 AD D R _ 6 AD D R _ 7 AD D R _ 8 AD D R _ 9 ADDR_11 AD D R _ 1 2 N O T_ B E 1 AD D R _ 1 3 VSS_IO NC VDD33_IO
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2.2
Pin Description
Table 1: Digital Video Input Stage Pin No.
140 141 142 143 144 145 146 147 148 149 150
Pin Name
VSYNC HSYNC CLK_DATA YCRCB0 YCRCB1 YCRCB2 YCRCB3 YCRCB4 YCRCB5 YCRCB6 YCRCB7 Vertical Sync Input Horizontal Sync Input
Pin Description
Video Input Clock from STV2310 4:2:2 Data Stream Input 0 from STV2310 4:2:2 Data Stream Input 1 from STV2310 4:2:2 Data Stream Input 2 from STV2310 4:2:2 Data Stream Input 3 from STV2310 4:2:2 Data Stream Input 4 from STV2310 4:2:2 Data Stream Input 5 from STV2310 4:2:2 Data Stream Input 6 from STV2310 4:2:2 Data Stream Input 7 from STV2310
Table 2: Digital Video Output Stage Pin No.
Digital 193 194 195 202 203 204 205 206 208 1 2 V100 H100 CLK_DFL P_VIDEO0 P_VIDEO1 P_VIDEO2 P_VIDEO3 P_VIDEO4 P_VIDEO5 Vertical Sync Output Horizontal Sync Output Clock Output
Pin Name
Pin Description
Digital Video Output 0 Digital Video Output 1 Digital Video Output 2
P_VIDEO6
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P_VIDEO7 P_VIDEO8 P_VIDEO9
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Digital Video Output 3 Digital Video Output 4 Digital Video Output 5 Digital Video Output 6 Digital Video Output 7 Digital Video Output 8 Digital Video Output 9
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P_VIDEO10 P_VIDEO11 P_VIDEO12 P_VIDEO13 P_VIDEO14 P_VIDEO15 P_VIDEO16 P_VIDEO17 P_VIDEO18
Digital Video Output 10 Digital Video Output 11 Digital Video Output 12 Digital Video Output 13 Digital Video Output 14 Digital Video Output 15 Digital Video Output 16 Digital Video Output 17 Digital Video Output 18
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Table 2: Digital Video Output Stage (continued) Pin No.
16 18 19 20 21 22 26 27 28 29 30 196 197
STV3550 Pin List
Pin Name
P_VIDEO19 P_VIDEO20 P_VIDEO21 P_VIDEO22 P_VIDEO23 P_VIDEO24 P_VIDEO25 P_VIDEO26 P_VIDEO27 P_VIDEO28 P_VIDEO29 DCLK DE Digital Video Output 19 Digital Video Output 20 Digital Video Output 21 Digital Video Output 22 Digital Video Output 23 Digital Video Output 24 Digital Video Output 25 Digital Video Output 26 Digital Video Output 27 Digital Video Output 28 Digital Video Output 29 Digital CMOS Clock Digital CMOS Data Enable
Pin Description
Table 3: Parallel Input/Output Pins Pin No.
158 160 180 181 162 164 165 166 188 187 186 185
Pin Name
PORTA0 PORTA1 PORTA2 PORTA3 PORTA4 PORTA5 PORTA6 PORTA7
Main Function (after Reset)
Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6
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PORTB0 PORTB1 PORTB2 PORTB3 PORTB4 PORTB5
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PWMCapture0/PWM0 PWMCapture1/INT2/PWM1 PWMCapture2/INT3/extreg/PWM2
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Alternate Function
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PWMCapture3/PWM3 UARTF TXD UARTF RXD/UARTF TXD Smartcard UARTF CTS UARTF RTS AD_0 AD_1 AD_2 AD_3 AD_4 / Timer Output 0 AD_5/ Timer Output 1 SDA_0 SCL_0 SDA_1 SCL_1 SDA_2 SCL_2 SDA_3 SCL_3 Timer Input 0
Port B0 Port B1 Port B2 Port B3
Port B4 Port B5 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 Port C6 Port C7 Port D0
PORTC0 PORTC1 PORTC2 PORTC3 PORTC4 PORTC5 PORTC6 PORTC7 PORTD0
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STV3550 Pin List
Table 3: Parallel Input/Output Pins (continued) Pin No.
175 176 177 159 169 179 161
STV3550
Pin Name
PORTD1 PORTD2 PORTD3 PORTD4 PORTD5 PORTD6 PORTD7
Main Function (after Reset)
Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7
Alternate Function
Timer Input 1 Timer Input 2 / Timer Output 2 Timer Input 3/ Timer Output 3 IR_in GFX_ACTIVE INT0 INT1/16 x UART Clock
Table 4: External Memory Interface Pins Pin No.
Flash Data Bus 114 112 110 108 104 100 98 95 113 111 109 107 102 99 96 94 FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 Flash Data Bus 0 Flash Data Bus 1 Flash Data Bus 2 Flash Data Bus 3 Flash Data Bus 4 Flash Data Bus 5 Flash Data Bus 6 Flash Data Bus 7 Flash Data Bus 8 Flash Data Bus 9
Pin Name
Pin Description
Flash Data Bus 10 Flash Data Bus 11
SDRAM Data Bus
O
bs
42 41 40 39 38 37 36 35 52 51 50
let o
FLASH_D15
Pr e
du o
Flash Data Bus 12
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Flash Data Bus 13 Flash Data Bus 14 Flash Data Bus 15
SDRAM_D0 SDRAM_D1 SDRAM_D2 SDRAM_D3 SDRAM_D4 SDRAM_D5 SDRAM_D6 SDRAM_D7 SDRAM_D8 SDRAM_D9
SDRAM Data Bus 0 SDRAM Data Bus 1 SDRAM Data Bus 2 SDRAM Data Bus 3 SDRAM Data Bus 4 SDRAM Data Bus 5 SDRAM Data Bus 6 SDRAM Data Bus 7 SDRAM Data Bus 8 SDRAM Data Bus 9 SDRAM Data Bus 10
SDRAM_D10
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STV3550
Table 4: External Memory Interface Pins (continued) Pin No.
49 48 47 46 45 Address Bus 73 72 71 70 65 64 63 62 61 60 74 59 58 56 91 77 75 88 89 90 Controls 81 87 ADDR_0 ADDR_1 ADDR_2 ADDR_3 ADDR_4 ADDR_5 ADDR_6 ADDR_7 ADDR_8 ADDR_9 ADDR_10 ADDR_11 ADDR_12 ADDR_13 ADDR_14 ADDR_15 ADDR_16 ADDR_17 ADDR_18 ADDR_19 Address Bus 0 Address Bus 1 Address Bus 2 Address Bus 3 Address Bus 4 Address Bus 5 Address Bus 6 Address Bus 7 Address Bus 8 Address Bus 9 Address Bus 10 Address Bus 11 Address Bus 12 Address Bus 13 Address Bus 14
STV3550 Pin List
Pin Name
SDRAM_D11 SDRAM_D12 SDRAM_D13 SDRAM_D14 SDRAM_D15 SDRAM Data Bus 11 SDRAM Data Bus 12 SDRAM Data Bus 13 SDRAM Data Bus 14 SDRAM Data Bus 15
Pin Description
Address Bus 15 / BA0 Address Bus 16 / BA1 Address Bus 17
O
bs
78 79 80 82 57 66 69
let o
RD_NOTWR
NOT_CS_FLASH
Pr e
du o
Address Bus 18 / Not_BE2 Address Bus 19 / Not_BE3
(s) ct
so Ob -
te le
ro P
uc d
s) t(
SDRAM Write Enable / Flash Write Enable* Flash Chip Select SDRAM Chip Select SDRAM Row Address Strobe SDRAM Column Address Strobe / Flash Output Enable* SDRAM Byte Enable 0 SDRAM Byte Enable 1 Clock Output for SDRAM SDRAM Clock Feedback
NOT_CS_SDRAM NOT_RAS NOT_CAS NOT_BE0 NOT_BE1 CKOUT_SDRAM CKIN_SDRAM
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STV3550 Pin List
Table 5: System Controls Pin No.
132 131 135 136 119 121 120 118 122 123
STV3550
Pin Name
XTALOUT XTALIN CLKXTM CLKXTP TCK TDI TDO TMS TRST NRESET 27 MHz Crystal Output 27 MHz Crystal Input
Pin Description
27 MHz Differential Clock for STV2310 27 MHz Differential Clock for STV2310 Test Clock Input Test Data Input Test Data Output Test Mode Select Input Test Reset Input STV3500 Reset Input (Active Low)
Table 6: Power Supplies Pin No.
Analog 192 139 190 191 133 134 129 130 127 128 138 137 Digital 11 SHIELD_ADCDAC SHIELD_PLL VCC33_ADC GND_ADC VCC18_PLL1 GND_PLL1 VCC18_PLL3 GND_PLL3 VCC18_IO GND_IO VDD18_PLL VSS_PLL To connect to Analog Ground Supply for PLL 3.3 V Analog Voltage Supply for A/D Converter Analog Ground Supply for ADC
Pin Name
Pin Description
1.8 V Analog Voltage Supply for PLL Analog Ground Supply for PLL
1.8 V Analog Voltage Supply for PLL Analog Ground Supply for PLL
1.8 V Analog Voltage Supply for PLL I/Os
O
bs
25 32 44 53 67 76 85 97 106 115 124
let o
VDD33_IO
Pr e
du o
Analog Ground Supply for PLL I/Os
(s) ct
so Ob -
te le
ro P
uc d
s) t(
1.8 V Analog Voltage Supply for PLL Analog Ground Supply for PLL
3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply
VDD33_IO VDD33_IO VDD33_IO VDD33_IO VDD33_IO VDD33_IO VDD33_IO VDD33_IO
VDD33_IO VDD33_IO VDD33_IO
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Table 6: Power Supplies (continued) Pin No.
151 163 167 178 189 201 207 5 17 31 43 55 68 86 105 116 125 153 168 182 199 200 23 34 83 92 117 126 152
STV3550 Pin List
Pin Name
VDD33_IO VDD33_IO VDD33_IO VDD33_IO VDD33_IO VDD33_IO VDD33_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VSS_IO VDD18_CORE VDD18_CORE VDD18_CORE VDD18_CORE 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply 3.3 V Digital Voltage Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply
Pin Description
1.8 V Digital Voltage Supply 1.8 V Digital Voltage Supply 1.8 V Digital Voltage Supply 1.8 V Digital Voltage Supply
VDD18_CORE
O
bs
198 24 33 84 93
let o
VDD18_CORE VDD18_CORE VDD18_CORE VSS VSS VSS VSS
Pr e
du o
(s) ct
so Ob -
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ro P
uc d
s) t(
1.8 V Digital Voltage Supply
1.8 V Digital Voltage Supply 1.8 V Digital Voltage Supply 1.8 V Digital Voltage Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply Digital Ground Supply
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STV3550 Pin List
Table 7: Not Connected Pin No.
54 101 103
STV3550
Pin Name
NC NC NC
Pin Description
2.3
Parallel I/O Pins and Alternate Functions
The STV3550 includes 30 Parallel I/O pins arranged in 4 banks of 6 to 8-bit ports. The pins can be programmable in input, output, bi-directional or as alternate function pins. The ports are listed in Table 3 on page 14. When configured as an output, the pin can be either open drain or with weak pull-up. The input to any pin can be compared to a stored value, and if not equal, can produce an interrupt. Any pin can be configured to output an alternate functions rather than programmed value. The input channel can be directly connected to a peripheral device to make the pin as a primary input of the device. The following table shows the assignments of the alternate functions for the 30 I/O pins.
Figure 6: Pin Connections
I/O Pin Open Drain Push-Pull Output
Alternate Function
1
0
Alternate Data Output
bs O
let o
Pr e
du o
Output Latch
(s) ct
so Ob Register
te le
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Alternate Input Clock
Synchronizer
Input Latch
STBus Interconnect
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Video Functional Description
3
3. 1
Video Functional Description
Standard Definition Input (SDIN)
The Standard Definition Input (SDIN) processes video signals before their storage in the external SDRAM. The SDIN includes the following features and functions:
4:2:2 D1 Input Stream De-multiplexing including ancillary data extraction Horizontal and Vertical Decimation by 2 and 4 with horizontal and vertical anti-aliasing filters (with programmable coefficients) 3D-Temporal Noise Reduction based on a proprietary ST algorithm Noise Level Estimator used to control the 3D-TNR through a software loop Motion Estimator to perform film mode detection or scene change detection through a software loop
Figure 7: SDIN Block Diagram
anc_data
Cr/Cb STBus Interface
Yn-2
Yn-1
anc_data
YCrCb CLK_DATA HS Y NC VSYNC D1 Interface
Y
Cr/Cb
O
3.1.1
bs
let o
Pr e
du o
D1 H/V
(s) ct
H/V Filter
so Ob Yn in
Yn out
Cr/Cb
Yn-1
De cimation by 2 and 4
3D- T NR Level Noise Level Estimator
Yn-2
te le
ro P
uc d
Yn
s) t(
Motion Estimator
Registers Synchronization H5 0 V50 Field Parity
Interrupts
System Description
3.1.1.1 D1 Interface The D1 interface extracts the luma and chroma pixels from the 8-bit data stream as well as the ancillary data embedded in the horizontal and vertical blanking interval (VBI). This data includes VBI data such as Teletext, Closed Caption, WSS, VPS, etc... and sync pulses for horizontal and vertical synchronization.
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The ancillary data is stored aligned in 32-bit packets. If necessary, the packets are completed by a filler with programmable data (060h, by default). The parity of each field is extracted from the embedded F pulse or from the external H/V pulse. The field can be determined as top first or bottom first by programming. The data stream sequence for the Y, Cr or Cb samples is programmable. 3.1.1.2 D1 Formats The typical input format supported by the SDIN is 720 pixels per line and 480 lines per frame for the 60-Hz source or 576 lines per frame for 50-Hz source (ITU-R BT.656) with a 27-MHz pixel clock. The D1 interface can also support other formats with a pixel clock up to 30 MHz. The input format is given by the configuration of the interface that is programmable up to 960 pixels per line and 1024 lines per frame. The 3D-TNR and the Motion Estimator can be used only with standardized line length of 720 pixels per line. 3.1.1.3 Synchronization Pulse Extraction The SDIN interface is able to extract either the sync pulses embedded in the data stream as described in specification ITU-R BT.656 or external H/V pulses sent on the H/V inputs. After extraction, the sync pulses are used to capture the data which is then sent to the Video Timebase Generator (VTG) to synchronize the chip. Synchronization modes are described in Section 3.2: Video Timebase Generator (VTG). The following sync pulses can be extracted and are selected using the registers:
Embedded F and H sync pulses (for the vertical sweep, and EAV or SAV pulse for the horizontal sweep), Embedded V and H sync pulses (rising or falling edge of the V sync pulse, for the vertical sweep, and EAV or SAV pulse for the horizontal sweep), External H/Vsync pulses (rising or falling edge of the external V sync pulse, for the vertical sweep, and rising or falling edge of the external H pulse for the horizontal sweep), External H/Fsync pulses (rising and falling edge of the external F sync pulse, for the vertical sweep, and rising or falling edge of the external H pulse for the horizontal sweep).
3.1.1.4 Horizontal and Vertical Filter To perform high-factor Zoom-out on a picture (from 1/4 to 1/16 of the screen) with no extra load on the memory bandwidth, the SDIN can perform a horizontal and vertical decimation by 2 or 4 on the input signal. This means that unused pixels are not stored in the SDRAM and the memory bandwidth is not penalized. Before decimation, the input signal passes through a horizontal and vertical filter to prevent aliasing effects. The coefficient of this filter is programmable and then can be optimized for each decimation factor. This filter and the decimator can be by-passed. The decimation factor is selectable by programming. When the decimator is active, the 3D-TNR is by-passed. The vertical filter line-memories are limited to 720 pixels. When a line exceeds 720 pixels, the input line must be truncated to 720 pixels by the D1 interface (configured at 720 pixels per line). 3.1.1.5 3D Temporal Noise Reduction (TNR) When the D1 interface is set in a standard configuration (720 pixels per line and 288 or 240 lines per field) and the decimation filter is by-passed, the luma signal can be filtered in the spatial and temporal domain in order to reduce in-band noise. The noise reduction is based on a proprietary ST
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Video Functional Description
algorithm that includes a comet-effect canceller. The strength of the noise reduction can be adjusted in 32 steps depending on the noise level. The SDIN includes a Noise Estimator that delivers a 32-step data item on the noise level for each field. This data can be processed by the CPU to control the 3D-Temporal Noise Reductor and then performs an adaptive noise reduction. This function is available in standard configurations only. 3.1.1.6 Motion Estimator When the D1 interface is set in a standard configuration (720 pixels per line and 288 or 240 lines per field), the SDIN provides scene change and video picture format data based on 3 consecutive fields. This information can be processed by the CPU to determine if the signal is from a video or a film source, and then the CPU can select the optimized up-conversion mode (Proscan field merging or interpolation). This data is also used to determine the polarity of the field: Top First (generally used) or Bottom First.
3.2
Video Timebase Generator (VTG)
This block generates the up-converted horizontal and vertical sync pulses required to drive the video output stages. It receives the extracted H/V sync pulses from the SDIN block, in the 1H domain, and, depending on the selected synchronization mode, provides H/V sync pulses for the 2H domain. The VTG is able to generate all output synchronization pulses from 1H to 3H for horizontal sweep and 50 Hz to 120 Hz for Vertical sweep, in Interlaced or Progressive mode. The VTG clock is derived from the on-board crystal oscillator to reduce jitter. Vertical and horizontal sync pulses are generated by the division of the VTG_CLK signal frequency. The CPU manages the division factors and processes the incoming 50-Hz H and V pulses to generate the required 100-Hz scanning sequences.
3.2.1
Synchronization Modes
Slave by H and V signals (embedded or external) Slave by V signals (embedded or external) Master mode. Pass-through (for VGA application) with generator-locking of the OSD clock.
3.2.2
bs O
Deinterlacing Modes and Progressive Scan Output
The de-interlacing can be done in the following modes: Spatial line interpolation, using the high resolution vertical polyphase filter Motion adaptive spatial-temporal interpolation, using the median filter Field merging for film sources
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
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Note:
The scrolling mode is done by programming the Video Timebase Generator (VTG) that defines the output number of lines/field, and by programming the Video Display Pipeline that performs the number of pixel/line interpolations.
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Video Functional Description
The following table shows typical de-interlacing modes, according to the input format:
Table 8: De-interlacing and Scaling Modes
INPUT Panels & Output modes 50 Hz interlaced Video
A+A*B*+B Or A+Med (A,B)
STV3550
50 Hz interlaced movie
A +B Z out H 720>640 Z out V 576>480
50 Hz n-interlaced game
A+A*B*+B Or A+Med (A,B) Z out H 720>640 Z out V 576>480 A+A*B*+B Or A+Med (A,B) Zin H 720>1024 Z in V 576>768
60 Hz interlaced Video
A+A*B*+B Or A+Med (A,B) Z out H 720>640 Z out V 576>480 A+A*B*+B Or A+Med (A,B) Zin H 720>1024 Z in V 576>768
60 Hz interlaced movie (3:2)
3:2pd Z out H 720>64 0 Z out V 576>48 0
60 Hz interlaced movie (2:2)
A +B Z out H 720>640 Z out V 576>480
60 Hz n-interlaced game
A+A*B*+B Or A+Med (A,B) Z out H 720>640 Z out V 576>480 A+A*B*+B Or A+Med (A,B) Zin H720>1024 Z in V 576>768
VGA
OUTPUT
Z out H 720>640 Z out V 576>480 A+A*B*+B Or A+Med (A,B)
A +B Z in H 720>1024 Z in V 576>768
3:2pd Zin H 720>1024 Z in V 576>76 8
A +B Zin H 720>1024 Z in V 576>768
XGA
Z in H 720>1024 Z in V 576>768
Note:
720 pixels/line refers to ITU-R BT 601/656 video input standard resolution.
3.2.3
Regulation Modes
The regulation modes of the input and output dataflows are based on the configurations of several blocks such as the SDIN, VTG, Display, and also depends on the selected synchronization modes. These regulation modes are then managed by a software layer that controls the various registers and includes algorithms to maintain the balance between the input and output dataflows. This service software layer allows various regulation modes as described below, selectable at the application level. When the VTG block is set in Slave mode, the PLL that line-locks the clock pixel to the Hsync signal is used to regulate the input and output dataflows. When the VTG block is set in Master mode, the following regulation modes are possible: 1. Frame Skip & Repeat Mode (used for Proscan mode) In this mode, depending on the speed variations between the input flow and the output flow, a frame is repeated or skipped from time to time (1 to 2 per second). In this mode, depending on the speed variations between the input flow and the output flow, a field is repeated or skipped from time to time (1 to 2 per second). In this mode, certain lines are repeated or skipped during the VBI, depending on the delay between the input and output Vsync signals. 4. Pixel Skip & Repeat Mode In this mode; pixel periods are repeated or skipped during the horizontal or vertical blanking interval, depending on the delay between each Vsync signal.
bs O
2. Field Skip & Repeat Mode (used for field rate up-conversion as 100 Hz)
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3. Line Skip & Repeat Mode
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3.3
Video Display Pipeline
The Video Display block includes all the processing required for adapting the incoming video stream to the selected display format. Depending on the up-conversion mode, this block generates the correct video sequence with the selected number of pixels per line, lines per field or fields per second. It uses high-resolution horizontal and vertical polyphase filters to interpolate the additional pixels and lines required for the selected display format. These filters are also used for zoom-in and zoom-out rescaling. It also includes picture improvement algorithms (PSI/CTI) to provide the picture with a more "highresolution" aspect.
Figure 8: Video Display Flowchart All data is in Analog Y/Cr/Cb format STBus Interconnect Domain System Clock T2 Memory Interface
Pan/Scan
Pan/Scan
VTG
Luma Path HFC/V F C
bs O
let o
ro P e
PSI
du
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Chroma Path HFC/V F C
CTI
V-rst
Line Buffer
Line Buffer
4:2:2 to 4:4:4 Up-Conversion
Display Clock Domain Pixel FIFO Pixel Clock Domain
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STV3550 3.3.1 Main Features
Horizontal resizing using a Sample Rate Converter based on an 8-tap, 32-phase polyphase filter with a programmable factor from 0.25 to 4. Vertical resizing using a Sample Rate Converter based on a 4-tap, 32-phase polyphase filter with a programmable factor from 0.5 to 4. Non-linear horizontal and vertical format conversion with up to 5 programmable segments. Horizontal video output resolution adjustable between 360 and 1920 active pixels per line by using a programmable pixel clock frequency. Vertical video output resolution adjustable between 240 and 1080 active lines per field. Field parity interpolation by controlling the phase offset in the vertical polyphase filter. Programmable Pan and Scan video positioning. Color Edge Replacement for Color Transient Improvement (CTI). Horizontal and Vertical Luma Peaking. Contrast Enhancement: Black, Grey, and White Stretch. 4:2:2 to 4:4:4 Chroma Up-sampling 10-bit RGB output
3.3.2
Horizontal and Vertical Rescaling
Figure 9: Zoom Rescaling Diagram
VZoom Factor
V 3
bs O
let o
4
ro P e
HZoom Factor
du
(s) ct
so Ob -
te le
ro P
uc d
s) t(
16:9 TV Screen
1 2 Constant 5 Zone 1
Linear Zone
Constant Zone 3 Zone 2 Zone 4
H
Zone 5
The rescaling function is performed by two 32-phase polyphase filters (Horizontal and Vertical), of which all coefficients are stored in a programmable table. In this case, if needed, the transfer function of the filter can be optimized by referring to a specific up-conversion process. This scaling
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factor is programmable from 0.25 to 4 for horizontal scaling and 0.5 to 4 for vertical scaling with an accuracy of 1/8192. This allows for continuous linear zoom variations. 3.3.2.1 Non-Linear Zoom The rescaling block performs the horizontal and vertical non-linear zoom as shown in Figure 9. The picture can be divided into 5 different segments in all directions. 3.3.2.2 Letter-box Format Detection Letter-box format detection is included in order to automatically detect the horizontal black bars used with letter-box input video (Cinemascope,...) signals. This detection system is based on a proprietary algorithm that measures a certain level of data on a field basis. This function can also detect video effects such as logos or subtitles inserted in the black parts of the video. The programmer can use this data to create an automatic format conversion for all the various cinema formats. 3.3.2.3 Format Conversion The horizontal and vertical polyphase filters can be also used for the format conversions required for adapting the input video to the display format. Various examples are shown in the following figures. All formats are software-controlled and the letter-box format detector can also be used to automatically select the best-suited display format to prevent the horizontal black bars from being displayed.
Figure 10: Display Formats for 4:3 Input, 4:3 Aspect Ratio and 16:9 TV Screen
No Zoom
bs O
let o
Pr e
du o
(s) ct
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Zoom 1 H compression 33%
Zoom 2 H compression 16.5% V expansion 16.5%
Zoom 3 V expansion 33%
Zoom 5 Non-linear H (Panoramic1)
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Figure 11: Display Formats for 4:3 Input, 16:9 Aspect Ratio (Letter-box) and 16:9 TV Screen
No Zoom
Zoom7 V expansion 33%
Sub-title Zoom8 V expansion 33% and V pan
Figure 12: Display Formats for 4:3 Input, 2.35 Aspect Ratio (Wide Film) and 16:9 TV Screen
No Zoom
V expansion 33%
V expansion 75% H expansion 33%
Figure 13: Display Formats for 4:3 Input, 16:9 Aspect Ratio and 4:3 TV Screen
No Zoom
3.3.3
Image Improvement
3.3.3.1 Main Features
bs O
Contrast Enhancement with 4 different modes: Black Stretch, White Stretch, Grey Stretch and Black & White Shrink Vertical and Horizontal peaking, Luma Coring Color Edge Replacement for Color Transition Improvement (CTI) Brightness Estimator Histogram
let o
Pr e
du o
(s) ct
so Ob -
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ro P
uc d
V expansion 75% H non-linear shrink
s) t(
H and V expansion 16.6%
V non-linear Zoom
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Figure 14: Image Improvement Block Diagram
Input Stage
Filtering Brightness Estimator Histogram Autoformat Detection Average Brightness Low pass
Contrast Enhancer
Black Stretch White Stretch Grey Stretch B&W Shrink
Mix
Yin
Yout
Spectral Processing
High pass Adaptive Peaking & Coring
Chrominance Processing
Cbin, Crin Color Transient Improvement Cbout, Crout
3.3.4
Brightness Estimator
The Brightness Estimator provides the value of the average field brightness of the picture. It can be used to hardware tune the two brightness correction functions (spectral processing and contrast enhancer). Otherwise, a manual mode enables the CPU to force the average brightness value of the image.
3.3.5
Histogram
A high-resolution, non-linear histogram that uses 16 levels to characterize the image luminance is included. The accumulation of the histogram is done through an entire field and is ready to be used at the next V sync signal. A window for histogram calculation can be selected for reducing the image size which will be used for histogram processing.
3.3.6
Contrast Enhancer
The luminance processing block works only on the low pass spectrum of the input signal. All these algorithms are based on the same model (Figure 15) that uses three different segments for contrast modification: the high limit (Yhl), the low limit (Yll) and the middle segment (Ym).
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Figure 15: Yce = Ylp + Yg
255
Ym Yhl OUT
0 Yll
IN
255
The Inflexion point is dependant either on the average brightness (when using brightness estimator values) or the input value (when using manual mode). The Range parameter modifies the slope of the Ym segment. Slope values are algorithmdependant.
The Gain parameter modifies the overall curve gain in relation to the transfer curve (Yout = Yin).
bs O
let o
ro P e
0
du
(s) ct
Figure 16: Original Curve
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255
Figure 17: Example Curve after applying a Gain Factor of 2
Gain 255 0
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Table 9 shows the relation between the gain parameter and the gain factor values.
Table 9: Gain Factor Gain Parameter
0 1 2 3 4 5 6 7
Gain Factor
0.500 0.750 0.825 1.000 1.125 1.500 1.750 2.000
3.3.6.1 Black Stretch
The Black Stretch algorithm is used to decrease the black part under the average brightness point. The inflection point is based on the average brightness, but another value can be set by user. The range and gain parameters are used to set the correction slope value. This filter can be used when the overall picture is bright in order to improve the overall contrast. Figure 18 shows samples of the black stretch algorithm with an average brightness of 128 with various gain and range values.
Figure 18: Black Stretch
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3.3.6.2 White Stretch The White Stretch algorithm is used on a dark sequence in order to increase the contrast on the entire image. By default, the inflexion point is based on the average brightness, but another value can be set by user. Two modes are available by setting the range parameter: 1. When Range = 0, the inflection point is based on the value the average brightness. 2. When Range = 1, 2 or 3, the inflexion point IS NOT BASED on the value of the average brightness, but is used as parameter for an extended set of possibilities. The following figures shows various examples of the white stretch algorithm with the following values: Gain = 7, Range = 0 and an Average Brightness of 64.
Figure 19: White Stretch 1
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Figure 20: White Stretch 2
Figure 21 shows the special case of range values of 1, 2 and 3 in which the inflexion point is set by the user and is not based on the value of the average brightness.
Figure 21: White Stretch 3
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3.3.6.3 Grey Stretch In Grey Stretch mode, the Black and White Stretch values are combined to increase the contrast in both the black and white parts of the image. This function decreases the black level in the dark part of the image and increases the white level in the bright part. It can be used to increase the global contrast on low-contrast sequences that are centered on the average brightness. By default, the inflection point is based on the value of the average brightness, but another value can be set by the user. In this case, the range parameter is used to modify the slope of the central segment.
Table 10: Range and Slope Values Range
0 1 2 3
Slope
0.25 0.50 0.75 1.00
The gain parameter magnifies the correction factor and modifies the global curves in relation to the standard linear curve. Figure 22 shows the grey stretch algorithm with various range values.
Figure 22: Grey Stretch
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Figure 23 shows the grey stretch algorithm with the maximum gain value.
Figure 23: Grey Stretch Algorithm with Maximum Gain
3.3.6.4 Black & White Shrink
The Black and White Shrink function increases the black level in the dark part of the picture and decreases the white level in the bright part while maintaining the average brightness of the image. The inflection point is set at a value of 128 and cannot be seen.
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This function is used to reduce the global contrast on an over-contrasted sequence or to reveal details in the dark and bright areas. The Black and White Shrink function acts in the opposite manner of the Grey Stretch function.
Figure 24: Black and White Shrink Diagram
3.3.7
Spectral Processing
3.3.7.1 Adaptive Peaking
The luminance bandwidth must be improved when processing decoded composite signals and especially when a notch filter from the external digital video decoder is used. Luminance is improved in the STV3550 by adaptive peaking which increases the signal amplitude of a highfrequency spectrum.
bs O
This improves the outline of objects in a picture and increases the sharpness of the image. Peaking effect is auto-adaptive and depends on image brightness. In addition to the typical horizontal peaking, a vertical peaking mode can be selected in which vertical luminance components are used in the peaking algorithm. In this mode, vertical edges are also amplified. In this case, the vertical sharpness is much more sensitive to input noise and should be disabled.
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3.3.7.2 Coring If certain noisy sources are input (RF broadcast or VCR, for example), noise may be present in the signal. To prevent peaking due to noise amplification, certain coring thresholds must be used to suppress any increase of small-amplitude high-frequency signals (noise). The coring effect is programmable from 0 to 16 LSB.
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As an example, the strength of the peaking is adjustable up to 64 steps from 0 to +10 dB. The frequency peaking is adjustable from 1.5 MHz to 3.5 MHz by software (1H domain frequencies). Coring is set using the coring level parameter which gives the strength of the noise suppression in 32 steps.
3.3.8
Color Transient Improvement
Color Transient Improvement (CTI) is used to improve color transitions and chroma resolution. It uses a custom filter to enhance chroma transitions. Overshoots and undershoots of correction are suppressed to eliminate incorrect colors at the output of the algorithm. Also small amplitudes are not amplified and are further reduced to suppress noise amplification. Figure 25 shows an example of step enhancement and noise pass through.
Figure 25: Step Enhancement and Noise Pass Through
25 20 15 10 5 0 -5 -10 -15
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= Correction Signal = Peaked Signal = Input Signal
6
8
10
12
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Graphics Functional Description
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4
Note:
Graphics Functional Description
Some descriptions in this section are not applicable for LCD applications.
4.1
4.1.1
On-Screen Display Generator (OSD)
General Information
The On-Screen Display (OSD) unit is used to overlay the video image with graphics or Teletext information generated by software. The OSD pipeline uses color look-up tables (CLUTs) also called palettes, with an 8-bit input. The CLUTs can then generate 256 predefined colors that are stored in the external SDRAM. The CLUT also includes 8 bits for Transparency Mode control. The output from the CLUT is in ARGB 32-bit/pixel format (8-A, 8-R, 8-G, 8-B). The OSD plane can consist of several display regions. For each region, a different CLUT can be defined. Before being mixed with the video signal, the OSD output can be filtered by Anti-Flicker and AntiFlutter filters. These filters are used to build an OSD plane in Progressive mode and store it in a field-based format so that it may be displayed in Interlaced mode. Other display modes can be used for a full-page graphic plane: Progressive mode or Non-Interlaced mode.
4.1.2
Main Features
8 bit per pixel Bitmap OSD with 10-bit RGB output resolution through a 32-bit CLUT Up to 1920 pixels per line and 1024 lines per field Capable of displaying Teletext 1.5 to 2.5, Teleweb and EPG applications 4 display planes (Video, Background, Graphics and Cursor) with mixing capabilities:
Global, pixel-based and proportional mixing Programmable 8-bit color-based mixing factor for anti-aliasing effect on character edges Programmable 8-bit region-based mixing factor for transparency effect
Interlaced or Progressive Display Mode Anti-Flicker and Anti-Flutter filters 2-D Graphics Accelerator
Programmable RGB gain and offset Field- or frame-based storage Embedded display special effects controlled by software
O
4.1.3
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Flash, Underline, Italics, Fringe, Rounding and Shadow Vertical Scrolling Horizontal Scrolling Rolling Scrolling Opening Window
Functional Description
The OSD function displays a user-defined bitmap over any part of the displayable (i.e. non-blanked) screen, independent of the size and location of the active video area. This bitmap can be defined independently for each field. The OSD is enabled by setting the OSDON bit in the OSD_CONFIG register. The OSD bitmap is defined in relation to the display region and is independent of the decoded picture size and any pan/scan offset.
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STV3550
4.1.3.1 OSD Display Regions
Graphics Functional Description
The OSD consists of one or more display regions. Each display region is rectangular and can have its own color palette and other properties. Three examples of OSD regions are shown in Figure 26. In this figure, Region 3 shows that an OSD region can be displayed outside the active video area. A single display line cannot be included in more than one active OSD region, i.e. only one OSD region can be active on a single line. If two OSD regions are required to be displayed on the same display line, a new OSD region must be defined that includes both regions.
Figure 26: OSD Regions
Boundary of displayable area
Active video area (X0, Y0) Region 1 (X1, Y1) Region 2 Transparent
Region 3
For example, in Figure 27, two different OSD regions (A and B) use some of the same display lines. If both OSD regions are to be active at the same time, a new region (C) must be defined including both regions A and B. The area of region C that is outside regions A and B can be defined as transparent.
Figure 27: Two Display Regions using the same Display Lines
O
4.1.4
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A
Display lines in both regions B
OSD Regions
Programming OSD Display Regions
The characteristics of each OSD region are contained in an OSD specification which is stored in the 64-Mbit SDRAM. The following data is contained in the OSD specification:
A header which defines the boundaries of the region and contains 4 pointers that are used to identify the SDRAM location of the current palette, the current top block, the current bottom block, the next OSD region and other control information.
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A color palette which defines the colors in the SDRAM. Up to 256 colors can be used by the bitmap. If required, one of these colors can be "transparent" allowing the background to show through. These colors are loaded in the OSD CLUT. A bitmap composed of 2 blocks of 32-bit words.
CAUTION: When 2 regions are displayed one after the other, there must be at least one TV scan line between them with nothing displayed. This enables the OSD to reload the 256 colors in the CLUT. OSD specifications are stored as linked lists, as shown in Figure 28 and Figure 29. The order that the specifications are stored in SDRAM is the order that the regions are displayed on the screen. This self-chained mode is managed by software by programming the address of the next OSD region to be displayed in the Next OSD Specification pointer (OSDp[31:0]). The Stop Linked List (SLL) bit indicates the last specification in the list.
Figure 28: OSD Specification First Specification Address register
SDRAM
Header 1
Palettep[31:0]
Free Space
Topp[31:0] OSDp[31:0]
Palette 1 Free Space
Bottomp[31:0]
Top Field Block 1 Free Space
Bottom Field Block 1
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The OSD will stop at the end of Region 2.
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Memory space between Header, Palette, Top and Bottom Field blocks
Linked Lists
Top Field Block 2 Free Space Bottom Field Block 2 Free Space Header 3
An OSD specification can be placed anywhere within the entire 64-Mbit SDRAM. Each OSD region displayed on the screen is the object of an OSD specification. The position of the first OSD region
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Graphics Functional Description
(or OSD specification) stored in the SDRAM is defined in bits FSA[31:0] in the First Specification Address register. Each block (Header, Palette and Bitmap Data) defines one field of one OSD region and must be contiguous. Each block and its first bitmap pixel address must be aligned on a 32-bit boundary in the SDRAM. The line numbers used to define the top and bottom lines of an OSD region are the internal (field) line numbers illustrated in Figure 29. The same OSD specification may be used for both fields in a single frame.
Figure 29: Linked List Structure for OSD Data
First Specification Address register
Palettep[31:0] Header 1 Palette Topp[31:0] Bottomp[31:0] OSDp[31:0] OSD1 Bottom Field Block OSD1 Top Field Block
Decoded Image
OSD1
Header 2 Topp[31:0] OSDp[31:0] Bottomp[31:0] Palettep[31:0]
OSD2 Top Field Block
OSD2 Bottom Field Block
Header 3
Palette
STOP, if Stop Linked Lists bit is set.
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Bottomp[31:0]
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OSD3
OSD3 Top Field Block
OSD3 Bottom Field Block Legend: Topp[31:0]: Top Field Block Pointer of the current OSD region Bottomp[31:0]: Bottom Field Block Pointer of the current OSD region OSDp[29:0]: Next OSD region specification pointer
Field Storage Formats OSD planes can be stored in a field-based format with an OSD top field and an OSD bottom field, or using a frame-based format. If the bitmap is stored in frame-based format, it can be read as top and bottom fields using the Pitch function. Using pointers Topp[31:0] and Bottomp[31:0], the top field block and the bottom field block can be the same (e.g. it can be used for Simple Character mode). In this case, the data in the Top Field is the same as in the Bottom Field.
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Graphics Functional Description
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Figure 30: Field Storage Formats Field-Based Format Header Free Space Bottomp[31:0] Bottomp[31:0] Topp[31:0] Topp[31:0] Frame-Based Format Header Free Space Line-Based Format Header Free Space
Palette Free Space Top Field Block Free Space Bottom Field Block Free Space
Palette Free Space Topp1 Bottomp1 Topp2 Bottomp2
Palette Free Space
Field Block
Free Space Topp[31:0] = Bottomp[31:0]
Free Space
4.1.4.1 Header Format
The header is a block of nine 32-bit words dedicated to a single specification (i.e. one OSD region on the screen). Figure 31 shows the header mapping, with each line representing a 32-bit word.
Figure 31: OSD Header Mapping Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved Reserved
1 2 3 4 Rd 5 6 7 8 9
Offset[9:0]
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MiW[7:0]
MiGa[8:0]
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Pitch[12:0]
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GaEn
SLL
PNDL[11:0]
Gain[5:0] NCL[7:0] TPND[21:0]
CLUTAdd[7:0]
Y_bottom[10:0] Y_top[10:0] Bottomp[31:0] Topp[31:0] Palettep[31:0] OSDp[31:0]
X_left[11:0] X_right[11:0]
Address Pointers The address of the first byte (in the SDRAM) of the first color which will be loaded from the palette to the OSD CLUT is defined in bits Palettep[31:0]. If a new palette (CLUT programmed in the SDRAM) must be loaded when the OSD displays a new OSD region, the New Palette (NP) bit must be set.
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Topp2 = Topp1 + Pitch value Pitch value = 2 x PNDL value
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7
6
5
4
3
2
1
0
MiMo [1:0]
FM [1:0]
STV3550
Note:
Graphics Functional Description
The Palettep[31:0] value is not the address of the first byte of the first color in the palette. It is the address of the first byte of the first color loaded in the OSD CLUT. The address of the first byte (first pixel) in the Top Field block which will be displayed in the OSD region is defined in bits Topp[31:0]. The address of the first byte (first pixel) in the Bottom Field block which will be displayed in the OSD region is defined in bits Bottomp[31:0].
Note:
Using pointers Topp[31:0] and Bottomp[31:0], the top field block and the bottom field block can be the same (e.g. it can be used for Simple Character mode). The address of the next OSD specification in the SDRAM is defined in bits OSDp[31:0]. If the current OSD specification is the last one displayed on the TV screen, the Stop Linked List (SLL) bit must be set. OSD Region Positions The top position of the current OSD region is specified in bits Y_top[10:0] which define the vertical start of the OSD region on the screen. This value is given as a number of TV lines. The top line specified in the first word of an OSD region specification must be greater than or equal to 3. The bottom position of the current OSD region is specified in bits Y_bottom[10:0] which define the vertical end of the OSD region on the screen. This value is given as a number of TV lines. The left position of the current OSD region is specified in bits X_left[11:0] which define the horizontal start of the OSD region on the screen. This value is given as a number of pixel clock periods. The right position of the current OSD region is specified in bits X_right[11:0] which define the horizontal end of the OSD region on the screen. This value is given as a number of pixel clock periods.
Note:
An OSD region must be at the same position (same TV line) in both Interlaced and Progressive mode. In Progressive or Non-Interlaced mode, the Y_top and Y_bottom positions are programmed the same way. This means that the number of TV lines displayed for an OSD region in Progressive mode is never an odd number. An OSD region will always have (Y_bottom -Y_top)*2 TV lines displayed. In Interlaced mode, the same number of TV lines is displayed in both fields. Value "Y_bottom Y_top" is field-based. OSD Region Characteristics
The total number of pixels to be displayed in the top or bottom field for the current OSD region is given in bits TPND[21:0]. The number of pixels in the Top Field block is the same as in the Bottom Field block. This is not the number of pixels programmed in the Top and Bottom Field blocks.
bs O
The pitch value which will be added to the Topp[31:0] or Bottomp[31:0] pointers in order to load the next pixels is defined in bits Pitch[12:0]. This value represents the maximum number of pixels which will be displayed in a TV line. The number of pixels displayed in a single TV scan line is given in bits PNDL[11:0]. This value is the same for all TV scan lines in a given OSD region.
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Graphics Functional Description
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Figure 32: OSD Region Positions Vsync TV Screen Vertical Shift "X" TV lines Y_top
X_left N' TV lines OSD Region
X_right
Y_Bottom Horizontal Shift N Pixel Clock Periods
Hsync
Color Characteristics
The address in the OSD Color Look-Up-Table (CLUT) (not in the SDRAM), where the color defined in the palette of the current specification and pointed to by Palettep[31:0] will be loaded, is defined in bits CLUTAdd[7:0]. If the New Palette bit is reset, these bits are ignored. The number of colors which will be loaded in the OSD CLUT is defined in bits NCL[7:0]. The OSD CLUT can contain up to 256 colors. For more information, refer to Section 4.1.4.2: Color Data on page 46. Note: When NCL[7:0] = 00h, one color will be loaded. Each region may have its own palette, with its own number of colors (these colors will be loaded in the OSD CLUT before displaying the bitmap). If a sequence of regions uses the same palette, the palette need only be defined in the first region of the sequence. If a region only uses a part of the colors defined in the palette of the previous region, the unused colors from the previous palette can be reprogrammed for the current region in the OSD CLUT.
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Mixing Characteristics
Four different modes may be applied to RGB components for mixing OSD and video signals: Pixel Mixing mode, Global Mixing mode (mixing factor defined in Mix-Weight bits), Proportional Mixing mode (mixing factor defined in Mix-Gain bits) and No Mixing mode (full OSD). The mixing mode is specified in bits MiMo[1:0]. For more information, refer to Section 4.1.5: Mixing OSD and Video
Signals on page 48
Filter Mode Flicker problems may occur inside an OSD when there is a significant difference in the color between pixels in a top line and those of its surrounding bottom lines (e.g. if one object is visible in one line and not in its surrounding lines).
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Graphics Functional Description
In this case, the OSD consists of 2 different images which are displayed one after the other at a rate of 50 images per second. The human eye is able to detect the appearance and disappearance of both these images in the OSD. This effect is known as "flicker".
Figure 33: Filter Modes
OSD Region
Flicker
ST
Fl utte r
Flutter problems occur when the same image is used in both the top and bottom fields of a single frame. The top field is displayed in the same position as the bottom field. In this case, the OSD consists of top field lines and bottom field lines which are displayed one after the other at a rate of 50 images per second. The OSD image seems to move up and down. This effect is called "flutter". Anti-Flicker and Anti-Flutter filter modes may be applied to Alpha and RGB color values stored in the CLUT. The filter mode is selected by bits FM[1:0]. Note: The Anti-Flicker and Anti-Flutter filters are exclusive and cannot be used simultaneously. Anti-Aliasing Mode
bs O
Anti-Aliasing mode is used to smooth and remove the effects caused by insufficient sampling or poor filtering of the video signal. To enable Anti-Aliasing mode, reset the BDWOFF bit in the OSD_CONFIG register. The Anti-Aliasing value is stored in the BDW[7:0] bits in the OSD_CONFIG register. This value is only applied to the first and last lines of the OSD region. The same value is applied to all OSD regions displayed in the entire frame.
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Gain and Offset Operations A gain value may be applied to RGB outputs after the filter operations for the current OSD region by setting bit GaEn. This value is always associated with an offset value. 64 gain values are available by setting bits Gain[5:0]. The gain is never applied to Alpha or 1-Alpha values. The offset added to the RGB outputs after the gain operation for the current OSD region is defined in bits
Offset[9:0].
R[9:0] = Gain[5:0]/32 x R[9:0] + Offset[9:0] G[9:0] = Gain[5:0]/32 x G[9:0] + Offset[9:0] B[9:0] = Gain[5:0]/32 x B[9:0] + Offset[9:0]
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This can be used to independently control the contrast of the OSD plane in relation to the Video display plane.
Table 11: OSD Header Characteristics Bitfield
PNDL[11:0]
Bits
12 000h: FFFh:
Description
The Number of Pixels displayed per TV line.
Gain[5:0]
6
Gain Factor applied to RGB outputs. 00h: 0/32 Gain factor 3Fh: 63/32 Gain factor
GaEn
1
Gain Enable 0: Gain and offset operations are disabled. 1: Gain and offset operations are enabled.
MiMo[1:0]
2
Mixing Mode 00: Pixel Mixing mode 01: Global Mixing mode 10: Proportional Mixing mode 11: No Mixing mode (full OSD)
FM[1:0]
2
Filter Mode 00: No Filter mode 01: Anti-Flicker mode 10: Anti-Flutter mode 11: Reserved
SLL
1
Stop Linked List
0: The next OSD specification will be displayed. 1: The current OSD specification is the last one displayed on the TV screen. After this specification is displayed, the OSD will switch off. NP 1 New Palette 0: The CLUT from the previous OSD region will be used. 1: A new palette must be loaded for the current OSD region. Offset[9:0] 10 Offset value added to RGB outputs. 000h: 3FFh: CLUTAdd[7:0] 8
Address in the OSD CLUT where the first color (pointed by Palettep[31:0]) will be (re) loaded. 00h: FFh: 00h: FFh: Mixing factor applied to RGB outputs when Global mixing mode is selected. Values greater than 80h are clamped to 80h. 00h: 80h:
NCL[7:0]
MiW[7:0]
O
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Number of Colors Loaded in the OSD CLUT
MiGa[8:0]
Mixing factor which multiply or divide the Alpha parameter when Proportional mixing mode is selected. 000h: 1FFh:
TPND[21:0]
22
Total Number of Pixels Displayed. 0 0 00h: 3FFFFFh:
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Table 11: OSD Header Characteristics
Bitfield
Pitch[12:0]
Bits
13 0000h: 1FFFh:
Description
Pitch Value (Max. number of pixels which will be displayed on a TV line)
Y_top[10:0]
11
Top Position of the OSD Region (in number of TV scan lines). 000h: 7FFh:
Y_bottom[10:0]
11
Bottom Position of the OSD Region (in number of TV scan lines). 000h: 7FFh:
X_left[11:0]
12
Left Position of the OSD Region (in number of pixel clock periods). 000h: FFFh:
X_right[11:0]
12
Right Position of the OSD Region (in number of pixel clock periods). 000h: FFFh:
Palettep[31:0]
32
Palette Pointer 0 0 0000h: FFFFFFFFh:
Topp[31:0]
32
Top Field Block Pointer 0 0 0000h: FFFFFFFFh:
Bottomp[31:0]
32
Bottom Field Block Pointer 0 0 0000h: FFFFFFFFh:
OSDp[31:0]
32
Next OSD Region Specification Pointer. 0 0 0000h: FFFFFFFFh:
4.1.4.2 Color Data
Each color in the CLUT is defined using the RGB color elements and a mixing factor which determines the overlaying effect of the OSD.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R[7:0]
O
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Bitfield
R[7:0] G[7:0]
Pr e
Bits
8
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8
7
6
5
4
3
2
1
0
G[7:0]
B[7:0]
Alpha[7:0]
Table 12: : Palette Line Format in 32-bit Color Desc ription
Red Color value 00h: FFh: 8 Green Color value 00h: FFh:
B[7:0]
8
Blue Color value 00h: FFh:
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Graphics Functional Description
Table 12: : Palette Line Format in 32-bit Color Bitfield
Alpha[7:0]
STV3550
Bits
8 Alpha Pixel Mixing factor
Desc ription
Values greater than 80h are clamped to 80h. 00h: 80h:
Note:
Due to the GAMMA specification, the Alpha[7:0] range is from 0 to 128 in decimal (00h is transparent, 80h is full OSD). All values greater than 80h (from 81h to FFh) are clamped to 80h. The user may define a color palette with "n" number of colors ("n" words of 32 bits) for a single OSD region. Before this region is displayed, these colors are loaded into a Color Look Up Table (CLUT) in SDRAM where the RGB and Alpha bits are written. The user defines the number of colors that will be loaded into the CLUT (NCL[7:0]) and the address in the CLUT where the first color will be loaded (CLUTAdd[7:0]). These two parameters may be used to reprogram or modify certain colors in the CLUT when several regions are displayed simultaneously.
Note:
Palettep[31:0] points to the address in SDRAM of the first byte of the first color loaded.
CLUTAdd[7:0] is only used to load the colors in the CLUT and not to read the CLUT during display. The number of colors in the palette (programmed in the SDRAM) can be greater or less than 256 (a color is a word of 32 bits). But, a only maximum of 256 colors will be loaded in the OSD CLUT. The NCL[7:0] parameter refers to a contiguous number of colors programmed in the palette. If NCL = 0, one color will be loaded. Each OSD specification after the first one can either use the same color palette as the previous OSD region, or a new one can be defined. If a new palette is defined in the SDRAM, the following bits must be modified in the header:
NP must be set.
Palettep[31:0] will indicate the new address of the first byte to be loaded. NCL[7:0] gives the number of colors to be loaded in the OSD CLUT. CLUTAdd[7:0] gives the OSD CLUT address where the first color will be loaded.
CLUT outputs are 32-bits; 8-bits for R, 8-bits for G, 8-bits for B, plus 8 bits for transparency control (or mixing factor). 4.1.4.3 OSD Bitmap
bs O
The bitmap defines the OSD pixels, from left to right, in order and within lines, and follows the lines from top to bottom. The first line of a bitmap is always a top line, and the last line is always a bottom line. The number of bits per pixel is 8. The value for each pixel gives the line of the palette or the address in the CLUT, which defines the color for the pixel.
8 7 6 5 4 3 2 1 0
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 4 Pixel 8 +1 Pixel +1 Pixel +1 Pixel +1 Pixel
Pixel 1 Pixel 5
The bitmap block is subdivided in two field blocks, the top field block and the bottom field block. These two blocks always contain the same number of pixels (in both Interlaced and Progressive mode). Each field block (top or bottom) defines one field of one region and each block must be contiguous, aligned on a 32-bit boundary in the SDRAM.
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Graphics Functional Description
Two pointers, defined in the header, give the first bitmap pixel address in each field block. The bottom field block can be merged with the top field block (line-based format).
Figure 34: OSD CLUT Programming Flowchart
Header Palettep[31:0] First Address Memory Space 1st Color 2nd Color 4th Color NCL[7:0] Clutadd[7:0] = >@ 17
32 bits
n Colors 4th Color
... Colors
(NCL[7:0]+1) th Color 256th Color
Palette with n Colors nth Color Memory Space
32 bits
4.1.5
bs O
Mixing OSD and Video Signals
The mixing function is used to blend each OSD pixel with the corresponding pixel generated by the video planes behind the OSD. The mix weight is a programmable parameter and can be set for each OSD region, or for each color. The Mixing Mode bits (MiMo[1:0]) are used to select one of four possible mixing modes.
Table 13: Mixing Modes MiMo[1:0]
00 01
let o
In this example, the 4th color of the palette (programmed in SDRAM) is loaded at the CLUTAdd[7:0] address in the OSD CLUT (18th address of the OSD CLUT). Therefore, the 4th color of the palette (pointed by Palettep[31:0]) is the first color to be loaded in the OSD CLUT.
Pr e
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256th Address OSD CLUT
Description
Pixel Mixing mode Global Mixing mode
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Table 13: Mixing Modes MiMo[1:0]
10 11
STV3550
Description
Proportional Mixing mode No Mixing mode
4.1.5.1 Pixel Mixing Mode In Pixel Mixing mode, the only mixing factor applied is the Alpha mixing factor parameter (Alpha[7:0]) programmed in the CLUT. 4.1.5.2 Global Mixing Mode In Global Mixing mode, the mixing factor applied is the Mix-Weight parameter (MiW[7:0]) programmed in the header. These bits define the mixing factor (transparent level) for each OSD region used for blending the OSD and video signals. This mixing value is applied to the entire OSD region and the Alpha mixing factor in the CLUT is ignored. 4.1.5.3 Proportional Mixing Mode
In Proportional Mixing mode, the mixing factor is the result of the multiplication or division of the Alpha mixing factor (Alpha[7:0]) programmed in the CLUT by the Mix-Gain parameter (MiGa[8:0]) programmed in the header. The Mix-Gain bits define the offset applied to the mixing factor (the transparent level) for each pixel of one OSD region. In this mode, if the MSB bit (MiGa[8]) is set, the operation is multiplication. If reset, the operation is division.
MiGa[8]
0 1
MiGa[7:0]
XXh XXh
Description
Alpha[7:0] is multiplied by MiGa[7:0]
Alpha[7:0] is divided by MiGa[7:0]/128
Note:
Due to the GAMMA specification, the Alpha[7:0] range is from 0 to 128 in decimal (00h is transparent, 80h is full OSD). All values greater than 80h (from 81h to FFh) are clamped to 80h.
4.1.5.4 No Mixing Mode
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In No Mixing mode, the mixing factor is the full OSD. The Alpha mixing factor (Alpha[7:0]) programmed in the CLUT is ignored.
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A 2D Graphics Accelerator can be used to speed-up the re-location and display of graphic images. This function will automatically generate the desired link list required to move an image block from one position to another in order to accelerate data transfers in memory. This module reads a block from one area of the memory, processes this block (a process could be a simple copy), and writes the result in an other area. Memory addresses can be byte-aligned. The copying is managed by a DMA engine which alleviates the CPU load. To perform a 2D block move (with or without processing), the module must be initialized with the source and destination start addresses, the width and the height of the block and the source and destination skip value. (The skip value is equal to the number of columns of the region minus the width.) SKIP_SOURCE and SKIP_DEST data can be specified and their values can be different.
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Graphics Functional Description
There are different types of processes that must also be selected:
Read/Write (with or without filtered Data compression) Parity Checksum Simple transfer Color key based transfer: data transfered if different from a specified color (i.e. background masking) Filling Transfer with filtering (nibble to byte, parity check, ...)
Figure 35: 2D Block Move Flowchart
32-bit Width Height Repeat Width Height Times Skip_ Source
Memory
Display Screen
bsaphic Application Examples 4.3 O G r
In addition to the menus required for the user interface, certain graphic applications are supported by the STV3550.
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Memory Mapping
4.3.1
Note:
Teletext 1.5
40-character width by 26-character (12 x 10) rows 8 fully-defined colors for both foreground and background planes Mix mode (background color is fully-transparent to video)
Specific font formats can be required to fit with the panel resolution.
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Graphics Functional Description
STV3550
Subtitle mode (full-quality picture with subtitle windows) Newsflash mode / Box attribute (Text with solid background, other areas with standard video) Zoom mode: Characters and semi-graphic symbols are zoomed in by a vertical factor of 2. The zoom is done by software. Half a page is then displayable. A key enables the user to alternatively display the upper half of the page, the bottom half of the page or the complete page without zoom.
Figure 36: Teletext Level 1.5
4.3.2
Teletext Level 2.5
In Teletext 2.5, additional graphics objects are decoded to enhance Teletext page content. Up to 32 re-definable colors can be used by graphic objects. Moreover, up to 16 columns can be added to either side of the page. Horizontal resolution is then increased to 672 pixels per line.
4.3.3
TeleWeb
Full support of authored content in a 640 x 480 pixel area Minimum colour resolution of 12 bit (RGB = 444), 24 bit recommended Support for a minimum of 196 colours (the default CLUT) Software Dithering to achieve best color matching Support for full (100%) and partial (30%) transparency Support for GIF, JPEG and PNG image formats, including animation
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Graphics Functional Description
Background plane
Figure 37: TeleWeb
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4.4
Picture Compositor
The Picture Compositor is used to mix the video plane improved by the Picture Structure Improvement (YSI/CTI) module in the Video Display pipeline, with the graphics plane from the OSD pipeline. The Picture Compositor also includes a cursor plane and background color plane. A 256level Transparency mode can be used for mixing the various planes. The following figure shows a typical configuration of the video/graphics datastream flow through the Picture Compositor.
Figure 38: Typical Configuration of Picture Compositor
STBus OSD Pipeline 4:2:2 OSD Interface Cursor Module Video Plug 2H 4:4:4 Video
YCrCb to RGB
Picture Compositor Mixer + Background Color Register
Video Display Pipeline
RGB Out
Clk Reset VTG Register Interface
Video Output Encoding Digital to Analog
Figure 39: Picture Compositor Block Diagram
Background Color RGB 8:8:8
Video Display Pipeline (Main) YCbCr 4:4:4 YCbCr 4:4:4 3*10-bit to RGB 4:4:4
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OSD Pipeline
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Window Generator
OSD_ACT
RGB 10:10:10 nA1/8
A1/8
Output (TV) RGB 4:4:4 3*10-bit
128x128 Cursor Plane ACLUT8
CLUT
ARGB4444
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The Picture Compositor is a real-time multilayer (or multiplane) digital mixer. It can compose a single output stream from up to four sources:
Background color plane (programmable register) Video plane (D1 input, once captured into the local memory) Cursor plane On-Screen Display (OSD) and Graphics (GFX) plane
4.4.1
Background Color Plane
The background color is stored in a 24-bit RGB register that acts as a full-screen plane filled with a solid color. This plane is always opaque with no alpha value associated. It will be seen on each screen location, according to the resulting transparency of all the foreground planes. This plane, associated with the video plane and its mixing factor, can perform a contrast function used to adjust the contrast of the video plane, independently of the OSD plane.
4.4.2
Video Plane
The Video Display Pipeline provides a video stream that can be resized and pre-processed on the video input port. The video plane has the following characteristics:
YCbCr 4:4:4 format with 10-components, SD format compatible, Single Viewport mechanism with a global alpha value, Color Space Conversion matrix (YCbCr 601 to RGB).
4.4.3
Cursor Plane
The curser plane is defined as a 128 x 128 pixel area stored in an external memory chip. Each cursor entry is an ARGB4444 pixel. The alpha factor of 4-bits is for antialiasing the cursor pattern on top of the composited output picture. List of features :
ACLUT8 format with ARGB4444 CLUT entries, Size is programmable up to 128 x 128. Hardware rectangular clipping window, out of which the cursor is never displayed (per-pixel clipping, so only part of the cursor can be out of this window, and consequently transparent). Current bitmap is specified using a pointer register to an external memory location, making cursor animation very easy. Programmable pitch, so that all cursor patterns can be stored in a single global bitmap.
4.4.4
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Graphics Plane
List of features : On-Screen Display and Graphics data arrives in ARGB 8:10:10:10 format, Gain and offset adjustment.
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The table below summarizes the various source formats for each GAMMA Picture Compositor plane.
Table 14: List of Accepted Picture Compositor Formats Background Color Plane
X
Graphics Plane
X
Cursor Plane
Format
Description
Us e
RGB888 24-bit RGB (RGB24) ACLUT8 Bitmapped graphics with 8-bit per pixel (256 colors). For Graphics, the CLUT output is 8-bit per color component (RGB) and 8 bit for transparency (alpha). For the Cursor, the CLUT output is 4-bit per color component (RGB) and 4-bit for transparency (alpha) YCbCr Raster-based 4:2:2 picture from the D1 4:2:2 input. 4:2:2 to 4:4:4 up-conversion is performed in the video pipeline output stage before sending data to the Picture Compositor.
Only use for the background color plane with a field-based resolution (1 color only for a complete field). Simple graphics with reduced memory needs. 8-bits per pixel can use the byte manipulation modes. X
Format used for the video display pipeline output
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Video Plane
STV3550
Output Stage
5
Note:
Output Stage
Some descriptions in this section are not applicable for LCD applications.
5.1
5.1.1
Color Space Adaptor (CSA) and Interpolator
Main Features
RGB to YUV Convertion Up-sampling by two GFX_ACTIVE Programmable Delay
5.1.2
General Description
At the output of the Picture Compositor, the video format is 3x10-bit RGB 4:4:4. The video signal is first sent to a Color Space Adaptor that outputs RGB signals. The bit stream is then interpolated in order to double the bit rate. The interpolation function can be used in the event of a double-rate OSD, or mixed mode (OSD and video).
Figure 40: CSA and Interpolation Diagram
CLK_PIX
10-bit RGB 4:4:4 27 to 72 MHz
Video Matrix
Interpolator by 1 or 2
5.1.3
Up-sampling
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In this sub-block, incoming RGB data are up-converted using the CLK_DAC clock. There are two possible cases: the CLK_PIX and CLK_DAC clock frequency is the same: only the clock domain is changed, or the CLK_DAC clock frequency is twice the CLK_PIX clock frequency: the clock domain is changed and the outputs signals are padded with a zero level every two samples.
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RGB to YCrCb Conversion
On/Off
10-bit RGB 4:4:4 27 to 72 MHz
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CLK_DAC
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Output Stage
STV3550
Figure 41: Color Space Adaptor Block Diagram
RGB2YUV_EN
UPSAMPLING_EN
FILTER_EN
Up-sampling
COLOR_FILTER
RGB to YUV Signal Converter
Picture Compositor
10
2
10
FC
10
30
10
2
FC
10
10
10
2
CLK_PIX
Note:
RGB to YUV conversion and color filter functions are not used in LCD applications
5.1.4
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