Programming Manuals | Microcontrollers | 32-bit Microcontrollers | STPC 32-bit x86 Microprocessor

STPC Vega Programming Manual

Programming Manual

Format: (1725 kb)

Last Updated: 15/12/2004

Pages: 262

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STPC Vega Programming Manual

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USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. STMicroelectronics PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF STMicroelectronics. As used herein: 2. A critical component is any component of a life support device or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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1. Life support devices or systems are those which (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided with the product, can be reasonably expected to result in significant injury to the user.

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Table of Contents
TABLE OF CONTENTS
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1 HOW TO USE THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 SPECIFIC NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.1. RESERVED BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.2. SIGNAL ACTIVE STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.3. HEXADECIMAL NOTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.4. ENDIAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.3 ISSUING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 LIST OF REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2 AGENT DECODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 MEMORY ADDRESS MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.1. MEMORY HOLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.2. SMM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.3. ADDRESSABLE SDRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.4. CPU ADDRESS TO SDRAM ADDRESS MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4 IO ADDRESS MAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.1. PCI CONFIGURATION ADDRESS MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.5 CACHE RELATED REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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3.5.1. CACHE ARCHITECTURE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.5.2. CACHE ARCHITECTURE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.5.3. CACHE ARCHITECTURE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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3.6 ADDRESS DECODE RELATED REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.6.1. MEMORY HOLE CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.6.2. SHADOW CONTROL REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.6.3. SHADOW CONTROL REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6.4. SHADOW CONTROL REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.5. SHADOW CONTROL REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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3.7 HOST SDRAM CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.1. MEMORY BANK 0 REGISTER - C.I. 30H (Memory__Bank0) . . . . . . . . . . . . . . . . . . . 45 3.7.2. MEORY BANK 1 REGISTER - C.I. 31H (Memory_Bank1) . . . . . . . . . . . . . . . . . . . . . 45 3.7.3. MEMORY BANK 2 REGISTER - C.I. 32H (Memory_Bank2) . . . . . . . . . . . . . . . . . . . . 45 3.7.4. MEMORY BANK 3 REGISTER - C.I. 33H (Memory_Bank3) . . . . . . . . . . . . . . . . . . . . 46 3.7.5. SDRAM REFRESH REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.8 ACCESSING CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4 SDRAM CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2 MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3 SDRAM REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3.1. REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3.2. REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.3. REGISTER 2 (MEM_REG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.4. DDC CONTROL REGISTER DDCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.4 MEMORY CLOCK REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.4.1. MCLK control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.4.2. MCLK control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5 PCI CONTROLLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1.1. PCI ADDRESS DECODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.1.2. PCI ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.1.3. PCI ARBITER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2 ACCESSING THE PCI CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3 PCI CONFIGURATION ADDRESS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.4 CONFIGURATION DATA REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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5.5 NORTH BRIDGE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.5.1. NORTH BRIDGE PCI COMMAND REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.5.2. NORTH BRIDGE PCI STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.5.3. NORTH BRIDGE PCI REVISION ID REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.5.4. NORTH BRIDGE DEVICE CLASS CODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 61 5.5.5. NORTH BRIDGE HEADER TYPE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.5.6. NORTH BRIDGE CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.5.7. NORTH BRIDGE PCI ERROR STATUS REGISTER . . . . . . . . . . . . . . . . . . . 262. . . 63 ... 5.6 THE SOUTH BRIDGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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5.7 SOUTH BRIDGE PCI ISA CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.7.1. SOUTH BRIDGE PCI COMMAND REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.7.2. SOUTH BRIDGE PCI STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.7.3. SOUTH BRIDGE PCI REVISION ID REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.7.4. SOUTH BRIDGE DEVICE CLASS CODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 67 5.7.5. SOUTH BRIDGE HEADER TYPE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.7.6. SOUTH BRIDGE MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.8 SOUTH BRIDGE PCI FUNCTION 1 CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . 69 5.8.1. SOUTH BRIDGE VENDOR IDENTIFICATION REGISTER . . . . . . . . . . . . . . . . . . . . 69 5.8.2. SOUTH BRIDGE DEVICE IDENTIFICATION REGISTER . . . . . . . . . . . . . . . . . . . . . 69 5.8.3. SOUTH BRIDGE PCI COMMAND REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.8.4. SOUTH BRIDGE PCI STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.8.5. SOUTH BRIDGE REVISION ID REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.8.6. SOUTH BRIDGE PROGRAMMING INTERFACE REGISTER . . . . . . . . . . . . . . . . . . 72 5.8.7. SOUTH BRIDGE SUB-CLASS CODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8.8. SOUTH BRIDGE BASE-CLASS CODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.8.9. SOUTH BRIDGE LATENCY TIMER CONTROL REGISTER . . . . . . . . . . . . . . . . . . . 73 5.8.10.SOUTH BRIDGE HEADER TYPE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.8.11.SOUTH BRIDGE IDE BASE ADDRESS 0 REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 74 5.8.12.SOUTH BRIDGE IDE BASE ADDRESS 1 REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 74 5.8.13.SOUTH BRIDGE IDE BASE ADDRESS 2 REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 75 5.8.14.SOUTH BRIDGE IDE BASE ADDRESS 3 REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 75 5.8.15.SOUTH BRIDGE IDE BASE ADDRESS 4 REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 76 5.8.16.SOUTH BRIDGE IDE TIMING REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.8.17. SOUTH BRIDGE MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.9 PCI TO IDE BRIDGE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.9.1. PCI to IDE BRIDGE PCI COMMAND REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.9.2. PCI to IDE BRIDGE PCI STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.9.3. PCI to IDE BRIDGE REVISION ID REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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5.9.4. PCI to IDE BRIDGE PROGRAMMING INTERFACE REGISTER . . . . . . . . . . . . . . . . 84 5.9.5. PCI to IDE BRIDGE SUB-CLASS CODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.9.6. PCI to IDE BRIDGE BASE-CLASS CODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 85 5.9.7. PCI to IDE BRIDGE LATENCY TIMER CONTROL REGISTER . . . . . . . . . . . . . . . . . 85 5.9.8. PCI to IDE BRIDGE HEADER TYPE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.9.9. PCI to IDE BRIDGE IDE BASE ADDRESS 0 REGISTER . . . . . . . . . . . . . . . . . . . . . . 86 5.9.10.PCI to IDE BRIDGE IDE BASE ADDRESS 1 REGISTER . . . . . . . . . . . . . . . . . . . . . 86 5.9.11.PCI to IDE BRIDGE IDE BASE ADDRESS 2 REGISTER . . . . . . . . . . . . . . . . . . . . . 87 5.9.12.PCI to IDE BRIDGE IDE BASE ADDRESS 3 REGISTER . . . . . . . . . . . . . . . . . . . . . 87 5.9.13.PCI to IDE BRIDGE IDE BASE ADDRESS 4 REGISTER . . . . . . . . . . . . . . . . . . . . . 88 5.9.14.MISC REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

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5.9.15.MISC REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.9.16.PRIMARY MASTER TIMING REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.9.17.PRIMARY SLAVE TIMING REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.9.18.SECONDARY MASTER TIMING REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.9.19.SECONDARY SLAVE TIMING REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.10 PCI TO USB BRIDGE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.10.1.PCI to USB BRIDGE VENDOR IDENTIFICATION REGISTER . . . . . . . . . . . . . . . . . 92 5.10.2.PCI to USB BRIDGE DEVICE IDENTIFICATION REGISTER . . . . . . . . . . . . . . . . . . 92 5.10.3.USB BRIDGE PCI COMMAND REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.10.4.USB BRIDGE PCI STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.10.5.USB BRIDGE PCI REVISION ID REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.10.6.USB BRIDGE DEVICE CLASS CODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.10.7.USB BRIDGE HEADER TYPE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.11 PCI CONFIGURATION FOR OPENHCI-COMPLIANT USB HOST CONTROLLER . . . . . . 95 5.11.1.COMMAND REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.11.2.CLASS_CODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.11.3.BAR_OHCI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.12 LEGACY USB SUPPORT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.13 PCI TO LAN BRIDGE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.13.1.Command Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.13.2.Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.13.3.Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.13.4.Class Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.13.5.Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.13.6.Latency Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.13.7.Header Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.13.8.BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.13.9.Memory Base Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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6 ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.2 PCI / ISA CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.1. PCI to ISA read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.2. PCI TO INTERNAL REGISTER READ AND WRITE . . . . . . . . . . . . . . . . . . . . . . . . . 105 262 6.2.3. Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2.4. ISA to PCI read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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5.13.10.I/O Base Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.13.11.Interrupt Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.13.12.Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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6.2.5. ISA to PCI buffered reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2.6. ISA to PCI posted writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.7. ISA to register read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3 XBUS READ AND WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.1. Real Time Clock Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.2. BIOS ROM read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.3. CPU Reset and Gate A20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.3.1.Reset Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.4 ISA STANDARD REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.4.1. DMA 1 controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.4.2. Interrupt controller 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.4.3. Interval Timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.4.4. Port B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.4.5. Port 70h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.4.6. Interrupt Controller 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.4.7. DMA Controller 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.4.8. DMA Page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.5 ISA CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.5.1. Miscellaneous Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.5.2. Miscellaneous Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.5.3. PIRQ Routing control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.5.4. Interrupt Level Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.5.5. Interrupt Level Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.5.6. IPC Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.5.7. I2C IRQ Routing control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.5.8. ISA I/O port select and sync. register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.5.9. GPIO IRQ Routing control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.6 INTERRUPT ROUTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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6.7 DRQ ROUTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.7.1. DRQ Interrupt Router Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.7.2. DRQ Routing control registerS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

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6.6.1. INTERRUPT CONTROLLER REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . 125 6.6.2. INTERRUPT Routing control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

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7 UIDE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.2 ATA4 COMPLIANT UIDE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.3 UDMA CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

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7.4 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.4.1. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.5 IDE CONTROLLER OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.6 PRD TABLE ENTRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 7.7 IDE BUS MASTER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.7.1. Physical Region Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.7.2. Physical Region Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.8 BUS MASTER IDE REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.9 BUS MASTER IDE COMMAND REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7.9.1. IDE Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7.9.2. IDE Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.9.3. Descriptor Table Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.10 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.10.1.Standard Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.11 DATA SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.11.1.Status Bit Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.12 ERROR CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.13 PCI SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

8 LOCAL BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.2 MEMORY BANK SWITCHING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.3 FLASH DEVICE IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.3.1. Standard BIOS Boot or Boot Loader in Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 147

8.4 CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

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8.5 LOCAL BUS BASE INDEX REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.5.1. InitialiSation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.5.2. write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.5.3. Read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.5.4. I/O slot base address registers IOAREG0 to IOAREG7 . . . . . . . . . . . . . . . . . . . . . . 150 8.5.5. I/o slot mask registerS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.5.6. memory base address register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 . . 151 ... 8.5.7. memory base address register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

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8.5.8. MEMory MASK register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 8.6 LOCAL BUS TIMING REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 8.6.1. TIMING MEMORY TEMPLATE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 8.6.2. TIMING MEMORY TEMPLATE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8.6.3. i/o timing template register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8.6.4. i/o timing template register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 8.6.5. i/o timing template register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8.6.6. i/o timing template register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.6.7. i/o timing template register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8.6.8. i/o timing template register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.6.9. i/o timing template register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 8.6.10.i/o timing template register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.7 LOCAL BUS CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.8 LOCAL BUS DEVICE WIDTH REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

9 GPIO INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.2 GPIO CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.3.1. Port Direction Control Register (Base+00h): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.3.2. Read Port Control Register (Base+01h): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.3.3. Read register (Base+02h): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.3.4. INTERRUPT UNMASK REGISTER (Base+03h): . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.3.5. INTERRUPT EDGE REGISTER (Base+04h): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.3.6. INTERRUPT CLEAR COMMAND(Base+05h): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 9.3.7. GPIO port register (Base+06h): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 9.3.8. STRAP REGISTER (Base+07h): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

10 UNIVERSAL SERIAL BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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10.2 OPERATIONAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.3 PCI CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.3.1.PCI INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.3.2.PCI Configuration Spaces for OpenHCI-compliant USB Host Controller . . . . . . . . . 175

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11 MAC ETHERNET INTERFACE (LAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

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11.3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.3.1.LAN Target Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.3.2.LAN Master Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.3.3.MAC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.3.4.PHY Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.4 I/O SPACE REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.5 REGISTER BIT FIELD DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.5.1.Bus Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.5.2.Transmit Poll Demand Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.5.3.Receive Poll Demand Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.5.4.Receive Descriptor Ring Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.5.5.Transmit Descriptor Ring Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.5.6.Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.5.7.Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.5.8.Current Tx Descriptor Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.5.9.Current Rx Descriptor Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.5.10.MAC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.5.11.MAC Address Hi and lo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 11.5.12.Multicast Address Hi/Lo RegisterS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.5.13.MII Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.5.14.MII Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.5.15.Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.5.16.VLAN1 Tag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.5.17.VLAN2 Tag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.6 HOST COMMUNICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.7 DESCRIPTOR LISTS AND DATA BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.7.1.Receive Descriptors (RDES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.7.1.1.Receive Descriptor 0. 11.7.1.2.Receive Descriptor 1. 11.7.1.3.Receive Descriptor 2 11.7.1.4.Receive Descriptor 3

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197 199 199 200 201 203 204 204

11.7.2.Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 11.7.2.1.Transmit Descriptor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7.2.2.Transmit Descriptor 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7.2.3.Transmit Descriptor 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7.2.4.Transmit Descriptor 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 SERIAL PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
262 12.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

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12.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.2.1.Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.2.2.Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.2.3.Modem Control Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.3.1.Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.3.2.Receiver Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.3.3.Transmitter Holding Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.3.4.Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.3.5.Interrupt Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.3.6.Receive Timeout Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.3.7.TX FIFO Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.3.8.FIFO Polled Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.3.9.FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.3.10.Line Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12.3.11.Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.3.12.Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.3.13.Modem Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.3.14.Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.3.15.Divisor Latch (LS) - divisor latch (ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.4 SPECIAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 12.4.1.Transmit Machine Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 12.4.2.THR Empty Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 12.4.3.FIFO Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

13 I2C BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
13.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 13.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 13.3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 13.4 I2C BUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

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13.11MASTER OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13.12SLAVE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 13.13SLAVE MODE PROGRAMMING EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.13.1.Initialize Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.13.2.Write One byte as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.13.3.Read Two Bytes as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.14MASTER PROGRAMMING EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.14.1.Initialize Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.14.2.Write One Byte as a Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.14.3.Read One Byte as a Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 13.15CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 13.16I2C CONTROLLER CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 13.16.1.Buffer Receive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.16.2.Buffer Transmit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.16.3.Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 13.16.4.Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13.16.5.Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 13.16.6.Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.16.7.Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.16.8.Byte Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

14 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
14.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 14.2 POWER MANAGEMENT CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 14.2.1.TIMER REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 14.2.2.TIMER REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 14.2.3.TIMER REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

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14.2.4.SYSTEM ACTIVITY ENABLE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 14.2.5.SYSTEM ACTIVITY ENABLE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 14.2.6.SYSTEM ACTIVITY ENABLE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 14.2.7.HOUSE-KEEPING ACTIVITY ENABLE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . 247 14.2.8.HOUSE-KEEPING ACTIVITY ENABLE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . 247 14.2.9.PERIPHERAL INACTIVITY DETECTION REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . 248 14.2.10.PERIPHERAL ACTIVITY DETECTION REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . 249 14.2.11.PERIPHERAL ACTIVITY DETECTION REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . 249 14.2.12.ADDRESS RANGE 0 REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 14.2.13.ADDRESS RANGE 0 REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262. . 250 ... 14.2.14.SMI CONTROL REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

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14.2.15.SMI STATUS REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 14.2.16.SMI STATUS REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 14.2.17.PERIPHERAL INACTIVITY STATUS REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . 254 14.2.18.ACTIVITY STATUS REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 14.2.19.ACTIVITY STATUS REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 14.2.20.ACTIVITY STATUS REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 14.2.21.PMU STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 14.2.22.GENERAL PURPOSE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14.2.23.CLOCK CONTROL REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.2.24.DOZE TIMER READ BACK REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 14.2.25.STANDBY TIMER READ BACK REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 14.2.26.SUSPEND TIMER READ BACK REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 14.2.27.HOUSE-KEEPING TIMER READ BACK REGISTER . . . . . . . . . . . . . . . . . . . . . . . 261 14.2.28.PERIPHERAL TIMER READ BACK REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . 261

15 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

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LIST OF TABLES
Table 3-1. IO Map Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 3-2. PCI Configuration Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 3-3. Bits 4-3 SRAM Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 3-4. L2 Cache Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 3-5. Burst Access Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 3-6. Tag Access Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 3-7. Memory Hole Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 4-1. Memory Bank Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 4-2. SDRAM Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 4-3. MCLK Control Register Address 22/23 Index 40h, 41h . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 5-1. Register CF8h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 5-2. Register CFCh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 5-3. North Bridge Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 5-4. ISA Bridge Configuration Space Register Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 5-5. Function 1 (IDE Bridge) PCI Configuration Space Register Reset Values. . . . . . . . . . . . . 69 Table 5-6. Operating Mode of the Secondary Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 5-7. Operating Mode of the Primary Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 5-8. Timing Register Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 5-9. DMA Speed Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 5-10. IDE DMA Recovery Time Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 5-11. IDE DMA Active Time Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 5-12. Recovery R/W Signal Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 5-13. Active R/W Signal Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 5-14. Address Setup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 5-15. Prefetch Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 5-16. PCI to IDE Bridge Configuration Space Register Reset Values . . . . . . . . . . . . . . . . . . . . 81 Table 5-17. Operating Mode of the Secondary Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 5-18. Operating Mode of the Primary Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 5-19. PCI to USB Bridge Configuration Space Register Reset Values . . . . . . . . . . . . . . . . . . . 92 Table 5-20. PCI to LAN Bridge Configuration Space Register Reset Values . . . . . . . . . . . . . . . . . . . 99 Table 6-1. DMA1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 6-2. Interrupt Controller 1 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 6-3. Interval Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 6-4. Interrupt Controller 2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 6-5. DMA Controller 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 6-6. DMA Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 6-7. CPU Deturbo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 6-8. Routing Control Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 6-9. IPC Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 6-10. DMA 16-bit Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 6-11. DMA 8-bit Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 6-12. I2C Routing Control Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 6-13. UART COM Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 6-14. l COM Port IRQ Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 6-15. GPIO Routing Control Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 . . 123 ... Table 6-16. Interrupt Routing Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 6-17. Interrupt Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

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Table 6-18. DRQ Routing Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 6-19. IDRQ Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 7-1. Ultra DMA Control Signal Re-definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 7-2. Bus Master IDE Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 7-3. Interrupt/Activity Status Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 8-1. 16-bit Address Decode Registers for I/O and MEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 10-1. Host Controller Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 11-1. Ethernet Control / Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 11-2. Ethernet - PCI Configuration Registers (Function2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 12-1. Serial Port Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 12-2. Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 12-3. RX FIFO Trigger Level Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 12-4. Word Length Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 12-5. Decimal Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Table 13-1. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 13-2. Clock Control Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Table 13-3. START and STOP Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 13-4. I2C Controller Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Table 14-1. Activity Detected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Table 14-2. Suspend Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Table 14-3. Standby Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Table 14-4. House-keeping Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Table 14-5. Peripheral Timer Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Table 14-6. Doze Timer Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Table 14-7. PMU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Table 14-8. Power-on and Housekeeping States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Table 14-9. Doze/Standby/Suspend States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

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LIST OF FIGURES
Figure 3-1. STPC Host Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 3-2. STPC Physical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 4-1. Memory Controller Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 5-1. PCI Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 6-1. Interrupt Router Schematic Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 6-2. Interrupt Router Schematic Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 7-1. PRD Table Entry Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 8-1. Standards BIOS Boot Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 8-2. Two flash device implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 11-1. Block Diagram: MAC Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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1 HOW TO USE THIS MANUAL
1.1 INTRODUCTION This manual provides full technical documentation for the STPC device. It is recommended that the reader is familiar with the x86 series processors and PC compatible architectures before reading this document. Many terms are related directly to the PC architecture. The manual itself is split into chapters. These chapters hold the information for a particular functional block of the device. For example, the chapter titled "Memory Access" gives the memory map of the STPC device, the memory architecture and interface to the external DRAM modules. 1.2 SPECIFIC NOTES 1.2.1. RESERVED BITS

Write mode 1 is a subset of Write Mode 0. No CPU-supplied write data is used. The read data latched from a previous read operation is written. The bit mask is disabled. The map-masks are implemented as they are for Write Mode 0. Many bits in the register descriptions are noted as reserved. These bits are not internally connected, physically not present or are used for testing purposes. In all cases these bits should be set to a `0' when writing to a register with reserved bits. When reading from a register with reserved bits, these specific bits should be masked from the data value before action is taken on the data. Any functionality found by setting the reserved bits to levels other than `0' cannot and will not be guaranteed on future revisions of the circuit design. Thus it is not recommended to use the bits marked as reserved in any way different from noted above. 1.2.2. SIGNAL ACTIVE STATE

The hash symbol (#) following a signal name indicates that when the signal is in its active (asserted) state, the signal is at a logic low level. When the "#" is not present at the end of a signal name, the logic high level represents the active state.

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1.2.3. HEXADECIMAL NOTATION In this manual Hexadecimal (Hex) numbers (numbers to the base 16: [0-9,A-F]) are denoted by the postfix `h'. For example a memory address 783A hexadecimal will be written 783Ah.

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1.2.4. ENDIAN In common with the x86 architecture, values in memory are little-endian, that is the lower part of the memory contains the least significant Byte. For an 8-bit value
N 7 6 5 4 3 2 1 0

For a 16-bit (word) value
N N+1 7 15 6 14 5 13 4 12 3 11 2 10 1 9 0 8

For a 24-bit value
N N+1 N+2 7 15 23 6 14 22 5 13 21 4 12 20 3 11 19 2 10 18 1 9 17 0 8 16

For a 32-bit (long word) value
N N+1 N+2 N+3 7 15 23 31 6 14 22 30 5 13 21 29 4 12 20 28 3 11 19 27 2 10 18 26

For a 64-bit (QUAD word) value
N N+1 N+2 N+3 N+4 N+5 N+6 N+7 7 15 23 31 39 47 55 63 6 14 22 30 38 46 54 62 5 13 21 29 37 45 53 61 4 12 20 28 36 44 52 60 3 11 19 27 35 43 51 59

1.3 ISSUING NOTES

There are three levels identified; Advanced data, Preliminary data and Full production release. Each level is identified in a specific way as follows.
Document Identification ADVAN CED DATA

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P R E L I M I N A RY DATA FULL PRODUCTION DATA

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2 10 18 26 34 42 50 58

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1 9 17 25 33 41 49 57

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0 8 16 24 0 8 16 24 32 40 48 56

Release Identification

In design

This document based on the product specification. The information may be Release A, Release updated without notice. Large changes may B... still occur. Pre-production This document contains preliminary data and may be updated without notice in order to Issue 0.X. Data improve the product features. This is the finalised document and all test Production Data plans are completed. The information may be Issue 1.X. updated without notice in order to improve the product features.

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2 LIST OF REGISTERS
This chapter lists all the registers accessible by external software.
Section Register Name 3.1 3.1.1 3.1.2 3.1.3 3.5 Power on Strap Registers ADPC Strap Register 0 ADPC Strap Register 1 ADPC Strap Register 2 ADPC0 ADPC1 ADPC2 Configuration Configuration Configuration 0022h Cash_arc0 Cash_arc1 Cash_arc2 Configuration Configuration Configuration 0023h Index 020h Index 021h Index 022h Mnemonic Purpose Address Access type 0022/23h Index 04Ah Index 04Bh Index 04Ch

Cache Related Registers

3.5.1. Cache Architecture Register 0 3.5.2. Cache Architecture Register 1 3.5.3. Cache Architecture Register 2

3.6

Address Decode Related Registe rs MEM_HOLE SHADOW_0 SHADOW_1 SHADOW_2 SHADOW_3

0022h Configuration Configuration

3.6.1. Memory Hole Control Register 3.6.2. Shadow Control Register 0 3.6.3. Shadow Control Register 1 3.6.4. Shadow Control Register 2 3.6.5. Shadow Control Register 3

3.7

Host SDRAM Controller Registe rs

3.7.1. SDRAM Bank 0 Register

3.7.2. SDRAM Bank 1 Register 3.7.3. SDRAM Bank 2 Register 3.7.4. SDRAM Bank 3 Register

3.7.5. SDRAM Refresh Register

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Configuration

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Index 024h Index 025h Index 026h Index 027h Index 028h

Configuration

0022h Configuration Configuration Configuration Configuration Configuration 0023h Index 030h Index 031h Index 032h Index 033h Index 039h

SDRAM_bank0

SDRAM_bank1 SDRAM_bank2 SDRAM_bank3 SDRAM_Ref

Memory Interface Register 0 Register 1 Register 2 MCLK Control Registers

MEM_REG0 MEM_REG1 MEM_REG2

GBase+4C6000h Configuration 000h Configuration 004h Configuration 008h 22h

4.4.1. MCLK Control Register 0 4.4.2. MCLK Control Register 1

MCLK00 MCLK01

23h

Index 0x40h Index 0x41h

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Section Register Name

Mnemonic

Purpose

Address Access type

Config_ PCI CONFIGURATION ADaddress DRESS REGISTER CONFIGURATION DATA REGIS- Config_data 5.4 TER NORTH BRIDGE CONFIGURA5.5 TION REGISTERS 5.5.1. North Bridge PCI Command NB_Com Register 5.5.2. North Bridge PCI Status Register NB_Stat 5.3 NB_R_ID 5.5.3. North Bridge PCI Revision ID Register NB_C_ 5.5.4. North Bridge Device Class Code Code Register 5.5.5. North Bridge Header Type Register NB_Hesd 5.5.6. North Bridge Control Register 5.5.7. North Bridge PCI Error Status Register SOUTH BRIDGE PCI ISA CONFIGURATION REGISTERS South Bridge PCI Command 5.7.1. Register 5.7.2. South Bridge PCI Status Register 5.7 5.7.3. South Bridge PCI Revision ID Register 5.7.4. South Bridge Device Class Code Register 5.7.5. South Bridge Header Type Register South Bridge Miscellaneous 5.7.6. Register NB_Cont NB_E_ Stat

IO IO

0xCF8h 0xCFC CFFh

PCI Config PCI Config PCI Config PCI Config PCI Config PCI Config

Index 0x4h Index 0x6h Index 0x8h Index 0x9h

SB_ Com0

SB_Stat0

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PCI Config

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Index 0x54h

0xCF8h Index 0x4h Index 0x6h Index 0x8h Index 0x9h Index 0xEh Index 040h

SB_C_ Code0 SB_Head0

PCI Config F#0 PCI Config F#0

SB_Misc0

PCI to IDE BRIDGE CONFIGURATION REGISTERS PCI to IDE Bridge PCI Command Register PCI to IDE Bridge PCI Status Register PCI to IDE Bridge Revision ID Register PCI to IDE Bridge Programming Interface Register

ID EB_Com1 ID EB_Stat1 ID EB_R_ID1 Prog_Int

PCI Config F#1 PCI Config F#1 PCI Config F#1 PCI Config F#1

Index 0x4h Index 0x6h Index 0x8h Index 0x9h

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Section Register Name 5.9.5. PCI to IDE Bridge Sub-Class Code Register PCI to IDE Bridge Base-Class code 5.9.6. Register 5.9.7. PCI to IDE Bridge Latency Timer control Register 5.9.8. PCI to IDE Bridge Header Type Register PCI to IDE Bridge Base Address 0 5.9.9. Register 5.9.10. PCI to IDE Bridge Base Address 1 Register PCI to IDE Bridge Base Address 2 5.9.11. Register 5.9.12. PCI to IDE Bridge Base Address 3 Register PCI to IDE Bridge Base Address 4 5.9.13. Register 5.9.14. Misc Register 0 5.9.15. Misc Register 1 5.9.16. Primary Master Timing Register 5.9.17. Primary Slave Timing Register 5.9.19. Secondary Slave Timing Register PCI to USB BRIDGE CONFIGURATION REGISTERS PCI to USB Bridge Vendor Identification Register PCI to USB Bridge Device Identification Register USB Bridge PCI Command Register USB Bridge PCI Status Register

Mnemonic Sub_Class Base_Class Lat_T Head_T Base0 Base1 Base2 Base3 Base4 MISC_REG0 MISC_REG1 PMT_REG PST_REG SST_REG

Purpose PCI Config F#1 PCI Config F#1 PCI Config F#1 PCI Config F#1 PCI Config F#1 PCI Config F#1 PCI Config F#1 PCI Config F#1 PCI Config F#1

Address Access type Index 0xAh Index 0xBh Index 0xDh Index 0xEh Index 0x10h Index 0x14h Index 0x18h

5.9.18. Secondary Master Timing Register SMT_REG

5.10 5.10.1. 5.10.2. 5.10.3.

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5.10

5.10.4.

USBB_R_ID 5.10.5. USB Bridge PCI Revision ID Register 5.10.6. USB Bridge Device Class Code USBB_C_Code Register 5.10.7. USB Bridge Header Type Register USBB_Head

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Index 0x1Ch Index 0x20h Index 0x40h Index 0x50h Index 0x54h Index 0x58h Index 0x5Ch

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Index 0x48h

0xCF8h/ 0xCFCh Index 0x00h Index 0x02h Index 0x04h Index 0x06h Inderx 0x08h Index 0x09h, 0Ah & 0Bh Index 0x0Eh

USBB_V_ID1

USBB_D_ID1 USBB_Com USBB_Stat

PCI to USB BRIDGE CONFIGURATION REGISTERS 5.11.1. Command Register 5.11.2. Class Code

Command CLASS_CODE

Index 0x h Index 0x h

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Section Register Name 5.11.3. Base Address Register

Mnemonic BAR_OHCI

Purpose

Address Access type Index 0x h 0xCF8h/ 0xCFCh 05h 06h 08h 09h 0Ch 0Dh

PCI to LAN Bridge Configuration Registers 5.13.1. Command Register COMMAND 5.12 5.13.2. Status Register 5.13.3. Revision ID Register 5.13.4. Class Code Register 5.13.5. Cache Line Size Register 5.13.6. Latency Timer Register 5.13.7. Header Type Register 5.13.8. BIST Register ST AT US REVISION_ID CLASS_CODE C A C HE _ L I N E _ SIZE LATENCY_TIM ER HEADER_TYPE BIS T

5.13.9. Memory Base Address Register 0 MEMORY_BAS E _ A D D RE S S 5.13.10. I/O Base Address Register 0 5.13.11. Interrupt Line Register 5.13.12. Interrupt Pin Register IO_BASE_ADD RES S IN TE RRUP T_LI NE IN TE RRUP T_PI N

6.4

ISA Standard Registers

6.4.1. DMA 1 Controller Registers 6.4.1. DMA 1 Channel 0 Base and Current Count 6.4.1. DMA 1 Channel 1 Base and Current Address DMA 1 Channel 1 Base and 6.4.1. Current Count 6.4.1. DMA 1 Channel 2 Base and Current Address DMA 1 Channel 2 Base and 6.4.1. Current Count 6.4.1. DMA 1 Channel 3 Base and Current Address 6.4.1. DMA 1 Channel 3 Base and Current Count DMA 1 Read Status / Write 6.4.1. Command Register 6.4.1. DMA 1 Request Register

O

bs

let o

Pr e

od

ct u

(s)

DMA_1

Ob -

so

te le
IO IO IO IO IO IO IO IO IO IO

ro P

uc d

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0Eh 0Fh 10h 14h 3Ch 3Dh

0000h 0001h 0002h 0003h 0004h 0005 0006h 0007h 0008h 0009h

DMA1_CBA0

DMA1_CBC0 DMA1_CBA1 DMA1_CBC1 DMA1_CBA2 DMA1_CBC2 DMA1_CBA3 DMA1_RSWC DMA1_RR

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Section Register Name

Mnemonic

Purpose IO IO IO IO IO IO IO IO IO IO IO

Address Access type 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0020h 0040h 0040h 0041h

6.4.1. DMA 1 Read Command / Write Sin- DMA1_RCWSM gle Mask Register 6.4.1. DMA 1 Mode Register DMA1_Mode 6.4.1. DMA 1 Set / Clear Byte Pointer Flip - Flop 6.4.1. DMA 1 Read Temp Register / Master Clear DMA 1 Clear Mask / Clear All Re6.4.1. quest 6.4.1. DMA 1 Read / Write all Mask Register Bits 6.4.2. Interrupt Controller 1 Registers 6.4.3. Interval Timer Registers 6.4.3. Interval Timer Register Counter 0 Count 6.4.3. Interval Timer Register Counter 1 Count 6.4.3. Interval Timer Register Counter 2 Count 6.4.3. Command Mode Register 6.4.4. Port B Register 6.4.5. Port 60h Register 6.4.5. Port 64h Register 6.4.5. Port 70 Register 6.4.6. Interrupt Controller 2 Registers 6.4.7. DMA Controller 2 Registers DMA1_SCBPFF DMA1_RTMC DMA1_CMCAR DMA1_RWMB IC_1 IT_1 IT_0 IT_1 IT_2 IT_3 Port _B Port_60 Port_64 IC_2 Port_70

bs O

6.4.7. DMA 2 Channel 0 Base and Current Address DMA2 Channel 0 Base and Current 6.4.7. Count 6.4.7. DMA 2 Channel 1 Base and Current Address 6.4.7. DMA 2 Channel 1 Base and Current Count DMA 2 Channel 2 Base and 6.4.7. Current Address 6.4.7. DMA 2 Channel 2 Base and Current Count DMA 2 Channel 3 Base and 6.4.7. Current Address 6.4.7. DMA 2 Channel 3 Base and Current Count 6.4.7. DMA 2 Read Status / Write Command Register

let o

Pr e

du o

(s) ct

DMA_Cont2

Ob -

so

te le
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

IO

ro P

0042h

uc d

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0043h 0061h 0060h 0064h 0070h 00A0h

DMA2_CBA0

00C0h 00C2h 00C4h 00C6h 00C8h 00CAh 00CC h 00CEh 00D0h

DMA2_CBC0 DMA2_CBA1 DMA2_CBC1 DMA2_CBA2 DMA2_CBC2 DMA2_CBA3 DMA2_CBC3 DMA2_RSWC

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Section Register Name 6.4.7. DMA 2 Request Register

Mnemonic DMA2_RR

Purpose IO IO IO IO IO IO IO IO IO IO IO IO IO

Address Access type 00D2h 00D4h 00D6h 00D8h 00DAh 00DC h 00DEh

6.4.7. DMA 2 Read Command / Write Sin- DMA2_RCWSM gle Mask Register 6.4.7. DMA 2 Mode Register DMA2_Mode 6.4.7. DMA 2 Set / Clear Byte Pointer Flip - Flop 6.4.7. DMA 2 Read Temporary / Master Clear DMA 2 Clear Mask / Clear All Re6.4.7. quests Register 6.4.7. DMA 2 Read / Write all Mask Register Bits 6.4.8. DMA Page Registers DMA2_SCBPFF DMA2_RTMC DMA2_CMCAR DMA2_RWMRB DMA_Page

6.4.8. DMA Page Registers Port 80h (re- Port_80 serv ed) 6.4.8. DMA Page Register Channel 2 DMA_PRC2 6.4.8. DMA Page Register Channel 3 6.4.8. DMA Page Register Channel 1 6.4.8. DMA Page Register Port 84h 6.4.8. DMA Page Register Port 85h 6.4.8. DMA Page Register Port 86h 6.4.8. DMA Page Register Channel 0 6.4.8. DMA Page Register Port 87h 6.4.8. DMA Page Register Channel 6 6.4.8. DMA Page Register Channel 7 6.4.8. DMA Page Register Channel 5 6.4.8. DMA Page Register Port 8Bh 6.4.8. DMA Page Register Port 8Ch 6.4.8. DMA Page Register Port 8Dh 6.4.8. DMA Page Register Port 8Eh DMA_PRC3 DMA_PRC1 Port_84 Port_85 Port_86 DMA_PRC0 Port_87 DMA_PRC6

0080h 0081h

bs O
6.5 6.5.4.

6.5.1. Miscellaneous Control Register 0

let o

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uc d

(s) t

DMA_PRC 7

Ob -

so

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IO IO IO IO IO IO IO IO IO IO IO

ro P

0082h

0082h

uc d

s) t(

0084h

(Reserved) (Reserved) (Reserved)

0085h 0087h 0088h 0089h

0086h

008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0022h (Reserved) (Reserved) (Reserved) (Reserved)

DMA_PRC 5

Port_8B

Port_8C Port_8D Port_8E

ISA Configuration Registers Misc_Cont0 Misc_Cont1 PAR_Cont0 PBR_Cont0 PCR_Cont0 PDR_Cont0 Configuration Configuration Configuration Configuration Configuration Configuration Configuration

0023h

Index 050h Index 051h Index 052h Index 053h Index 054h Index 055h Index 056h

6.5.2. Miscellaneous Control Register 1

6.5.3. PIRQA Routing control Register 0

6.5.3. PIRQB Routing control Register 0 6.5.3. PIRQC Routing control Register 0 6.5.3. PIRQD Routing control Register 0

Interrupt Level Control Register 0 IRQ_Lev_C_0

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Section Register Name 6.5.5. 6.5.6. IPC Configuration Register

Mnemonic IPC_Conf

Purpose Configuration Configuration

Address Access type Index 057h Index 001h See UIDE Controller Chapter

Interrupt Level Control Register 1 IRQ_Lev_C_1

7

UIDE Controller

8

Local Bus Registers Local Bus Address Decode Registers IOAREG0 IOAREG1 IOAREG2 IOAREG3 IOAREG4 IOAREG5 IOAREG6 IOAREG7 IOMREG0

16 bit access

22h 23h

8.5.4. I/O Slot Base Register 0 8.5.4. I/O Slot Base Register 1 8.5.4. I/O Slot Base Register 2 8.5.4. I/O Slot Base Register 3 8.5.4. I/O Slot Base Register 4 8.5.4. I/O Slot Base Register 5 8.5.4. I/O Slot Base Register 6 8.5.4. I/O Slot Base Register 7 8.5.5. I/O Slot Mask Register 0 8.5.5. I/O Slot Mask Register 1 8.5.5. I/O Slot Mask Register 2 8.5.5. I/O Slot Mask Register 3 8.5.5. I/O Slot Mask Register 4 8.5.5. I/O Slot Mask Register 5 8.5.5. I/O Slot Mask Register 6

Base address Base address Base address Base address Base address Base address Base address

O

bs

8.5.5. I/O Slot Mask Register 7 8.5.6. Base address Memory Bank0 8.5.7. Base address Memory Bank1 8.5.8. Address Range Mem Bank0 & 1

let o

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du

(s) ct

IOMREG1 IOMREG2 IOMREG3 IOMREG4 IOMREG5 IOMREG6

Ob -

so

Base address Mask size Mask size Mask size Mask size Mask size Mask size Mask size Mask size

te le

ro P

uc d

IOMREG7 MEMAREG0 MEMAREG1 MEMMASK

Index 0x0000h Index 0x0002h Index 0x0004h Index 0x0006h Index 0x0008h Index 0x000Ah Index 0x000Ch Index 0x000Eh Index 0x0010h Index 0x0012h Index 0x0014h Index 0x0016h Index 0x0018h Index 0x001Ah Index 0x001Ch Index 0x001Eh Index 0x0FE0h

s) t(

Index 0x0FC0h Index 0x003Fh

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Section Register Name Local Bus Timing Registers 8.6.1. Memory Timing Template 0 8.6.2. Memory Timing Template 1 8.6.3. I/O Timing Template 0 8.6.4. I/O Timing Template 1 8.6.5. I/O Timing Template 2 8.6.6. I/O Timing Template 3 8.6.7. I/O Timing Template 4 8.6.8. I/O Timing Template 5 8.6.9. I/O Timing Template 6 8.6.10. I/O Timing Template 7

Mnemonic

Purpose

Address Access type Index 0x0020h Index 0x0022h Index 0x0024h Index 0x0026h Index 0x0028h Index 0x002Ah Index 0x002Ch Index 0x002Eh Index 0x0030h Index 0x0032h

TIMEBANK0 TIMEBANK1 TIMEIO0 TIMEIO1 TIMEIO2 TIMEIO3 TIMEIO4 TIMEIO5 TIMEIO6 TIMEIO7

Access Bank0 Access Bank1 Access I/O 0 Access I/O 1 Access I/O 2 Access I/O 3 Access I/O 4 Access I/O 5 Access I/O 6 Access I/O 7

Local Bus Control Register 8.7 8.8 Control Register I/O or Mem Width Register CONTROL IOWIDTH

9

GPIO

9.3.1. Port Direction Control Register 9.3.2. Read Port Control Register 9.3.3. Read Register

9.3.4. Interrupt Unmask Register

bs O

9.3.5. Interrupt Edge Register 9.3.6. Interrupt Clear Command 9.3.7. GPIO Port Register 9.3.8. Strap Register

let o

ro P e

du

(s) ct

so Ob -

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Index 0x0001h Index 0x0300h

portDirCtrl readPortCtrl readReg intrUnMask intrEdgeSelect clearIntr GPIOport strapReg

Index 0x0000h Index 0x0001h Index 0x0002h Index 0x0011h Index 0x0100h Index 0x0101h Index 0x0110h Index 0x0111h

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Section Register Name 12 Serial Port

Mnemonic

Purpose

Address Access type 03F8h/ 02F8h

12.3.2. Receiver Buffer Register 12.3.3. Transmitter Holding Register 12.3.4. Interrupt Enable Register 12.3.5. Interrupt Identification Register 12.3.9. FIFO Control Register 12.3.10. Line Control Register 12.3.11. Modem Control Register 12.3.12. Line Status Register 12.3.13. Modem Status Register 12.3.14. Scratch Register 12.3.15. Divisor Latch (LS) Register 12.3.15. Divisor Latch (MS) Register

RBR THR I ER IIR FCR LCR MCR LSR MSR DLL DLM

Index 0x00h Index 0x00h Index 0x01h Index 0x02h Index 0x02h Index 0x03h Index 0x04h Index 0x05h Index 0x06h Index 0x07h Index 0x00h Index 0x01h

10

MAC Ethernet Interface (LAN) BUS_MODE TRAN SMIT_PO LL_DEMAND REC EIVE_POL L_DEMAND

11.5.1. Bus Mode Register 11.5.2. Transmit Poll Demand Register 11.5.3. Receive Poll Demand Register 11.5.4. Rx Descriptor Ring Base Address Register Tx Descriptor Ring Base Address 11.5.5. Register 11.5.6. Status Register

11.5.6. Interrupt Enable Register

Current Tx Descriptor Pointer 11.5.8. Register

bs O

11.5.9. Current Rx Descriptor Pointer Register

let o

Pr e

du o

(s) ct

Rx _D ESCR_BA SE_ADD

Ob -

so

eP let

od r

uc

s) t(
03h 04h 08h 0Fh 13h 17h 1Eh 2Fh 33h 21h 37h 3Bh 3Fh

CF8h/ CFCh

Tx_DESC R_BA SE_ADD ST AT US INTERRUPT_E NABLE CURRENT_TX_ DP CURRENT_RX _DP MAC_CONTRO L M A C _ A D D RE S S_LO M A C _ A D D RE S S_HI MULTICAST_A DD RRESS _LO

11.5.10. MAC Control Register 11.5.11. MAC Address Low Register 11.5.11. MAC Address Hi Register 11.5.12. Multicast Address Low Register

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Section Register Name 11.5.12. Multicast Address Hi Register 11.5.13. MII Address Register 11.5.14. MII Data Register 11.5.15. Flow Control Register 11.5.16. VLAN1 Tag Register 11.5.17. VLAN2 Tag Register I2C Interface 13.16.1. Buffer Receive Register 13.16.2. Buffer_Transmit Register 13.16.3. Status Register 13.16.4. Command Register 13.16.5. Control Register 13.16.6. Clock Control Register 13.16.7. Scratch Register 13.16.8. Byte Count Register 10 USB Port

Mnemonic MULTICAST_A DD RESS_HI MII_AD DRESS MII_DATA FLOW_CONTR OL VLAN1_TAG VLAN2_TAG

Purpose

Address Access type 43h 47h 4Bh 4Fh 53h 57h

Buffer_Receive Buffer_Transmit Status Command Control Clock_Control Scratch Byte_Count

Index 0x00h Index 0x00h Index 0x04h

14.2

Power Management Controller Registers:

14.2.1. Timer Register 0 14.2.2. Timer Register 1 14.2.3. Timer Register 2

14.2.4. System Activity Enable Register 0 Sys_activ_en0 14.2.5. System Activity Enable Register 1 Sys_activ_en1 14.2.6. System Activity Enable Register 2 Sys_activ_en2 14.2.7. House-Keeping Activity Enable Register 0 House-Keeping Activity Enable 14.2.8. Register 1 14.2.9. Peripheral Inactivity Detection Register 0 Peripheral Activity Detection 14.2.10. Register 0 14.2.11. Peripheral Activity Detection Register 1 14.2.12. Address Range 0 Register 0

bs O

let o

Pr e

du o

(s) ct

so Ob -

te le

Pr

od

uc

Index 0x08h Index 0x10h

Index 0x0Ch Index 0x14h Index 0x18h

s) t(

See USB Port Chapter 0022h/ 0023h Index 060h Index 061h Index 08dh Index 062h Index 063h Index 064h Index 065h Index 066h Index 067h Index 069h Index 06Ah Index 06Bh

Timer0

Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration

Timer1

Timer2

HK_activ_en0 HK_activ_en1 Perif_inac tiv0 Perif_activ0 Perif_activ1 Add_range0-0

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Section Register Name 14.2.13. Address Range 0 Register 1 14.2.14. SMI Control Register 0 14.2.15. SMI Status Register 0 14.2.16. SMI Status Register 1 Peripheral Inactivity Status 14.2.17. Register 0 14.2.18. Activity Status Register 0 14.2.19. Activity Status Register 1 14.2.20. Activity Status Register 2 14.2.21. PMU State Register 14.2.22. General Purpose Register 14.2.23. Clock Control Register 0

Mnemonic Add_range0-1 SMI_cont0 SMI_stat0 SMI_stat1 Perif_stat0 Activ_stat0 Activ_stat1 Activ_stat2 PMU GP Clock_cont0

Purpose Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration

Address Access type Index 06Ch Index 071h Index 073h Index 074h Index 075h Index 077h Index 078h Index 079h Index 07Ah Index 07Bh Index 07Ch Index 088h

14.2.24. Doze Timer Read Back Register Doze 14.2.25. Stand-by Timer Read Back Stand-by Register 14.2.26. Suspend Timer Read Back Suspend Register 14.2.27. House-Keeping Timer Read Back HK_timer Register 14.2.28. Peripheral Timer Read Back Perif_timer Register Note 2: X is the value of the G_Base and is set to 180 0 00h.

bs O

let o

Pr e

du o

(s) ct

so Ob -

Pr te le

od

uc

Index 089h

s) t(

Index 08Ah

Index 08Bh Index 08Ch

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3 HOST INTERFACE
3.1 INTRODUCTION This Chapter describes the Memory and I/O Mapping of the STPC with details on how to configure the Cache Memory registers. The Host is the main interface between the CPU and the other integrated peripherals of the STPC. Table 3-1 below illustrates the relation of the integrated devices with reference to the Host Interface. Figure 3-1. STPC Host Layout x86

STPC ENVELOPE

Section 4 SDRAM

Host I/F

Section 8 LOCAL BUS INTERFACE

PCI Interface

IDE

LAN

US

bs O

let o

Pr e

du o

(s) ct
UARTE (RxTx)

so Ob PCI Bus

te le

ro P

uc d

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ISA

ISA Bus

IPC

PM

I/Os

I2C

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Figure 3-2. STPC Physical Memory Map

Total Pentium-CPU Real Mode Address Range
4GBytes
ROM 256kB
Controlled by RMRTCCS#

1MByte ROM 64KByte
Can be mapped to expansion bus

Shadowable Area Expansion Bus 3x64KByte

Available for Expansion bus

STPC Physical Memory Max 256MBytes

bs O

let o

ro P e

du

(s) ct

so Ob -

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ro P

uc d

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Main Memory 640KBytes

0 MByte

0 MByte

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3.2 AGENT DECODING All agents are decoded on a priority basis for instructions that are sent from the Host onto the host bus. If no agent on the Host Bus claims the cycle, it is then taken by the Host to PCI bridge (PCI North Bridge). If no agent on the PCI bridge claims the cycle it is forwarded to the ISA bridge. For PCI Memory accesses, the cycle is forwarded to the Host Bridge to be decoded in by the SDRAM Controller. PCI Master cycles follow the procedure above. For ISA Master devices, the cycle is first forwarded to the PCI Bridge and follows the procedure described above. ISA Memory cycles are forwarded in the same way as the PCI Memory cycles. 3.3 MEMORY ADDRESS MAP F i g u r e 3-2. illustrate the STPC Memory Map including the general overview of how the SDRAM controller is situated within the complete map including the STPC Frame Buffer Location.
Memory Region Address Range Description

MAIN MEMORY 0 0 0000h (640K) 0009FFFFh

SHAD OW (16K)

bs O

SHAD OW (16K)

let o

Pr e

000C0000h 000C3FFFh

du o

000C4000h 000C7FFFh

SHAD OW (16K)

000C8000h 000CBFFFh

Host access maps to the main memory and no ISA or PCI cycle will be initiated. PCI master cycles in this range maps to main memory provided they are not claimed by a PCI Slave. The STPC relies on subtractive decode before initiating an internal memory cycle. ISA master cycles in this range maps to main memory. The STPC will negate IOCHRDY if necessary. The DMA master cycles in this range maps to main memory. The STPC will actively drive the SD bus during target reads and modify main memory for target write transfers. This address segment is considered always cacheable in the L1 cache. PCI and ISA master cycles in this range, require the L1 cache. This 16K address segment can be programmed software to either map to main memory or expansion buses. Further, reads and writes can have different mappings. If mapped to main memory, this segment will behave as the 0-640K segment. If not mapped to main memory, refer to 3.2 above If mapped to the main memory, the cacheability of this address range is controlled by software. If mapped to the ISA bus, the ROMCS# signal may optionally be asserted as controlled by software. This allows the system and video/peripheral BIOS to physically reside in a single ROM device. This range has the same characteristics as that of 000C0000h000C3FFFh segment, as described above. The shadow control for this address range is provided via Shadow Control register 0 and cacheability and ROM chip-select control via Shadow Control register 3. This range has the same characteristics as that of 000C0000h000C3FFFh segment as described above, with the exception of the cacheability attribute. This address range is hardwired to be noncacheable. Shadow control for this address range is provided via Shadow Control register 0 and ROM chip-select control via Shadow Control register 3.

(s) ct

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Memory Region SHAD OW (16K)

Address Range 000CC000h 000CFFFFh

Description This range has the same characteristics as that of 000C8000h000CBFFFh segment, as described above. Shadow control for this address range is provided via Shadow Control register 0 and ROM chipselect control via Shadow Control register 3. This address range is hardwired to be non-cacheable. This range has the same characteristics as that of 000CC000h000CFFFFh segment, as described above. Shadow control for this address range is provided via Shadow Control register 1 and can be controlled at 16K resolution. ROM chip-select generation for the entire 64K range can be controlled via Shadow Control register 3. This address range is hardwired to be non-cacheable. This range has the same characteristics as that of 000CC000h000CFFFFh segment, as described above. Shadow control for this address range is provided via Shadow Control register 2 and can be controlled at 16K resolution. ROM chip-select generation for the entire 64K range can be controlled via Shadow Control register 3. This address range is hardwired to be non-cacheable. This range has the same characteristics as that of 000C0000h000C7FFFh segment, as described above. Shadow control for this address range is provided via Shadow Control register 3. If not shadowed in the main memory, cycles in this address range which are forwarded to the ISA bus will always results in an ROMCS# assertion. The cacheability of this address segment is controlled via Shadow Control register 3. This address segment is mapped to the main memory with the exception of one hole that can optionally be opened in the range 1MBytes to 16 MBytes. The address range defined for the hole is mapped to the expansion buses and is described later in this section. The addressable SDRAM memory can be different from the populated memory due to the memory remapping and the frame buffer. This is described in more detail in a later section. With the exception of the memory holes, this address range has the same characteristics as the 0-640K (compatible DOS memory) range. All cycles above the addressable SDRAM memory are forwarded to the expansion buses. Host access in this range initiates a PCI cycle and if unclaimed by a PCI slave, they are forwarded to ISA. Note that the ISA address space is only 16M. Higher addresses are aliased to this 16M space. This address segment is an alias of the 64K segment located at F0000hFFFFFh and has the same attributes except that this segment can never be shadowed into the SDRAM memory. This is also true for address E0000h, D0000h and C0000h provided I/O register Index 51h (see Section 6.5.2. ) is set correctly.

SHAD OW (64K)

000D0000h 000DFFFFh

SHAD OW (64K)

000E0000h 000EFFFFh

SHAD OW (64K)

000F0000h 000FFFFFh

TOP OF ADDRESSABL E SDRAM 0010 0 0h MEMORY (1M) TOP OF ADDRESSABL E SDRAM FFFC0000h MEMORY (4G-256K) ROM ALIAS (4G-64K)

bs O

let o

Pr e

FFFF0000 FFFFFFFFh

du o

(s) ct

so Ob -

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3.3.1. MEMORY HOLE The ISA bus is accessed through the PCI bus using subtractive decode and regardless of the address size. The ISA address bus is 24 bits wide and any PCI bus cycles which is not asserted by a PCI device will be transferred to the ISA. The 8 high bits of the address are just discared. For example, the 0xFFFFFFF0 address generated by the CPU at reset is going to be forwarded to ISA at address 0xFFFFF0. Through this way, an ISA device can be accessed at multiple locations in the CPU address space. Any 0x??xxxxxx address is going to be forwarded at ISA address 0x00xxxxxx. Only the true original address is processed on PCI bus and the address should be chosen in order to not conflict with any PCI device. If other devices are present on the ISA memory address space, an external decoding have to be implemented to avoid conflicts with this device. 3.3.2. SMM MEMORY

The STPC uses the physical memory behind the CPU address range A0000h - B0000h for the SMM memory. The SMM base address register inside CPU needs to be programmed to A0000h. The initialization of the SMM memory is controlled by RAM System management register and redirects the CPU A0000h-B0000h address range to SMM memory. After the initialization, SMM memory can only be accessed when SMIACT# is active. The cacheability of this segment is hardwired to 0. 3.3.3. ADDRESSABLE SDRAM MEMORY

Addressable SDRAM memory is a function of the size of populated SDRAM, the size of memory hole, and the shadow control of D0000h-DFFFFh and E0000h-EFFFFh segments. TOPM = The size of total physical SDRAM is defined by SDRAM Bank 3 Register. MHOLE_SIZE = The size of memory hole defined by Memory Hole Control register. REMAP_SIZE = 128KB, if none of the 8 x 16KB-segments of D0000h-EFFFFh is enabled for shadow, or 0KB, if any of the 8 x 16KB-segments of D0000h-EFFFFh is enabled for shadow. The addressable SDRAM memory =

bs O

TOPM + MHOLE_SIZE + REMAP_SIZE Note that this is an example and TOGM may not apply to all systems.

let o

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(s) ct

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3.3.4. CPU ADDRESS TO SDRAM ADDRESS MAPPING The CPU's concept of a physical address is a logical address to the STPC and is remapped to a SDRAM physical address. This section refers to the CPU's physical address as the "CPU address" and to the SDRAM's physical address as the "SDRAM address". STPC also defines a memory hole to allow the existence of memory devices on the PCI or ISA buses. The size of the CPU address space is increased by these memory holes, if they exist. CPU address space D0000h to EFFFFh is mapped to the add-in card BIOS area. If this ROM space is not shadowed, then the CPU address space is increased by another 128 KBytes (also see Section 3.6.1. ). For example: Total populated SDRAM = 4 MBytes Memory hole size = 1 MByte Memory hole starting address = 20 0 0h Shadow feature for D0000h to EFFFFh = disabled

The total CPU memory = 4 MBytes+ 1 MByte + 128 KBytes = 5 MBytes plus 128 KBytes Since a 1 MByte memory hole exists, the CPU address space is increased by 1 MByte and becomes 5 MBytes. The CPU address between 4 MBytes and 128 MBytes above this is mapped to the memory hole. Since the shadowing of the CPU address range D0000h to EFFFFh reserved for add-on card B I O S is not enabled, the CPU memory is increased by 128 KBytes to make use of this SDRAM space that no device accesses. The total CPU memory then becomes 5 MBytes plus 128 KBytes.

bs O

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3.4 IO ADDRESS MAP. Table 3-1. IO Map Space
IO address 0000h-000Fh 0020h-0021h 0022h 0023h 0040h-0043h 0060h-0064h 0070h-0071h 0080h-008Fh 00A0h-00A1h 061h 00C0h-00DFh 0CF8h 0CFCh-0CFFh Description 8237 DMA controller 1 registers. 8259 Interrupt controller 1 registers. STPC specific configuration registers index port STPC specific configuration registers data port 8254 Timer/Counter registers. Keyboard shadow registers. NMI Mask control registers. DMA Page registers. 8259 Interrupt controller 2 registers. ISA standard Port B. 8237 DMA controller 2 registers. PCI configuration Address register. PCI configuration Data register. Notes 1

1 1 1 1 1 1

The STPC implements a number of registers in IO address space. This is visible in the registers with access = 0022h/0023h. These registers use the index and data programming system where the index to which the data is to be written to is programmed in register 0022h and the data is written to register 0023h. These registers occupy the map in the IO space in the table above:Table 3-1 Notes:

1. This address range is partially decoded. Refer to the Register Description section for more de tails. 2.This address is occupied only if the STPC is strapped to look like a mother-board VGA. 3.4.1. PCI CONFIGURATION ADDRESS MAP The STPC occupies Device number 0 slot on the PCI bus and implements a number of registers in PCI configuration address space. These registers occupy the following map (see Table 3-2): Table 3-2. PCI Configuration Address Space

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Offset 00h-01h 02h-03h 04h-05h 06h-07h 08h 40h

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Description Vendor Identification register Device Identification register PCI Command register PCI Status register PCI Revision ID register PCI Control register

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3.5 CACHE RELATED REGISTERS The STPC supports two caching modes, write-through and write-back. For both modes, sdram read accesses are copied into the cache, and future accesses then return the cache copy with no access to sdram. The situation is different for write access; for the write-through mode, a write updates both the sdram and the cache, whereas in the write-back mode, a write updates the cache only with the sdram update taking place later. The write-back mode offers improved performance over the write-through mode. Two cache levels are generally available, level 1 (L1), within the CPU core, and level 2 (L2), within the chipset core (between the CPU and the sdram Controller). For the STPC product range, the L2 cache controller is included but not usuable because the related pins are not externally provided. Therefore the L2 Cache configuration registers control the CPU L1 Cache usage . 3.5.1. CACHE ARCHITECTURE REGISTER 0 This register controls various attributes of the L2 and L1 cache.
Cash_Arc0 7 Rsv 6 BAO Access = 0x22/ 0x23 5 4 3 2 L1 WB SRAM L2 B Default value after reset = 0 0 0000h Mnemonic R sv BAO L1 WB SR AM

Bit Number Bit 7 Bit 6 Bit 5 Bit 4-3 Bit 2

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L2 WBC L2 BC

Description Reserved Burst addressing order. Should be set to 0. L1 write back indication. 0: Not supported 1: Supported SRAM type. These bits control the type of SRAMs used to construct L2 cache. (See Table 3-3) Number of L2 banks. When programmed to 2 banks, L2 interleaving is enabled. 0: One bank 1: Two banks L2 write back control. Writing on this bit has no effect L2 cache enable. 0: Disabled 1: Enabled

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0 L2 BC

Regoffset = 0x20h

1 L2 WBC

Table 3-3. Bits 4-3 SRAM Type
Bit 4 0 0 1 1 Bi t 3 0 1 0 1 L2 cache SRAM type asynchronous SRAM synchronous burst pipelined SRAM synchronous burst SRAM reserved

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3.5.2. CACHE ARCHITECTURE REGISTER 1 This register controls various attributes of L2 cache.
Cash_Arc1 7 6 L2 CS Access = 0022h/ 0023h 5 4 3 2 Rs v Rs v Default value after reset = 0 0 0000h Mnemonic L2 CS R sv R sv R AWE R sv Regoffset = 0x21h 1 R AWE 0 Rs v

Bit Number Bits 7-5 Bit 4 Bits 3-2 Bit 1 Bit 0

Description L2 cache size. (See Table 3-4) Reserved Reserved Read around write enable. 0: Reads can not proceed around any posted writes 1: Reads can go around a posted write if it is to a different address to the posted writes Reserved.

Table 3-4. L2 Cache Size
Bit 7 0 0 0 0 1 1 Bit 6 0 0 1 1 0 0 Bit 5 0 1 0 1 0 1 L2 Cache Size 64Kb 128Kb 256Kb 512Kb 1 MB 2 MB

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3.5.3. CACHE ARCHITECTURE REGISTER 2
Cash_Arc2 7 Rs v 6 S HDD Access =00 22h/ 0023h 5 4 3 2 CW EPW C DHAW E BAW S Default value after reset = 11111111h Mnemonic R sv S HD D Regoffset = 0x22h 1 T AWS 0

Bit Number Bit 7 Bit 6

Bit 5

C WEPW

Bit 4 Bits 3-2 Bits 1-0

CDH AWE BAWS T AWS

Description Reserved. Slow host data driver. 0: Fast, One clock to drive the HD bus 1: Slow, two clocks to drive HD bus Cache write enable pulse width. 0: 1 clock wide 1: 1.5 clocks wide Applicable to asynchronous SRAMs only. Must be `0' for synchronous SRAMs. Cache data hold after write enable. 0: Data removed in the same clock as write enable trailing edge 1: Data is kept valid for 1 extra clock after write enable Must be a `1' if 1.5 clocks wide write enable pulse width is selected via bit 5 above. Burst access wait states. (See Table 3-5) Tag access wait states. (See Table 3-6)

Table 3-5. Burst Access Wait States
Bit 3 0 0 1 1 Bit 1 0 0 1 1 Bit 2 0 1 0 1 Bit 0 0 1 0 1

Burst access wait states fastest 1 clock slower than fastest 2 clocks slower than fastest 3 clocks slower than fastest

Table 3-6. Tag Access Wait States

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Tag access wait states fastest 1 clock slower than fastest 2 clocks slower than fastest 3 clocks slower than fastest

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3.6 ADDRESS DECODE RELATED REGISTERS The following registers are all 8-bit. They are accessed by setting the Configuration Index Port (22h) to the Regoffset shown, and then reading or writing the appropriate values from the Configuration Register Data Port (23h). 3.6.1. MEMORY HOLE CONTROL REGISTER This 8-bit register defines the enable, size, and starting address of memory hole. Any memory accesses to this memory hole are directed to PCI/ISA bus.
MEM_HOLE 7 MHE 6 Access = 0x22/ 0x23 4 3 Regoffset = 0x24h 1 MHSA 0

5 2 M HS Default value after reset = 0 0 0000h Mnemonic M HE M HS M HSA

Bit Number Bit 7 Bits 6-4 Bits 3-0

Description Memory Hole Enable. This bit controls the enable of memory hole function. 0 = disabled 1 = enabled Memory Hole Size. These bits control the size of memory hole (See Table 3-7) Memory Hole Start Address. These bits control the bits 23-20 of the memory hole starting address. The memory hole starting address must be aligned to the hole size.

Table 3-7. Memory Hole Size
Bit 6 0 0 0 1 Bit 5 0 0 1 1 others

Programming notes:

This memory hole is also non-cacheable.

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Bit 4 0 1 1 1

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Memory Hole Size 1 MB 2 MB 4 MB 8 MB reserved

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3.6.2. SHADOW CONTROL REGISTER 0 This 8-bit register controls the read/write attributes of the memory located at C0000h-CFFFFh. Each 16k of the whole 64k is controlled by 2 bits, one for read and one for write.
SHADOW_0 7 RC1 6 W C1 Access = 0022h/ 0023h 5 4 3 2 RC2 W C2 RC 3 W C3 Default value after reset = 0 0 0000h Mnemonic R C1 Regoffset = 0x25h 1 RC 4 0 WC4

Bit Number Bit 7

Bit 6

W C1

Bit 5

R C2

Bit 4

W C2

Bit 3

R C3

Bit 2

W C3

Bit 1

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W C4

Description Read Control CC000h-CFFFFh. This bit controls the read attribute of the CC000h-CFFFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Write Control CC000h-CFFFFh. This bit controls the write attribute of the CC000h-CFFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle Read Control C8000h-CBFFFh. This bit controls the read attribute of the C8000h-CBFFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Write Control C8000h-CBFFFFh. This bit controls the write attribute of the C8000h-CBFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle Read Control C4000h-C7FFFh. This bit controls the read attribute of the C4000h-C7FFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Write Control C4000h-C7FFFFh. This bit controls the write attribute of the C4000h-C7FFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle Read Control C0000h-C3FFFh. This bit controls the read attribute of the C0000h-C3FFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Write Control C0000h-C3FFFFh. This bit controls the write attribute of the C0000h-C3FFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle

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Programming Notes: There is single cacheability bit for the 32k Video BIOS segment (C0000h-C7FFFh) located in Shadow Control register 2. C7FFFFh-CFFFFh segment has the cacheability bit hardwired to `1' (enabled). If shadow is enabled for read/write cycles, read from and write to this area are directed to the system memory. Or else the cycles are forwarded to the expansion buses.

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3.6.3. SHADOW CONTROL REGISTER 1 Similar to Shadow Control Register 0, this 8-bit register controls the read/write attributes of the memory located at D0000h-DFFFFh.
SHADOW_1 7 SRC 6 SW C Access =00 22h/ 0023h 5 4 3 2 SW C SW C SRC SW C Default value after reset = 0 0 0000h Mnemonic SR C Regoffset = 0x26h 1 SRC 0 SW C

Bit Number Bit 7

Bit 6

S WC

Bit 5

S WC

Bit 4

S WC

Bit 3

SR C

Bit 2

S WC

Bit 1

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S WC

Description Shadow Read Control DC000h-DFFFFh. This bit controls the read attribute of the DC000h-DFFFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Shadow Write Control DC000h-DFFFFh. This bit controls the write attribute of the DC000h-DFFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle Shadow Write Control D8000h-DBFFFh. This bit controls the read attribute of the D8000h-DBFFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Shadow Write Control D8000h-DBFFFh. This bit controls the write attribute of the D8000h-DBFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle Shadow Read Control D4000h-D7FFFh. This bit controls the read attribute of the D4000h-D7FFFh memory 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Shadow Write Control D4000h-D7FFFh. This bit controls the write attribute of the D4000h-D7FFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle Shadow Read Control D0000h-D3FFFh. This bit controls the read attribute of the D0000h-D3FFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Shadow Write Control D0000h-DFFFFh. This bit controls the write attribute of the D0000h-DFFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle

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Programming Notes: This entire 64K segment has the cacheability bit hardwired to `0' (disabled)

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3.6.4. SHADOW CONTROL REGISTER 2 Similar to Shadow Control Register 0, this 8-bit register controls the read/write attributes of the memory located at E0000h-EFFFFh.
SHADOW_2 7 RC 6 WC Access = 0022h/ 0023h 5 4 3 2 RC WC RC WC Default value after reset = 0 0 0000h Mnemonic RC Regoffset = 0x27h 1 RC 0 WC

Bit Number Bit 7

Bit 6

WC

Bit 5

RC

Bit 4

WC

Bit 3

RC

Bit 2

WC

Bit 1

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Description Read Control EC000h-EFFFFh. This bit controls the read attribute of the EC000h-EFFFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Write Control EC000h-EFFFFh. This bit controls the write attribute of the EC000h-EFFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle Read Control E8000h-EBFFFh. This bit controls the read attribute of the E8000h-EBFFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Write Control E8000h-EBFFFFh. This bit controls the write attribute of the E8000h-EBFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle Read Control E4000h-E7FFFh. This bit controls the read attribute of the E4000h-E7FFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Write Control E4000h-E7FFFFh. This bit controls the write attribute of the E4000h-E7FFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle Read Control E0000h-E3FFFh. This bit controls the read attribute of the E0000h-E3FFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Write Control E0000h-EFFFFh. This bit controls the write attribute of the E0000h-EFFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle

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Programming Notes: This entire 64K segment has the cacheability bit hardwired to `0' (disabled)

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3.6.5. SHADOW CONTROL REGISTER 3 This 8-bit register controls the cacheability attributes of C0000h-C7FFFh and F0000h-FFFFFh shadow segments.
SHADOW_3 7 SMRAM 6 C CF Access = 0022h/ 0023h 5 4 3 2 CC C Rs v R svMHR 256MB Default value after reset = 0 0 0000h Mnemonic Regoffset = 0x28h 1 R CF 0 WC F

Bit Number

Bit 7

S MRAM

Bit 6

CCF

Bit 5 Bits 4 Bit 3 Bit 2 Bit 1

C CC R sv MHR

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W CF

Description SMRAM Initialization Enable. This bit controls whether CPU accesses in A0000h-BFFFFh address range are decoded as VGA frame buffer access or SMRAM access. 0 = A0000h-BFFFFh is interpreted as VGA frame buffer access 1= A0000h-BFFFFh is interpreted as SMRAM access. The STPC allows for 128KBytes of SMRAM. Physically this memory is located in the system memory behind the higher address range. This area of the system memory is normally unused since this address range is normally mapped to frame buffer which has its own memory. When the CPU is operating in SMM, accesses in the range of A0000-BFFFFh goes to SMRAM instead of VGA frame buffer. The rest of the address map remains unchanged. The address range A0000h-BFFFFh is always non-cacheable. Cache Control F0000h-FFFFFh. This bit controls the cacheability of F0000h-FFFFFh block when the shadow function is enabled. 0 = cacheability disabled 1 = cacheability enabled Cache Control C0000h-C7FFFh. This bit controls the cacheability of C0000h-C7FFFh block when the shadow function is enabled. 0 = cacheability disabled 1 = cacheability enabled Reserved. HCLK - MCLK Relation, Should be set to 0 if MCLK is greater or equal to HCLK. Should be set to 1 if HCLK is greater than MCLK Enable 256MByte support Read Control F0000h-FFFFFh. This bit controls the read attribute of F0000h-FFFFFh memory. 0 = shadow disabled for read cycle 1 = shadow enabled for read cycle Write Control F0000h-FFFFFh. This bit controls the write attribute of F0000h-FFFFFh memory. 0 = shadow disabled for write cycle 1 = shadow enabled for write cycle

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Programming notes: The rest of the shadow RAM segments have the cacheability bits hardwired to `0' (disabled). T h i s register also provides control over the address range for which ROM chip-select (ROMCS#) will be asserted allowing various BIOSes (system, video, disk etc.) to be imple-

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mented in a single part. Bit 7 of this register also provides accessibility to the SMM mode RAM (SMRAM). 3.7 HOST SDRAM CONTROLLER REGISTERS The STPC manages 4 Memory Banks (if DIMM sockets are used they can be populated with either single or double sided 64-bit data DIMMs). For supported SDRAM densities see the datasheet Section 3.3.3. . Configuration registers 30-33 provide the top addresses for each bank. Any bank can be skipped by the top addresses of two consecutive banks having the same address. 3.7.1. MEMORY BANK 0 REGISTER - C.I. 30H (MEMORY__BANK0) This 8-bit register controls the top address of memory bank 0. Register bit 7-0 corresponding to memory address bits 27-20. Bank 0 Top Address = Memory Bank0 size in MBytes -1. Bank 1 Top Address = Memory Bank0 + Memory Bank1 size in MBytes -1 This register defaults to 07h. Example 1: Memory Bank0 = 4MB Memory Bank1 = 4MB Bank 0 Top Address = 4 -1= 3= 03h Bank 1 Top Address = 4 + 4 - 1 = 07h Bank 2, 3 Top Address = 07h

Example 2: for use with double sided DIMMs Memory Bank0 = 32MBytes (dbl. sided DIMMS) Memory Bank1 = 32MBytes (dbl. sided DIMMS) Bank 0 Top Address = 16 - 1 = 15 = 0Fh Bank 1 Top Address = 16 + 16 - 1 = 31 = 1Fh

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3.7.4. MEMORY BANK 3 REGISTER - C.I. 33H (MEMORY_BANK3) This register controls the top address of memory bank 3. 3.7.5. SDRAM REFRESH REGISTER This refresh register also contains a number of host clock settings for the SDRAM refresh interval.
SDRAM_Ref 7 RE 6 5 Access = 0022h/0023h 4 3 RC Default value after reset = 30h 2 1 Regoffset = 039h 0

Bit Number Bit 7 Bits 6-0

Mnemonic RE RC

Description Refresh Enable. This bit must be programmed to `0' for normal operation Refresh Cycle. (HCLK frequency in MHz * 15.6us) >> 4

* Examples: (rounded down to nearest integer) round_down( (75MHz * 15.6us ) >> 4 ) = 73 = 49h round_down( (66MHz * 15.6us ) >> 4 ) = 65 = 41h round_down( (60MHz * 15.6us ) >> 4 ) = 58 = 3Ah round_down( (50MHz * 15.6us ) >> 4 ) = 48 = 30h Programming notes:

The refresh interval should be reset to the smallest likely run time value (typically 48 HCLKs) to provide warm up cycles for the SDRAM. A refresh request is generated whenever this register is written to without setting the refresh enable bit.

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3.8 ACCESSING CONFIGURATION REGISTERS The Host interface and the Local Bus Interface are programmed identically. To access all the internal configuration registers, the programmer will need to program the Index (address) and data registers of the required interface through port 22h/23h. The principle of the programming is to fix the address of device to a location that the user requires and to always dress it at that location. The steps required to access any of the internal registers are as follows: 1) Select the interface you want to programme. Each interface is described as a device and both have a number. The Local Bus device number is 6 and the Host device number is 7. The below example code describes how the devices are accessed and the Host device is used. Select Host interface base programming option in RBI, by writing 0x00 in register 0x11 and 0x07 inregister 0x10(0x06 for the Local Bus, see Section 8.4 for more details)(index value 0x11 and 0x10 accessed through I/O 22h/23h address)
IOWRITE8(0x22,0x10); IOWRITE8(0x23,0x07); IOWRITE8(0x22,0x11); IOWRITE8(0x23,0x00);

2) Select the Host interface address. Assume that HOST_BASE is the address of the Host interface I/O space.
IOWRITE8(0x22,0x12); IOWRITE8(0x22,0x13); IOWRITE8(0x23,HOST_BASE >>8); IOWRITE8(0x23,(HOST_BASE &0xFF) | 0x03);

The host interface registers are then accessed with HOST_BASE as the index register and HOST_BASE+4 as the data register, as shown below. 3) Writing into any Internal Register of the Host Interface:
IOWRITE8(HOST_BASE,offset); IOWRITE32(HOST_BASE+4,data);

Here the "offset" index address is as mentioned in the register table shown above. The 32bit "data" is written into the register.

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4) Reading from any internal register of Host Input
IOWRITE8(HOST_BASE,offset); IOREAD32(HOST_BASE+4,data);.

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Here the "offset" index address is as mentioned in the register tables shown above. The 32-bit "data" is expected to be read from the internal register. One constraint is that the Local Bus address must be set at multiples of 8h.

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4 SDRAM CONTROLLER
4.1 INTRODUCTION This chapter describes the mapping of the CPU memory and IO address spaces. Details of memory shadowing and cachability by software control and the Memory Hole for ISA BIOS are given. The actual interface to the external SDRAM modules is presented. Also introduced in this chapter are the PCI configuration space mapping registers, further details are in the chapter relating to the PCI Bus Controller. 4.2 MEMORY CONTROLLER The STPC handles the memory data bus directly, controlling from 8 MBytes to 256 MBytes. The SDRAM controller supports accesses to the Memory Banks to/from the CPU (via the host) and the local Bus which can be populated with either single-sided or double-sided 64-bit memory devices. Parity is not supported. The SDRAM controller only supports 64 bit wide Memory Banks.

The SDRAM Controller supports buffered or unbuffered SDRAM but not EDO or FPM modes. SDRAMs must support Full Page Mode Type access. The STPC Memory Controller provides various programmable SDRAM parameters to allow the SDRAM interface to be optimised for different processor bus speeds S