AN1943 APPLICATION NOTE
Design Guide for the Turbo uPSD33xx Series and DK3300
INTRODUCTION
As shown in Figure 1., the PSD33xx family is a series of 8051-class microcontrollers (MCUs) containing a new fast Turbo 8032 core with a large dual-bank flash memory, a large SRAM, many peripherals, programmable logic, and JTAG In-System Programming (ISP). This document shows the steps to create a design using the DK3300 development board, the software development tool PSDsoft Express, and Ulink USB-JTAG debugger from Keil Software. The project and debug environment (IDE), using the Raisonance development suite for Turbo PSD, is currently not featured in this Application Note. This will be addressed in the near future. Please see the PSD on-line resources page for new documentation at: http://www.st.com/stonline/products/families/ memories/psm/soft_c2.htm. PSDsoft has, though, been upgraded to connect to ST's JTAG programming cable (FlashLINK) or Raisonance's JTAG programming cable (R-LINK). It is important to make the correct selection in PSDsoft, using the HW Setup configuration menu. Figure 1. General Block Diagram of the PSD33xx
uPSD33XX
(3) 16-bit Timer/ Counters (2) External Interrupts Turbo 8032 Core PFQ & BC 1st Flash: 64K, 128K, or 256K Bytes
Programmable Memor y Decode and Page Logic
P3.0:7
I2 C
2nd Flash: 16K or 32K Bytes SRAM: 2K, 8K, or 32K Bytes
UART0 (8) GPIO, Port A (80-pin only) (8) GPIO, Port 3 General Pur pose Programmable Logic, 16 Macrocells (8) GPIO, Port B (2) GPIO, Port D (4) GPIO, Port C
PA0:7 PB0:7 PD1:2
(8) 10-bit ADC Optional IrDA Encoder/Decoder
SYSTEM BUS
P1.0:7
(8) GPIO, Port 1
PC0:7
JTAG ICE and ISP 8032 Address/Data/Control Bus (80-pin device only) Super visor : Watchdog and Low-Voltage Reset VCC, VDD, GND, Reset, Crystal In
UART1
SPI 16-bit PCA (6) PWM, CAPCOM, TIMER
MCU Bus
P4.0:7
(8) GPIO, Port 4
Dedicated Pins
AI08875
January 2005
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TABLE OF CONTENTS
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. General Block Diagram of the PSD33xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PSD33xx FAMILY OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. uPSD3334D Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dk3300 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. DK3300 Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DESIGN EXAMPLE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Design Example Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Design Example Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ENTERING DESIGN IN PSDsoft EXPRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Select MCU and Initial Placement of Flash in Code Space or Data Space. . . . . . . . . . . . . . . . 10 Figure 6. MCU Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. Page Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 C hip-Select Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. Chip-Select Definition for 8K byte SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Chip-Select Definition for Flash Memory Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11.External Chip-Select Definition for LCD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I/O Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 12.Logic Equation for Signal LCD_rw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 U ser-Defined Node Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13.4-bit Down-Counter with Automatic Reload of Initial Count . . . . . . . . . . . . . . . . . . . . . . 18 Figure 14.D-Register Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Edit ABEL HDL Statements for PLD Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 15.Design Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 A dditional PSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 C Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 16.Coded Example Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fitting Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Merging 8032 Firmware with PSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 17.Merging the Example Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 JTAG Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 18.Programming with FlashLINK/R-LINK JTAG Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 WATC H IT RUN ON DK3300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 USING uVISION2 AND ULink JTAG DEBUGGER FROM KEIL SOFTWARE, INC.. . . . . . . . . . . . . . 27
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Loading a Keil uVision2 Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 B uilding the Project and Programming the Turbo PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 R unning Keil's ULink - USB to JTAG Debugger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 19.Setting up ULink JTAG Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 20.Setting up ULink Target Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 21.Setting up the ULink Target Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 22.Tool Menu `Load' Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 23.Keil's ULink JTAG Debugger After Successfully Invoked . . . . . . . . . . . . . . . . . . . . . . . . 30 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 1. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 APPENDIX A.PSDsoft EXPRESS PROJECT SUMMARY FILE, DK3300_1.SUM . . . . . . . . . . . . . . . 32 APPENDIX B.PSDsoft EXPRESS ABEL HDL DESIGN FILE DK3300_1.ABL. . . . . . . . . . . . . . . . . . 35 APPENDIX C.PSDsoft EXPRESS FITTER REPORT FILE DK3300_1.FRP . . . . . . . . . . . . . . . . . . . . 38 APPENDIX D.DK3300 SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 24.MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 25.Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 26.Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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PSD33xx FAMILY OVERVIEW
The PSD33xx family is a turbo 4-clock per instruction 8032 MCU capable of being clocked up to 40MHz at 3.3V or 5.0V at industrial operating temperature range. Currently there are twelve family members that contain different combinations of flash memory size, operating voltage, and packaging (please see the full datasheet). In this Application Note, we will use uPSD3334D-40U6 as our example. The term "Turbo PSD" is used throughout the remainder of the document for brevity (see the Turbo PSD block diagram in Figure 2). The Turbo PSD has a unique memory structure that includes two independent flash memory arrays (Main and Secondary) capable of read-while-write operation. This is ideal for In-Application Programming (IAP) because the 8032 can fetch instructions from one flash array while erasing/writing the other array. Individual sectors of each flash memory array can be mapped to virtually any 8032 address by the Decode PLD (DPLD) for total flexibility. The Turbo PSD also contains a Page Register whose outputs feed the inputs of the DPLD. This allows paging (or banking) of flash memory to break the 8032's inherent limit of 64K byte addresses. The 8032 may write to the Page Register at runtime. For more complex designs, the Turbo PSD is capable of placing each of the flash memory arrays (Main or Secondary) into 8032 code address space, into 8032 data space, or into both code and data space on the fly. Mapping flexibility like this supports IAP because either flash array may be temporarily placed into data space while the firmware is updated, then moved back into code space when finished, all under control of the 8032. Many peripherals are available in this Turbo PSD, including: two UART channels, one IrDA channel, one SPI channel, one I2C channel, six PWM channels, eight 10-bit ADC channels, nine Timer/Counters, a watchdog timer, low-VCC detection with reset-out, a general purpose PLD, many GPIO and a USB-JTAG Debugge r. All of the peripherals on Ports 1, 3, and 4 are controlled using 8032 Special Function Registers (SFRs). I/ O Signals on ports A, B, C, and D are controlled one of two ways: 1. by a block of xdata memory mapped control registers, whose base address (csiop) can be mapped anywhere using the DPLD; and 2. by the programmable logic. In addition, Turbo PSD offers a Cross-Bar I/O, which means that Peripheral functions on Port 1 are also available on Port 4 (cross-bar switch), providing more flexibility. There is no need to sacrifice one peripheral function when two functions are available on a single pin, just use the other port. The JTAG channel on Port C is used for ISP and debug of the 8032 MCU core. ISP is ideal for rapid code iterations during firmware development and for Just-In-Time inventory management during manufacturing. JTAG ISP eliminates the need for sockets and pre-programmed devices, and requires no participation of the 8032. JTAG debug eliminates the need for expensive and intrusive hardware In-Circuit Emulator (ICE).
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Figure 2. uPSD3334D Block Diagram
Turbo uPSD33XX
Turbo 8032 MCU Divide or Pass (7) VCC and GND (2) Crystal Connection (1) Reference Voltage Input (80-pin only) Port 1: Available Functions (2) 8032 Timer 2 (2) UART1 - IrDA (4) SPI (These signals are alternately available on Port 4)
256 byte SRAM/SFRs (8) 10-bit ADC SPI UART1 w/IrDA (3) 16-bit Timer/Cntrs UART0 Local MCU Bus 8032 Interrupts I2C PCA: (6) 16-bit Timer/ Counter Units, CAPCOM, PWM (8) 8032 Data/Low Addr (4) 8032 High Address Supervisor, WDT/LVD System Reset JTAG Debut and ISP Memory Interface with Prefetch & Branch Cache General PLD, 16 Macrocell Main Flash: 64K/128K/ 256 Bytes 2nd Flash: 16K/32K Bytes
(8) GPIO
(8) ADC
Port 3: Available Functions (2) 8032 Timer 1 (2) UART0 (2) Interrupts (2) I2C Port 4: Available Functions (2) 8032 Timer 2 (2) UART1IrDA (4) SPI
(8) GPIO
(8) GPIO 10mA
(2) PCA CLK Inputs (6) PCA: PWM/ CAPCOM
(8) MCU AD0-AD7 (80-pin Pkg Only) (4) MCU A8-A11 (80-pin Pkg Only) (1) Reset Input Port C: Available Functions (4) GPIO (4) Dedicated JTAG (2) Extended JTAG (2) SRAM Battery B/U
Memory Bus
Port A: Available Functions (80-pin only)
Sector Selects
(8) GPIO
(8) PLD I/O
Port B: Available Functions SRAM: 2K/8K/32K Bytes (8) GPIO 256 Control Registers Port D: Available Functions Decode PLD & Page Logic (2) GPIO - 80-pin (1) GPIO - 52-pin (2) Chip Selects - 80-pin (1) Chip Select - 52-pin
AI09606
(8) PLD I/O
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DK3300 OVERVIEW
A picture of the DK3300 board is shown in Figure 3. Board layout and schematics are in the Appendix. Connectors CON1, CON2, and CON3 provide easy access to all Turbo PSD signals for expansion or testing. A list of jumpers JP0 - JP16 and their functions can be found on the DK3300 board's silk screen. For more detailed information on these jumpers, please refer to APPENDIX D., DK3300 SCHEMATICS and the DK3300 User's Guide. UARTs are available on connectors marked UART0 and UART1. The FlashLINK/R-LINK/ULink JTAG ISP cable connects at the connector, FLASH_LINK. The DK3300 also has a 16-character or graphical LCD interface and a full featured real-time clock with a back-up battery, a serial EEPROM, IrDA transceiver, PWM control over LCD brightness, and a rotary encoder knob for selection of various demo applications. Figure 3. DK3300 Development Board
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DESIGN EXAMPLE BLOCK DIAGRAM
This simple design example is represented by the block diagram of Figure 4, and the memory map of Figure 5., page 8. The Flash memory is paged, and few of the 8032 interfaces (e.g., ADC, PWM, UART) are configured and used. The idea is to touch several aspects of the PSD that may be unfamiliar to a typical 8051 user and to give you an idea of how to use the design tools and become familiar with Turbo PSD architecture. Figure 4. Design Example Block Diagram
uPSD3334D-40U6
A8-A15
8
ADDR
ADDR
PWM Jumper ADC
8 16
PWM Latch ADC AD0-AD7
16 16 ADDR 15
256KB Main Flash (data) fs0-fs7
DATA
pins A0-A11 12 pins P0.0-P0.7
8 DPLD 8
csboot0csboot3 rs0
8
DATA
pin_RESET RESET pin_XTAL1 40MHz pin_XTAL2 pin P3.0 (RxD) pin P3.1 (TxD)
13 13
Page Reg. (from Control Registers)
_RESET_IN
32KB Secondary Flash (code) 8KB SRAM Data Bus Repeater
pin PC0 (TMS) pin PC1 (TCK) pin PC2 (TSTAT) JTAG ISP pin PC3 (TERR) pin PC2 (TDI) pin PC2 (TDO) 16 PLD Macrocells
4 1 2 1
8032
XTAL1
psel0psel1 csiop
8
256 Control Regs.
XTAL2
16
RxD TxD ALE
Initial count Down counter
RS-232 Transceiver UART0
Pin PB0 (term_count)
8
pin PB5 (LCD_rs) pin PB6 (LCD_rw) pin PB6 (LCD_e) pins PA0-PA7 (LCD_d0 - LCD_d7)
REG SELECT READ/WRITE CHIP SELECT D0-D7
LCD MODULE
AI09607
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The 8032 outputs a repetitive PWM pulse train with a slowly varying pulse width to an RC network which converts the pulse train into a slowly sweeping DC voltage (0V to 3.3V). This DC signal is looped back into an ADC input. The 8032 will write the resulting HEX ADC conversion value to the LCD so you can watch the results. The RC network and loopback is implemented with two jumper blocks (JP13 and JP14) on the DK3300 board. Additionally and independently, a 4-bit, auto-reloading down-counter is created using PLD MicroCells. The 8032 directly loads the initial count value into four MicroCells, and that count is automatically loaded into another four MicroCells that create the 4-bit down-counter. Reloading occurs each time the counter reaches terminal count of zero. Terminal count is indicated externally by a pulse on a Turbo PSD output pin. The down-counter is clocked by ALE signal (ALE was random choice, could be any signal). The 8032 may load a different initial count at anytime, creating a variable divider of the ALE signal. The LCD module is connected to the Turbo PSD via a Port A for data and Port B for some glue logic and a chip-select signal. Port A is operating is an special data bus repeater mode this example, called Peripheral I/O mode. 8032 data will pass through Port A only for a given address range specified in PSDsoft Express (see Figure 5). Figure 5. Design Example Memory Map
Code Space (_PSEN)
Page X Page 0 Page 1
Data Space (_RD and _WR)
Page 2 Page 3 Page 4 Page 5 Page 6 Page 7
FFFF
FFFF
fs0
32K bytes uPSD (data) Main Flash
fs1
fs2
fs3
fs4
fs5
fs6
fs7
32K bytes uPSD (data) Main Flash
32K bytes 32K bytes uPSD uPSD (data) (data) Main Flash Main Flash
32K bytes 32K bytes uPSD uPSD (data) (data) Main Flash Main Flash
32K bytes 32K bytes uPSD uPSD (data) (data) Main Flash Main Flash
nothing mapped nothing mapped LCD _e and psel CSIOP 4000 3FFF 2000 1FFF 0000 csboot1
8K bytes uPSD Secondary Flash
chip select and data bus repeater for LCD control regs for Ports A, B, C, and D (xdata) 8K PSD SRAM (xdata) nothing mapped 8032 SFRs and idata SRAM Common Memory Across All Data Pages
8000 6200-7FFF 6100-61FF 6000-60FF 4000-5FFF
rs0
csboot0
8K bytes uPSD Secondary Flash
0100-3FFF 0000-00FF
AI09608
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The memory map in Figure 5., page 8 shows that in this design example, 16K byte secondary flash memory is used for code space, and the 256K byte main flash memory is used for data space, banked over eight pages. The nomenclature fsx, csbootx, rs0, csiop, and psel in Figure 5 refer to the individual internal Turbo PSD memory segments. The Turbo PSD main flash memory has a total of eight 32-Kbyte segments (fs0..fs7). The Turbo PSD secondary flash memory has a total of four 8-Kbyte segments (csboot0csboot3), although only csboot0 and csboot1 are used in this design example. The Turbo PSD 8-Kbyte SRAM has a single segment (rs0). A group of PSD control registers which control I/O ports A, B, C, and D lie in a 256-byte xdata address space whose base address is named csiop. The Turbo PSD has a data bus repeater feature that is enabled over a given address range as specified by psel. Figure 5 also shows one external memory select signal, LCD_e, for the LCD module. This memory map is specified using the software tool PSDsoft Express. Each memory segment can be placed at virtually any address, which provides an infinite number of mapping schemes. This is just one example. We will keep things simple for this particular application note, meaning the 8032 will "boot" and run code contained completely within the 16-Kbyte secondary flash in code space and we will treat the 256-Kbyte main flash as data only. However, this memory map may grow with the needs of your project. For example, if a large flash memory is needed for code space and IAP is required, a slight variation of the map in Figure 5 can accomplish this. The 8032 can boot from secondary flash (secondary flash resides in code space from 0-3FFF as in Figure 5), then the 8032 can calculate a checksum on the main flash and then program the main flash if necessary (main flash memory resides in data space from 8000-FFFF on eight pages as in Figure 5). After the contents of main flash are verified, the 8032 can write to special register, called the VM Register within the csiop register block, to "reclassify" the main flash memory from data space to code space. After which, the 8032 will have access to 256 Kbytes of flash for code in code space, paged across eight code pages in upper memory (8000-FFFF), and the 8032 will have access to 32 Kbytes of flash for code in code space common to all pages in lower memory (0-3FFF). At that point no flash memory will reside in data space. Upon reset, the memory map is reset to look like Figure 5 again. The VM Register can be accessed by the 8032 at runtime to perform a variety of manipulations. PSDsoft is used to set the initial value of the VM Register upon power-up. Future Application notes will illustrate various memory schemes.
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ENTERING DESIGN IN PSDsoft EXPRESS
Highlights of the design process will be given here. The steps are simple and navigation though PSDsoft Express is easy. Invoke PSDsoft Express and follow along if you wish and also consult the DK3300 User's Guide for more information. PSDsoft Express is free, and you will need to download and install the latest version (8.0 or later) from our website at www.st.com/psd, then look for "Software Downloads." Invoke PSDsoft Express and Create Project: 1. Start PSDsoft Express. 2. C reate a new project. 3. Select your project folder and name the project (in this example, name the project "DK3300_1" in the folder PSDexpress\my_project). Select MCU and Initial Placement of Flash in Code Space or Data Space 1. Select an MCU. In this case it is STMicroelectronics, then uPSD33xx, then uPSD3334D. 2. Select the main flash memory to reside in 8032 data space at power-up (means that the 8032 _RD and _WR signals are routed to the main flash array). 3. Select the secondary flash to reside in 8032 code space at power-up (means that the 8032 _PSEN signal is routed to the secondary flash array). Figure 6., page 11 shows what the screen should look like after you've made the selections. 4. C lick OK. Now you will be asked if you want to use the Design Assistant, Extended Design Assistant, or Example Template. Choose Example Template. This is a predefined design that matches this application note and it runs on the DK3300 board. 5. C hoose the template for the DK3300 Kit when prompted. Note: At runtime, the 8032 can alter the initial settings of code and data space by writing to the VM Register.
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Figure 6. MCU Selection
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Pin Definitions You will see the Pin Definitions screen appear. 1. C lick through the pins and see how they are configured and how they relate to Figure 4. You will notice that you cannot change the definition of some pins because they have a fixed function. A comment about JTAG pins: This example uses 6-pin JTAG which is up to 30% faster than the default standard 4-pin JTAG. The two extra pins in the 6-pin JTAG configuration are _TSTAT and _TERR. 2. C lick "Next" to move on to the Design Assistant for memory mapping and logic equations. You will see the Page Register definition screen. Figure 7. Pin Definitions
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Mem ory Map Defining the memory map requires defining the address range of chip-selects for individual memory elements of the Turbo PSD (memory external to the 8032 core). Definition of the use of the Turbo PSD Page Register is also required. Four memory blocks (Main flash, Secondary flash, SRAM, and Control Registers) external to the 8032 core are available and are individually selected segment-by-segment when 8032 addresses are presented to the Decode PLD (DPLD). Each of these memory segments has its own chip-select name (fs3, csboot1, rs0, csiop, and so forth). Equations for these chip-selects, and for any external chip-selects, must be specified using PSDsoft Express. For this example, chip-selects are defined to match the memory map of Figure 5. Page Register Since eight memory pages (or banks) are needed as shown in Figure 5, three paging bits (23 = 8) are specified as shown in Figure 8. Paging bits may be used for other types of memory manipulation (such as memory swapping), but that will be discussed in other application notes. Click "Next" to move on to the Chip Select Definition Screen. Figure 8. Page Register Definition
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Chip-Select Equations Now you will see the Chip-Select definition screen. 1. C lick the chip-select signal rs0 for the 8-Kbyte xdata SRAM 2. Make sure that its definition matches the memory map in Figure 5. N ote: No page number is specified for rs0 since the SRAM is common to all pages (page independent). Additional signal qualifiers (8032 control signals _rd, _wr, _psen, and ale) are NOT needed for internal PSD chip-selects as this is taken care of in silicon. The SRAM always defaults to 8032 data space. At any time, you may click the "View" button to see how you are doing, and a summary will appear. 3. C lick on the chip-select csiop (Chip Select I/O Port). This is a band of 256 xdata registers used to control Turbo PSD Ports A, B, C, D, the Page Register, power management, and other functions. 40 of the 256 registers are used (see the complete Turbo PSD datasheet for register definitions and their address offset from the csiop base address). There is no need to specify additional signal qualifiers for csiop, and it is not allowed to place csiop on a particular memory page. 4. C lick on fs0. fs0 .. fs7, which are chip-selects for the eight 32-Kbyte segments of Turbo PSD Main flash (see Figure 9). N ote: The page number is 0 for fs0, and the address range is 8000 - FFFF as shown in memory map of Figure 5. Figure 9. Chip-Select Definition for 8K byte SRAM
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5. C lick on remaining chip-selects for main flash N ote: No additional qualifiers are needed for the page number assignments. 6. C lick on csboot0. csboot0 .. csboot3, which are chip-selects for the four 8-Kbyte segments of Turbo PSD secondary flash memory (see Figure 10). 7. C heck the address assignments for each of these chip-selects. N ote: There are no page numbers assigned; the secondary flash is common to all pages. 8. C lick on psel0. This address range specifies when Port A pins will behave like a data bus repeater in Peripheral I/O Mode to drive the LCD module. Port A pins were earlier specified a "Peripheral I/O Mode" which acts like a `245 bus transceiver chip connecting the 8032 data bus to external peripherals over a given address range specified by the label psel0 or psel1. The direction of this transceiver function is controlled automatically in silicon by the 8032 _rd and _wr signals (see the full PSD datasheet for details). All we have to do is click on psel0 and enter the address range 6100 to 61FF to enable this feature for that address range as shown in Figure 5, with no Page Number assignment. psel1 is not needed because the Peripheral I/O feature is active for the logical OR of psel0 or psel1. 9. C lick on LCD_e. This is an external chip-select for the LCD module. Since this is an external chipselect, we must include signal qualifiers _rd and _wr. In this design, LCD_e is true (active-high) only when the 8032 presents an address in the range of 6100 to 61FF AND when either 8032 control signal _rd is true, OR when 8032 control signal _wr is true. To create this logic, information is entered as shown in Figure 11., page 16. Since both signals _rd and _wr are active-low, the logical NOT operator (!) is used when they are specified as qualifiers. N ote: Signal qualifiers may be added by setting the cursor where you want the signal name to go, then just double-clicking on the signal name in the list of eligible qualifiers. 10. C lick "Next" to move on to Logic Definitions. Figure 10. Chip-Select Definition for Flash Memory Segments
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Figure 11. External Chip-Select Definition for LCD Module
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I/O Logic Equations Defined here are equations for PLD outputs for the LCD interface signals. The Design Assistant (DA) will create HDL logic statements using the ABEL language in the background after you enter logic in this pointand-click design entry environment. The DA will also create all the declaration statements in ABEL. This saves much typing and reduces the chance of error. For more complicated logic PSDsoft allows you to edit the ABEL statements directly. 1. C lick on "LCD_rw" as shown in Figure 12. N ote: The internal signal a0 is assigned to drive the output signal "LCD_rw". Although this was a very simple logic equation, AND, OR, XOR, NOT, and other logic operators are also available for general purpose logic. 2. C lick through the remaining signal names and observe the logic assigned. N ote: There is no logic equation assigned to term_count because that assignment will be made by editing the ABEL file directly. 3. C lick "Next" to move on to User-Defined Node Equations. Figure 12. Logic Equation for Signal LCD_rw
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User-Defined Node Equations Here you will see how internal logic nodes are created. In this example, there are four registers (or nodes) to hold the initial count of the 4-bit down-counter, and four additional registers to create the actual 4-bit down-counter (see Figure 13). These nodes were created by: 1. C licking the "Def Node.." button; 2. naming the node; and 3. selecting the type node (e.g., combinatorial, D-register, J-K register). In this example, all eight nodes are D-register type. When a register is created, you can specify its source of Input, Clock, Reset (see Figure 13). Once the nodes are created: 1. C lick though the signal names and look at the assignments. N otes: There are no definitions for inputs on any of the eight nodes. For the down_count nodes, the inputs are defined elsewhere (the ABEL file). For the init_count nodes, no logic input (or clock input) is specified because the 8032 will load the nodes directly by writing to the appropriate Output MacroCell register that resides the band of 256 registers of csiop. It may seem odd to divide the design entry this way (some point-and-click entry and some direct ABEL file editing), but many declaration statements are automatically created in the background by the point-and-click entry. You will see that when it is time to enter ABEL equations for the down-counter, there is very little typing involved. 2. C lick "Done." Now you will see the main PSDsoft flow diagram that will guide you through the remaining steps. N ote: You may view a summary report at this time by pulling down the "Report" selection in the main menu bar at the top of the screen, then selecting "Design Assistant Summary." Your report will match the one in APPENDIX A. Figure 13. 4-bit Down-Counter with Automatic Reload of Initial Count
8032 data bus (initial count) 4-bit auto-reloading down-counter D3 D2 D1 D0 4 nodes to hold initial count
8032 WRITEs to OMCs in control register space (csiop) to load initial count
AB3
AB2
AB1
AB0 term_count
ALE
AB7
AB6
AB5
AB4 1 PLD output defined for terminal count
OD 4 nodes to form counter
OC
OB
OA
AI09609
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Figure 14. D-Register Node
Set
PRE Input D Q
Clock CLR
Reset
AI09610
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Edit ABEL HDL Statements for PLD Design If your PSDsoft flow diagram does not include the block "Edit/Add Logic Statements" as shown in Figure 15: 1. Pull down the "Project" selection in the main menu bar at the top of the screen. 2. Select "Preference." 3. C lick the box that says "Enable ABEL Editing Capability." 4. C lick "OK." To see the "HDL Assistant" window: 1. C lick the "Edit/Add Logic Statements" box. 2. Browse this box to see ABEL logic and syntax examples that you can cut and paste into future designs. 3. C lose the HDL Assistant and you will see the ABEL HDL source file. All the declarations and logic equations generated from the Design Assistant are there, and should match APPENDIX B. Figure 15. Design Flow Diagram
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There are only two regions in the ABEL file in which you can type statements, otherwise the Design Assistant (DA) will overwrite what you have typed next time you get into the DA. The first safe region. For ABEL declarations and lies between the two statements: "// Begin user preserved declarations" and "// End user preserved declarations." The second safe region. For logic equations and lies between the two statements: "// Begin user preserved equations" and "// End user preserved equations." Scroll down to the declaration region in the ABEL file, which should look like the following: // Begin user preserved declarations (not affected by iterations of DA usage) =================== WSIPSD PROPERTY `DataBus_OMC D[7:4]:down_count[3:0] MCELLAB'; // This statement forces the alignment // of down_count bits [3..0] to the MCU data bus bit positions [7..4]. // If this WSIPSD PROPERTY statement was not present, then PSDsoft // would pick random MCU bit positions. The WSIPSD PROPERTY is needed // only if the MCU will read or write to MicroCells and only if a // particular MCU data bus position is required by the designer. WSIPSD PROPERTY `DataBus_OMC D[3:0]:init_count[3:0] MCELLAB'; // This statement forces the alignment // of init_count bits [3..0] to the MCU data bus bit positions [3..0]. DCOUNT = [down_count3..down_count0]; INIT = [init_count3..init_count0]; // 4-bit down counter // 4-bit initial count from MCU //INIT = [0,1,0,0];
// End user preserved declarations (not affected by iterations of DA usage) =================== Note: The WSIPSD PROPERTY statements are needed whenever you want to dictate the placement of certain MicroCells of the PLD. If you do not enter any WSIPSD PROPERTY declarations statement, then the PSDsoft "fitter" process will place the MicroCells in random order. This is not a problem for most designs. However, in this example we want to load an initial count for the down-counter from the 8032 data bus so we must make sure the output MicroCells holding the initial count are in the correct bit order and the correct position in the bank of eight output MicroCells. The property statement: WSIPSD PROPERTY `DataBus_OMC D[7:4]:down_count[3:0] MCELLAB' forces the order of the bits of the down-counter and places them on the upper half of the 8032 data bus. The property statement: WSIPSD PROPERTY `DataBus_OMC D[3:0]:init_count[3:0] MCELLAB' forces the order of the bits of the initial count and places them on the lower half of the 8032 data bus. When the 8032 writes to the OMCAB register at address csiop+0x20, the lower four bits of the byte will get loaded into the initial count. There is also a OMCAB mask register at csiop+0x22 that is used to prevent the 8032 from disturbing the other bits in the OMCAB register while writing. If the PROPERTY statements above ended with MCELLBC instead of MCELLAB, then the other bank of eight output MicroCells would be used for the counter. See the complete PSD datasheet and PSDsoft Express User's Guide for more details.
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The next declaration statements DCOUNT and INIT create a shorthand notation for use in the logic equations. Scroll down in the ABEL file to the logic equations until you see: // Begin user preserved equations (not affected by iterations of DA usage) =================== term_count = (DCOUNT == 0); // term_count true when count reaches zero // automatically reload counter with // value after a count of zero is reached else DCOUNT := DCOUNT - 1; // specify down count action
// End user preserved equations (not affected by iterations of DA usage)
when term_count then DCOUNT := INIT; initial
====================== These three statements define the down-counter and the PLD output that appears on pin PB0 (term_count). Note: Very little typing is needed to implement logic designs. The same approach is used to create state machines, shifters, and so forth. Close the ABEL file and you will see the PSDsoft flow diagram again.
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Additional PSD Configuration Click the box "Additional PSD Configuration." This is where you can choose to set the security bit to prevent a device programmer from examining or copying the contents of the Turbo PSD. The only way to defeat the security bit is to erase the entire Turbo PSD, then it can be used again as a blank part. Note: You may also click through the other sheets on this screen to set the JTAG USERCODE value and set sector protection on individual PSD Non-Volatile memory segments. (Just click "OK" for now.) C Code Generation All the projects are now available as zipped files on-line (see Figure 16). Please visit ST at www.st.com/ psd, then look for "Software Downloads." Figure 16. Coded Example Generation
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Fitting Design Click the next highlighted box in the design flow, "Fit Design to Silicon." PSDsoft will compile all the configuration selections and present a report (also available in APPENDIX C). The fitter report documents how pins are configured and how the programmable logic is allocated. It also shows how many programmable logic product terms are used, which is needed to estimate power consumption. Merging 8032 Firmware with PSD Configuration Now that all Turbo PSD pins and configuration settings have been defined, PSDsoft Express will create a single object file (*.obj) that is a composite of the 8032 firmware (*.hex) and the Turbo PSD configuration. FlashLINK/R-LINK or third party programmer tools can use this object file to program a Turbo PSD device. PSDsoft Express will create DK3300_1.obj for this design example. During this merging process, PSDsoft Express will input firmware files from the 8032 compiler/linker in Srecord or Intel HEX format. It will map the content of these files into the physical memory segments of the Turbo PSD according to the choices that were made in the `Chip Select Equations' screen. This mapping process translates the absolute system addresses inside 8032 firmware files into physical internal Turbo PSD addresses that are used by a programmer device to program the Turbo PSD. This address translation process is transparent. All you need to do is type (or browse) the file name that was generated from the 8032 linker into the appropriate boxes and PSDsoft Express does the rest. You can specify a single file name for more than one Turbo PSD chip-select, or a different file name for each Turbo PSD chipselect. It depends on how the 8032 linker has created the firmware file(s). For each Turbo PSD chip-select in which you have specified a firmware file name, PSDsoft Express will extract firmware from that file only between the specified start and stop addresses, and ignore firmware outside of the start and stop addresses. Click on "Merge MCU Firmware" in the main flow diagram. You will see an information window pop up to remind you to be sure you have configured the firmware compiler and linker to support a paged memory mapping scheme. Select "OK" and you will see the screen shown in Figure 17., page 25. Step 1. In the left column are Turbo PSD memory segment chip-selects (e.g., FS0, FS1). The next column shows the logic equations for selection of each Turbo PSD memory segment. These equations reflect the choices that were made while defining Turbo PSD internal chip-select equations in an earlier step. In the middle of the screen are hexadecimal start and stop addresses that PSDsoft Express has filled in, based on the chip-select equations. On the right are fields to enter (browse) the 8032 firmware files. To select a firmware file: 1. Select "Intel Hex Record" for 'Record Type' as shown in Figure 17. 2. Slide the bar on the right side all the way down to the bottom until you see CSBOOT0. 3. U se the 'Browse' button and select the firmware file for CSBOOT0, PSDexpress\Examples\DK3300_1.hex. This is a small example program that exercises the PWM and ADC channels of the Turbo PSD on the DK3300 board, and this code fits completely within the 8Kbyte flash segment CSBOOT0. This specification places firmware in secondary Turbo PSD flash memory segment csboot0. PSDsoft Express will extract any firmware that lies inside the file DK3300_1.hex between MCU addresses 0000 and 1FFF and place it in Turbo PSD memory segment csboot0. Step 2. Click OK to generate the composite object file, DK3300_1.obj.
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Figure 17. Merging the Example Firmware
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JTAG Programming Selection of The Programming Tool (either FlashLINK OR R-LINK) is done in the HW setup window. 1. C lick the "STMicroelectronics JTAG/ISP" box to program the Turbo PSD. You will be asked how many JTAG devices are on the target circuit board. 2. C hoose "Only One" to see the screen shown in Figure 18. This window enables you to perform JTAG-ISP operations and also offers a loop back test for your FlashLINK/R-LINK cable. If this is your first use, test your FlashLINK or R-LINK cable and PC parallel or USB port by clicking the 'HW Setup' button, then click 'LoopTest' button and follow the directions. To define your JTAG-ISP environment: 1. C onnect the JTAG ribbon cable to the target system 2. Power-up the target system 3. C lick 'Execute' on the JTAG screen. The Log window at the bottom of the JTAG screen shows the progress. Programming should just take a few seconds. N ote: For this example project, PSDsoft Express should have filled in the folder and filename of the object file to program, the PSD device, and the JTAG-ISP operation, as shown in Figure 18. For this design example, we have chosen to use the six JTAG-ISP pins so the screen should indicates a 6-pin JTAG is being used. There are optional choices available when the "Properties.." button is clicked. One choice includes setting the state of all pins on port A, B, C, or D during JTAG-ISP operations (make them inputs or outputs). The default state of these pins is "input", which is fine for this design example. The other choice allows you to specify a USERCODE value to compare before any JTAG-ISP operation starts. This is typically used in a manufacturing environment (see on-screen description for details). 4. After JTAG-ISP operations are complete, click on the 'Save' button so that you can save the JTAG setup for this programming session to a file for later use. N ote: You may restore the setup of a different previous session by clicking the 'Browse..' button. Figure 18. Programming with FlashLINK/R-LINK JTAG Cable
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WATCH IT RUN ON DK3300
After JTAG programming completes in just a few seconds, you should see a message appear on the LCD: "PW M to ADC DEMO" You will see the HEX value of the ADC conversion sweep up and down between 0x000 and 0x3FF as the PW M pulse width changes. If you do not see the ADC value change, make sure there are two jumpers installed on the DK3300 board. On JP13, install one jumper across the opposite row of pins next to the word "PWM0," and the other jumper, JP14, install one jumper across the opposite row of pins next to the word "ADC7." Remove the jumper next the word "ADC7" and watch the ADC value on the LCD drop to 000 hex.
USING uVISION2 AND ULink JTAG DEBUGGER FROM KEIL SOFTWARE, INC.
This next section will briefly highlight the features of the Keil uVision2 and ULink JTAG debugger. Keil's PK51 Professional Developers Kit Version 7.08a was used for this example. Please refer to Keil documentation for more detail. Loading a Keil uVision2 Project The file, "DK3300_dsn_1.ZIP" is available, and contains all of the source and project files needed to build this design in Keil's uVision2. To get this file: 1. C lick on the "Generate C Code" box on the PSDsoft flow diagram. 2. C hose the "Coded Examples" tab 3. C hoose the selection for the DK3300 board. 4. Specify the folder in which you want the ZIP file written. 5. C lick "Generate." The ZIP file contains two folders, "DK3300_c" and "DK3300_p." DK3300_c has all the Keil 8032 files, DK3300_p has the PSDsoft Express project files for this application note. To invoke Keil uVision2: 1. Pull down the "Project" menu 2. Select "Open Project." 3. Open the uVision2 project that you just got from the ZIP file at ..\Dk3300_c\DK3300_1.Uv2. Everything should be ready to go. Building the Project and Programming the Turbo PSD You can build the project for this application note and create a new Intel HEX-80 file, "DK3300_1.hex:" 1. Invoke PSDsoft Express and open the project DK3300_1. 2. Go to the "Merge MCU Firmware" section and use the scroll bar at the right hand side and scroll down until you see CSBOOT0. 3. Put your cursor under the File Name and use the "Browse.." button to select the new HEX file from the folder where your DK3300_1.hex was created. 4. C lick the "OK" button. "DK3300_1.OBJ," which contains your firmware as well as the Turbo PSD's configurations, is created in your PSDsoft Express Project folder(..\DK3300_p). You can now program the DK3300 board with FlashLINK/R-LINK cable just as before. The LCD should display the PWM to ADC demo information.
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Running Keil's ULink - USB to JTAG Debugger The Turbo PSD features a built-in JTAG debugger which can provide ICE (In-Circuit Emulator) like functions. Currently this debugger is only supported by Keil, it makes use of a USB to JTAG adapter called ULink. Our current PSD system architecture already makes use of this JTAG port to perform programming of the Flash and PLD using the FlashLINK/R-LINK cable. This same JTAG port can also be used for debugging the hardware in the Turbo Core. Note: Please unplug the FlashLINK/R-LINK cable, then plug-in the ULink cable to the JTAG connector. In order to use the JTAG debugger, the Keil environment must be configured first: 1. Start the Keil uVision tool as normal. 2. C lick the "Options for Target" icon in the tools bar, as shown in Figure 19. 3. In the Options for Target system dialog menu, select the "Debug" option. Please select Use "ST uPSD ULink Driver" as shown in Figure 20., page 29. 4. C lick the "Settings" button next to the ST-uPSD ULink Driver, you should have the target setup as shown in Figure 20. If you are using Keil's software version 7.07A or earlier, please clear all the boxes under "Cache Options" and "Misc. Options." However, if version 7.07B or later is used, you should have these options enabled to improve the speed. N ote: The Turbo PSD programming functions can also be setup in this menu (see Figure 21., page 29). Under the PSDsoft Project Files, make sure to specify the correct path which points to your PSDsoft Project's *.ini file so that Keil software can automatically merge the *.hex file with your Turbo PSD's configurations setup to generate the final *.obj file. The *.obj file will be used to program your Turbo PSD devce when you click the "Load" button in the tool's menu (see Figure 22). Figure 19. Setting up ULink JTAG Debugger
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Figure 20. Setting up ULink Target Options
Figure 21. Setting up the ULink Target Options
Figure 22. Tool Menu `Load' Button
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In this project, DK3300_1.Uv2 has USB-JTAG Debugger already selected for the debugger tool; you just need to connected the ULink cable to your PC's USB port, then click the Debug icon in the toolbar to start the debugger. The screen should look like Figure 23 when the debugger is running successfully. Now you should be able to run your code and set break points, single-step, view 8032 internal registers and SFRs, view blocks of memory, etc. as you normally would using the Keil uVision ULink. Note: A maximum of 4 break points can be set at any point in time. Figure 23. Keil's ULink JTAG Debugger After Successfully Invoked
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CONCLUSION
Congratulations! You have seen the majority of steps to implement a Turbo PSD design on the DK3300 board. This design guide showed the basic steps to pre-configure the memories with PSDsoft, compile, program in Flash and debug with the Keil debugger suite. You still need to review the relevant documentation in this CD-ROM about the PSD Turbo architecture and the additional documentation from Keil Software Inc. You may also use the new debugger environment from Raisonance, S.A, which comes with its own C Compiler and high-level language debugger (RIDE). This tool chain is provided on a separate CD-ROM.
REVISION HISTORY
Table 1. Document Revision History
Date 04-May-2004 05-Jan-05 Version 1.0 2.0 First Issue Change document title Revision Details
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APPENDIX A. PSDsoft EXPRESS PROJECT SUMMARY FILE, DK3300_1.SUM
* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** PSDsoft Express Version 8.00 Summary of Design Assistant * * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** PROJECT : dk3300_1 DATE : 09/17/2003 DEVICE : uPSD3334D TIME : 09:22:47 MCU/DSP : uPSD33XX * * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** Initial setting for Program and Data Space: =========================================== Main PSD flash memory will reside in this space at power-up: Data Space Only Secondary PSD flash memory will reside in this space at power-up: Program Space Only Pin Definitions: ================ Pin Name -----------pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 tdo tdi pc4 pc3 tck tms ale _psen _rd _wr p4.0 p3.1 p3.0 p1.7 a11 a10 a9 a8 ad7 ad6 ad5 ad4 ad3 ad2 Signal Name ------------------------pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 LCD_e LCD_a1 LCD_a0 term_count tdo tdi _terr tstat tck tms ale _psen _rd _wr PWM0 UART0_TxD UART0_RxD ADC_Ch7 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 Pin Type -----------Peripheral I/O mode Peripheral I/O mode Peripheral I/O mode Peripheral I/O mode Peripheral I/O mode Peripheral I/O mode Peripheral I/O mode Peripheral I/O mode External chip select - Active Hi Combinatorial Combinatorial Combinatorial Dedicated JTAG - TDO Dedicated JTAG - TDI Dedicated JTAG - /TERR Dedicated JTAG - TSTAT Dedicated JTAG - TCK Dedicated JTAG - TMS ALE output Bus control output Bus control output Bus control output GP I/O mode UART0 TxD UART0 RxD ADC channel7 input Address line Address line Address line Address line Data/Address line Data/Address line Data/Address line Data/Address line Data/Address line Data/Address line
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ad1 ad0 debug Xtal1 Xtal2 _Reset_In Vref a1 a0 JTAG_debug_pin Xtal1 Xtal2 _Reset_In VREF Data/Address line Data/Address line JTAG debug pin Xtal1 Xtal2 Reset In VREF input
User defined nodes: =================== Node Name -----------init_count0 init_count1 init_count2 init_count3 down_count0 down_count1 down_count2 down_count3 Node Type -----------D-type register D-type register D-type register D-type register D-type register D-type register D-type register D-type register
Page Register settings: ======================= pgr0 pgr1 pgr2 pgr3 pgr4 pgr5 pgr6 pgr7 is is is is is is is is used for paging used for paging used for paging not used not used not used not used not used
Equations: ========== rs0 = ((address >= ^h4000) & (address <= ^h5FFF)); csiop = ((address >= ^h6000) & (address <= ^h60FF)); fs0 = ((page == 0) & (address >= ^h8000) & (address <= ^hFFFF)); fs1 = ((page == 1) & (address >= ^h8000) & (address <= ^hFFFF)); fs2 = ((page == 2) & (address >= ^h8000) & (address <= ^hFFFF)); fs3 = ((page == 3) & (address >= ^h8000) & (address <= ^hFFFF)); fs4 = ((page == 4) & (address >= ^h8000) & (address <= ^hFFFF)); fs5 = ((page == 5) & (address >= ^h8000) & (address <= ^hFFFF)); fs6 = ((page == 6) & (address >= ^h8000) & (address <= ^hFFFF)); fs7 = ((page == 7) & (address >= ^h8000) & (address <= ^hFFFF)); csboot0 = ((address >= ^h0000) & (address <= ^h1FFF)); csboot1 = ((address >= ^h2000) & (address <= ^h3FFF)); psel0 = ((address >= ^h6100) & (address <= ^h61FF) & (_psen)); LCD_e = ((address >= ^h6100) & (address <= ^h61FF) & (!_wr)) # ((address >= ^h6100) & (address <= ^h61FF) & (!_rd)); LCD_a1 = a1; LCD_a1.oe = Vcc; LCD_a0 = a0; LCD_a0.oe = Vcc; init_count0.ck = Gnd; init_count0.re = !_reset;
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init_count0.pr init_count1.ck init_count1.re init_count1.pr init_count2.ck init_count2.re init_count2.pr init_count3.ck init_count3.re init_count3.pr down_count0.ck down_count0.re down_count0.pr down_count1.ck down_count1.re down_count1.pr down_count2.ck down_count2.re down_count2.pr down_count3.ck down_count3.re down_count3.pr = = = = = = = = = = = = = = = = = = = = = = Gnd; Gnd; !_reset; Gnd; Gnd; !_reset; Gnd; Gnd; !_reset; Gnd; ale; !_reset; Gnd; ale; !_reset; Gnd; ale; !_reset; Gnd; ale; !_reset; Gnd;
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APPENDIX B. PSDsoft EXPRESS ABEL HDL DESIGN FILE DK3300_1.ABL
module dk3300_1 pa7 PIN 21; "Reserved for Peripheral pa6 PIN 22; "Reserved for Peripheral pa5 PIN 24; "Reserved for Peripheral pa4 PIN 26; "Reserved for Peripheral pa3 PIN 28; "Reserved for Peripheral pa2 PIN 32; "Reserved for Peripheral pa1 PIN 34; "Reserved for Peripheral pa0 PIN 35; "Reserved for Peripheral LCD_e PIN 66; LCD_a1 PIN 67; LCD_a0 PIN 71; term_count PIN 80; tdo PIN 6; "TDO tdi PIN 7; "TDI _terr PIN 9; "/TERR tstat PIN 14; "TSTAT tck PIN 16; "TCK tms PIN 20; "TMS ale PIN 4; "ALE output _psen PIN 63; _rd PIN 65; _wr PIN 62; PWM0 PIN 33; "GP I/O UART0_TxD PIN 77; "UART0 TxD UART0_RxD PIN 75; "UART0 RxD ADC_Ch7 PIN 64; "ADC channel7 input a11 PIN 57; "Address line a10 PIN 55; "Address line a9 PIN 53; "Address line a8 PIN 51; "Address line a7 PIN 47; "Data/address bus line a6 PIN 45; "Data/address bus line a5 PIN 43; "Data/address bus line a4 PIN 41; "Data/address bus line a3 PIN 39; "Data/address bus line a2 PIN 38; "Data/address bus line a1 PIN 37; "Data/address bus line a0 PIN 36; "Data/address bus line JTAG_debug_pin PIN 8; "JTAG debug pin Xtal1 PIN 48; "Xtal1 Xtal2 PIN 49; "Xtal2 _Reset_In PIN 68; VREF PIN 70; "VREF input psel0 node; rs0 node; csiop node; fs0 node; fs1 node; fs2 node; fs3 node; fs4 node; fs5 node; fs6 node; fs7 node; csboot0 node; csboot1 node; _reset node 543; I/O I/O I/O I/O I/O I/O I/O I/O mode mode mode mode mode mode mode mode
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a12 node 512; a13 node 513; a14 node 514; a15 node 515; pgr2..pgr0 node; init_count0 NODE init_count1 NODE init_count2 NODE init_count3 NODE down_count0 NODE down_count1 NODE down_count2 NODE down_count3 NODE
istype istype istype istype istype istype istype istype
`reg_D'; `reg_D'; `reg_D'; `reg_D'; `reg_D'; `reg_D'; `reg_D'; `reg_D';
X = .x.; address = [a15..a0]; page = [pgr2..pgr0]; Vcc = 1; Gnd = 0; // Begin user preserved declarations (not affected by iterations of DA usage) =================== WSIPSD PROPERTY `DataBus_OMC D[7:4]:down_count[3:0] MCELLAB'; // This statement forces the alignment // of down_count bits [3..0] to the MCU data bus bit positions [7..4]. // If this WSIPSD PROPERTY statement was not present, then PSDsoft // would pick random MCU bit positions. The WSIPSD PROPERTY is needed // only if the MCU will read or write to MicroCells and only if a // particular MCU data bus position is required by the designer. WSIPSD PROPERTY `DataBus_OMC D[3:0]:init_count[3:0] MCELLAB'; // This statement forces the alignment // of init_count bits [3..0] to the MCU data bus bit positions [3..0]. DCOUNT = [down_count3..down_count0]; // 4-bit down counter INIT = [init_count3..init_count0]; // 4-bit initial count from MCU // INIT = [0,1,0,0]; // End user preserved declarations (not affected by iterations of DA usage) =================== equations rs0 = csiop fs0 = fs1 = fs2 = fs3 = fs4 = fs5 = fs6 = fs7 = ((address >= ^h4000) & (address <= ^h5FFF)); = ((address >= ^h6000) & (address <= ^h60FF)); ((page == 0) & (address >= ^h8000) & (address <= ((page == 1) & (address >= ^h8000) & (address <= ((page == 2) & (address >= ^h8000) & (address <= ((page == 3) & (address >= ^h8000) & (address <= ((page == 4) & (address >= ^h8000) & (address <= ((page == 5) & (address >= ^h8000) & (address <= ((page == 6) & (address >= ^h8000) & (address <= ((page == 7) & (address >= ^h8000) & (address <=
^hFFFF)); ^hFFFF)); ^hFFFF)); ^hFFFF)); ^hFFFF)); ^hFFFF)); ^hFFFF)); ^hFFFF));
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AN1943 - APPLICATION NOTE
csboot0 = ((address >= ^h0000) & (address <= ^h1FFF)); csboot1 = ((address >= ^h2000) & (address <= ^h3FFF)); psel0 = ((address >= ^h6100) & (address <= ^h61FF) & (_psen)); LCD_e = ((address >= ^h6100) & (address <= ^h61FF) & (!_wr)) # ((address >= ^h6100) & (address <= ^h61FF) & (!_rd)); LCD_a1 = a1; LCD_a1.oe = Vcc; LCD_a0 = a0; LCD_a0.oe = Vcc; init_count0.ck = Gnd; init_count0.re = !_reset; init_count0.pr = Gnd; init_count1.ck = Gnd; init_count1.re = !_reset; init_count1.pr = Gnd; init_count2.ck = Gnd; init_count2.re = !_reset; init_count2.pr = Gnd; init_count3.ck = Gnd; init_count3.re = !_reset; init_count3.pr = Gnd; down_count0.ck = ale; down_count0.re = !_reset; down_count0.pr = Gnd; down_count1.ck = ale; down_count1.re = !_reset; down_count1.pr = Gnd; down_count2.ck = ale; down_count2.re = !_reset; down_count2.pr = Gnd; down_count3.ck = ale; down_count3.re = !_reset; down_count3.pr = Gnd; // Begin user preserved equations (not affected by iterations of DA usage) =================== term_count = (DCOUNT == 0); // term_count true when count reaches zero
when term_count then DCOUNT := INIT; // automatically reload counter with initial // value after a count of zero is reached else DCOUNT := DCOUNT - 1; // specify down count action
// End user preserved equations (not affected by iterations of DA usage) =================== end dk3300_1
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AN1943 - APPLICATION NOTE
APPENDIX C. PSDsoft EXPRESS FITTER REPORT FILE DK3300_1.FRP
* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** PSDsoft Express Version 8.00 Output of PSD Fitter * * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** PROJECT : dk3300_1 DATE : 09/17/2003 DEVICE : uPSD3334D TIME : 13:56:57 FIT OPTION : Keep Current DESCRIPTION: Example design for uPSD3334D in Application Note AN1763. Simple memory map with 16K secondary flash in code space, and 256K main flash paged in data space. Down-Counter built in PLD. Runs on DK3300 board. * * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** ==== Pin Layout for U (80-Pin TQFP) Package Type ==== ----------------------------| | |1 ] pd2 adio4 [41| Address A4/Data D4,a4 |2 ] p3_3 p3_5 [42| |3 ] pd1 adio5 [43| Address A5/Data D5,a5 ale |4 ] pd0 p3_6 [44| |5 ] pc7 adio6 [45| Address A6/Data D6,a6 tdo, TDO |6 ] pc6/TDO p3_7 [46| tdi, TDI |7 ] pc5/TDI adio7 [47| Address A7/Data D7,a7 JTAG_debug_pin |8 ] debug Xtal1 [48| Xtal1 _terr, TERR |9 ] pc4/TERR Xtal2 [49| Xtal2 |10] 3.3V VCC 5.0V VCC [50| |11] N/C adio8 [51| Address A8, a8 |12] 5.0V VCC p1_0 [52| |13] GND adio9 [53| Address A9, a9 tstat, TSTAT |14] pc3/TSTAT p1_1 [54| |15] pc2 adio10 [55| Address A10, a10 tck, TCK |16] pc1/TCK p1_2 [56| |17] N/C adio11 [57| Address A11, a11 |18] p4_7 p1_3 [58| |19] p4_6 p1_4 [59| tms, TMS |20] pc0/TMS p1_5 [60| pa7, Peripheral I/O Mode |21] pa7 p1_6 [61| pa6, Peripheral I/O Mode |22] pa6 cntl0 [62| _wr |23] p4_5 cntl2 [63| _psen pa5, Peripheral I/O Mode |24] pa5 p1_7 [64| ADC_Ch7 |25] p4_4 cntl1 [65| _rd pa4, Peripheral I/O Mode |26] pa4 pb7 [66| LCD_e |27] p4_3 pb6 [67| LCD_a1 pa3, Peripheral I/O Mode |28] pa3 Reset_In [68| _Reset_In |29] GND GND [69| |30] p4_2 Vref [70| VREF |31] p4_1 pb5 [71| LCD_a0 pa2, Peripheral I/O Mode |32] pa2 3.3V VCC [72| PWM0 |33] p4_0 pb4 [73| pa1, Peripheral I/O Mode |34] pa1 pb3 [74| pa0, Peripheral I/O Mode |35] pa0 p3_0 [75| UART0_RxD a0, Address A0/Data D0 |36] adio0 pb2 [76| a1, Address A1/Data D1 |37] adio1 p3_1 [77| UART0_TxD a2, Address A2/Data D2 |38] adio2 pb1 [78| a3, Address A3/Data D3 |39] adio3 p3_2 [79| |40] p3_4 pb0 [80| term_count | | -----------------------------
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AN1943 - APPLICATION NOTE
==== Global Configuration ==== Data Bus : 8-Bit Address/Data Mode : Multiplexed ALE/AS Signal : Active High Control Signals : /WR, /RD, /PSEN Main PSD flash memory will reside in this space at power-up : Data space Secondary PSD flash memory will reside in this space at power-up : Program space Enable Chip-Select Input(/CSI) : OFF Standby Voltage Input (PC2) : OFF Standby-on Indicator (PC4) : OFF RDY/Busy function (PC3) : OFF Load Micro-Cell on : edge Security Protection : OFF ==== DataBus_IMC access information ==== CSIOP Location Address Offset Register Name Signals -------------------------------------------------------===== Resource Usage Summary ===== Total Product Terms Used: 61
Device Resources used / total -----------------------------------------------Port A: (pins 35 34 32 28 26 24 22 21) I/O Pins : 8 /8 GP I/O or Address Out : 0 Peripheral I/O : 8 Logic Inputs : 0 Address Latch Inputs : 0 PT Dependent Latch Inputs : 0 PT Dependent Register Inputs : 0 Combinatorial Outputs : 0 Registered Outputs : 0 Other Information Microcells : 8 /8 Micro-Cells AB : Buried Microcells : 8 Output Microcells : 0 Product Terms : 15 / 24 Control Product Terms : 24 / 34 Port B: (pins 80 78 76 74 73 71 I/O Pins : GP I/O or Address Out Logic Inputs Address Latch Inputs PT Dependent Latch Inputs PT Dependent Register Inputs Combinatorial Outputs Registered Outputs Other Information Microcells Micro-Cells AB : Buried Microcells Output Microcells 67 66) 4 : 0 : 0 : 0 : 0 : 0 : 4 : 0 : : : 8 4 0 / 8
/
8
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AN1943 - APPLICATION NOTE
Micro-Cells BC : Buried Microcells Output Microcells Product Terms Control Product Terms Port C: (pins 20 16 15 14 9 7 6 I/O Pins : GP I/O or Address Out Logic Inputs Address Latch Inputs PT Dependent Latch Inputs PT Dependent Register Inputs JTAG signals Standby Voltage Input Rdy/Bsy signal Standby On Indicator Combinatorial Outputs Registered Outputs Other Information Microcells Micro-Cells BC : Buried Microcells Output Microcells Product Terms Control Product Terms Port D: (pins 4 3 1) I/O Pins : GP I/O or Address Out Logic Inputs Chip-Select Input Clock Input Control Signal Input Fast Decoding Outputs Other Information Product Terms Control Product Terms
: : : : 5) : : : : : : : : : : : : : : : :
0 4 10 16 6 0 0 0 0 0 6 0 0 0 0 0 4 4 0 5 0 1 0 0 0 0 1 0 0 0
/ / /
28 34 8
/
8
/ / /
32 34 3
: : : : : : : :
/ /
3 3
==== OMC Resource Assignment ==== Resources PT User Used Allocation Name --------------------------------------------------------Micro-Cell AB : Micro-Cells 0 init_count0 => Register Micro-Cells 1 init_count1 => Register Micro-Cells 2 init_count2 => Register Micro-Cells 3 init_count3 => Register Micro-Cells 4 down_count0 => Register Micro-Cells 5 down_count1 => Register Micro-Cells 6 down_count2 => Register Micro-Cells 7 down_count3 => Register Micro-Cell BC Micro-Cells Micro-Cells Micro-Cells Micro-Cells : 0 5 6 7 term_count (mcellbc0) => Combinatorial LCD_a0 (mcellbc5) => Combinatorial LCD_a1 (mcellbc6) => Combinatorial LCD_e (mcellbc7) => Combinatorial
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AN1943 - APPLICATION NOTE
External Chip Select : ========= Equations ========= DPLD EQUATIONS : ======================= fs0 = !pdn & !pgr2 & !pgr1 & !pgr0 & a15; fs1 = !pdn & !pgr2 & !pgr1 & pgr0 & a15; fs2 = !pdn & !pgr2 & pgr1 & !pgr0 & a15; fs3 = !pdn & !pgr2 & pgr1 & pgr0 & a15; fs4 = !pdn & pgr2 & !pgr1 & !pgr0 & a15; fs5 = !pdn & pgr2 & !pgr1 & pgr0 & a15; fs6 = !pdn & pgr2 & pgr1 & !pgr0 & a15; fs7 = !pdn & pgr2 & pgr1 & pgr0 & a15; csboot0 = !pdn & !a15 & !a14 & !a13; csboot1 = !pdn & !a15 & !a14 & a13; csiop = !pdn & !a15 & a14 & a13 & !a12 & !a11 & !a10 & !a9 & !a8; rs0 = !pdn & !a15 & a14 & !a13; psel0 = !pdn & _psen & !a15 & a14 & a13 & !a12 & !a11 & !a10 & !a9 & a8; PORTA EQUATIONS : ======================= init_count0.D := 0; init_count0.PR = 0; init_count0.RE = !_reset; init_count0.C = 0; init_count1.D := 0; init_count1.PR = 0; init_count1.RE = !_reset; init_count1.C = 0; init_count2.D := 0; init_count2.PR = 0; init_count2.RE = !_reset; init_count2.C = 0; init_count3.D := 0; init_count3.PR = 0; init_count3.RE = !_reset; init_count3.C = 0; down_count0.D := (!down_count0.Q & !term_count.PIN) # (init_count0 & term_count.PIN); down_count0.PR = 0; down_count0.RE = !_reset;
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AN1943 - APPLICATION NOTE
down_count0.C = ale; down_count1.D := (down_count1.Q & down_count0.Q & !term_count.PIN) # (!down_count1.Q & !down_count0.Q & !term_count.PIN) # (init_count1 & term_count.PIN); down_count1.PR = 0; down_count1.RE = !_reset; down_count1.C = ale; down_count2.T := (!down_count1.Q & !down_count0.Q & !term_count.PIN) # (!down_count2.Q & init_count2 & term_count.PIN) # (down_count2.Q & !init_count2 & term_count.PIN); down_count2.PR = 0; down_count2.RE = !_reset; down_count2.C = ale; down_count3.T := (!down_count3.Q & init_count3 & term_count.PIN) # (down_count3.Q & !init_count3 & term_count.PIN) # (!down_count2.Q & !down_count1.Q & !down_count0.Q & !term_count.PIN); down_count3.PR = 0; down_count3.RE = !_reset; down_count3.C = ale; PORTB EQUATIONS : ======================= term_count = !down_count3.Q & !down_count2.Q & !down_count1.Q & !down_count0.Q; term_count.OE = 1; term_count.LE = 1; LCD_a0 = a0; LCD_a0.OE = 1; LCD_a1 = a1; LCD_a1.OE = 1; LCD_e = (!_wr & !a15 & a14 & a13 & !a12 & !a11 & !a10 & !a9 & a8) # (!_rd & !a15 & a14 & a13 & !a12 & !a11 & !a10 & !a9 & a8); LCD_e.OE = 1; PORTC EQUATIONS : ======================= PORTD EQUATIONS : ======================= --End ---
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1 6 VCC
8 7 6 5 8 7 6 5
2
3
4
5
Figure 24. MCU
X2
VCC
JP6 R1 10K VCC
1 2 3 4 RC_RST CPU_JTAG 4 1 2 1 2 3 4
X2 40MHz R2 10K D
C17 20pf
C18 20pf
C13 104P
D
3 2 1
X1
X1
R12 FlashLINK
3
200
VCC OSC_OUT OE GND
40MHz
Clock
3.3V low active RESET
CPU_TMS CPU_TCK CPU_TSTA CPU_TERR CPU_TDI CPU_TDO JTAG_CTRL 3.3V_RST
VCC C5 104P
MCU
VCC D1 JEN U3 DK3300
X1 X2 RESET_IN
14 12 10 8 6 4 2 TERR GND GND RST TSTAT CNTL TRST TDO TCK TMS VCC TDI GND JEN
13 11 9 7 5 3 1
VCC
CPU_CLOCK
X1
48
D2 DEBUG R4 470
X2
49
C
C
3.3V_RST 68
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7
36 CPU_AD0 37 CPU_AD1 38 CPU_AD2 39 CPU_AD3 41 CPU_AD4 43 CPU_AD5 45 CPU_AD6 47 CPU_AD7
R7 470
8 DEBUG AD[0.. 11]
3.3V Reset
APPENDIX D. DK3300 SCHEMATICS
JP2
JTAG_CNTRL
1 2
CPU_DEBUG JTAG_CNTRL
P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11
51 CPU_AD8 53 CPU_AD9 55 CPU_AD10 57 CPU_AD11
FlashLINK JTAG for 3300 Programming/Debugging
JTAG (FlashLINK)
CPU_CMM
CPU_P3
CPU_I2C Control Bus
CPU_U1RXD CPU_U1TXD CPU_INT0 CPU_INT1 CPU_P3.4 CPU_P3.5 CPU_I2CSDA CPU_I2CSCL RXD/P3.0 TXD/P3.1 EXINT0/GATE0/P3.2 EXINT1/GATE1/P3.3 T0/P3.4 T1/P3.5 I2CSDA/P3.6 I2CSCL/P3.7 CTRL0/WR CTRL0/RD CTRL2/PSEN ALE(PD0) 62 CPU_WR 65 CPU_RD 63 CPU_PSEN 4 CPU_ALE
75 77 79 2 40 42 44 46
Reset
VCC D3 1N4148 RC_RST
2 3 RESET 3.3V_RST
JP8 B
3 2 1
B
PA[0.. 7]
CPU_ADC_IN
CPU_UART2
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
35 CPU_PA0 34 CPU_PA1 32 CPU_PA2 28 CPU_PA3 26 CPU_PA4 24 CPU_PA5 22 CPU_PA6 21 CPU_PA7
JP1
VREF PB[0.. 7]
CPU_ADC0 CPU_ADC1 CPU_U2RXD CPU_U2TXD CPU_ADC4 CPU_ADC5 CPU_ADC6 CPU_ADC7 ADC0/T2/P1.0 ADC1/T2x/P1.1 . ADC2/RXD2/P1.2 ADC3/TXD2/P1.3 ADC4/SPISCLK/P1.4 ADC5/SPIRXD/P1.5 ADC6/SPITXD/P1.6 ADC7/SPISEL/P1.7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 80 CPU_PB0 78 CPU_PB1 76 CPU_PB2 74 CPU_PB3 73 CPU_PB4 71 CPU_PB5 67 CPU_PB6 66 CPU_PB7
52 54 56 58 59 60 61 64
1
100H
4
1 2
3.3V L1
VREF
70
RESET SWITCH PUSH-BUTTON
C4 105P Reset Circuit
C8 104P VC1 C15 104P C11 103P
3.3V C9 104P C12 104P
CPU_PWM_OUT
CPU_SPI_BUS 3 CPU_PD1 1 CPU_PD2v CPU_JTAG
CPU_PWM0 CPU_PWM1 CPU_PWM2 CPU_PCA0CLK CPU_SPI_CLK CPU_SPI_RXD CPU_SPI_TXD CPU_SPI_SEL T2/TCM0/P4.0 T2x/TCM1/P4.1 TMS/PC0 RXD2/TCM2/P4.2 TCK/PC1 TXD2/PCA0/P4.3 VSTBY/PC2 SPISCLK/TCM3/P4.4 TSTAT/RDY/PC3 SPIRXD/TCM4/P4.5 TERR/V BATON/PC4 SPITXD/TCM5/P4.6 TDI/PC5 SPISEL/PCA1/P4.7 TDO/PC6 PC7 20 CPU_TMS 16 CPU_TCK 15 CPU_PC2 14 CPU_TSTA 9 CPU_TERR 7 CPU_TDI 6 CPU_TDO 5 CPU_PC7 VCC VCC VDD VDD GND GND GND N.C. N.C. PD1 PD2
33 31 30 27 25 23 19 18
A
3.3V 13 29 69 72 10 12 50 11 17 VC1
VC1 C14 104P C16 103P
3.3V
Title
A C7 103P C10 103P MCU
Size B Date: File: Number Revision 4-August-2003 Sheet 2 of 4 C:\Documents and Settings\bo kang.ST
5V
R8
3.3V
0 R16
AI09611
2 3
0 4 5
1
6
AN1943 - APPLICATION NOTE
43/46
8 7 6 5
D
1 2 3 4 S Q RESET F32K VCC HOLD
104pF U7
VCC VBAT VOUT TPCLR ECON IRQ SQW RST PFO1 PFO2 VSS F 3 2k 21 F32k 12 M41ST87_PFO1 7 M41ST87_PFO2 26 M41ST87_IRQ 8 M41ST87_SQW 19 RESET 25 M41ST87_VOUT 18 TPCLR 16 ECON 17 22 27 9 SDA SCL EX WDI RST INT1 RST INT2 PFI1 PFI2 TP1IN TP2IN 14
VCC W VSS
VCC 3 4 C D 6 5 CPU_SPI_CLK CPU_SPI_TXD
CON6
1 2
I2CSDA I2CSCL
C19 104P CON5 VCC U10
1 D C RESET VCC S W 5 3.3V 6 3.3V 20 24 VSS 7 GND Q 2 3 4 8 CPU_SPI_RXD 2 1 23 13 10 11
3.3V
CPU_SPI_TXD
AN1943 - APPLICATION NOTE
CPU_SPI_CLK
R21 10K M41ST87
C35 104P 48PE16
3.3V_RST
SPI_SEL
28
15
PA[0.. 7] 2
B R11
GND
JP0
VCC
RS R/W E GND
5V
U2
5V OP-A IP-A IP_A GND VCC OP-B IP-B IP_B 8 7 6 5
1
44/46
2 6 JP11 R22 4K7
5V 3.3V VCC 8 7 GND VCC
1
3
4
5
VCC
Figure 25. Peripheral
JP7 C33 0 3.3V or 5V
1 2
R15 10K U4 M95080W
R24 4K7
R28 0 R29
Battery Socket BATTERY
1 2
CPU_PC2 M41ST87_VOUT
2 1
CPU_SPI_SEL SPI_SEL CPU_SPI_RXD
D
JP10
CPU_I2CSCL CPU_I2CSDA 1 3 2 4
C
SPI Interface Circuit
CON4
R23 V_UNREG 6k8 R26 3k6 5V
I2CSCL I2CSDA
C JP18
LCD Interface Circuit
CON3
3 2 1
R25 R27 1k2 1k2 JP12
M41ST87_IRQ M41ST87_VOUT 1 2 3 4 M41ST87_PFO 25 M41ST87_SQW 8 6 7 9 10 M41ST87_PFO 11 CPU_PB1 14 15 12 13
ECON TPCLR F32k GND
1 2 3 4
CPU_INT0 CPU_INT1
SENSOR1
LCD Module Only Operates on 5V
5V
5V
R10 4K7
GND
LCD
C6 104P
SENSOR2
1 2
LCD_EN CPU_PB7
I2C Interface Circuit with Battery PWM, ADC
JP14
B
1K
R0 4K7 JP3
3 VL 7101ADC CPU_PB6 4 CPU_PB5 5 LCD_EN 6
CPU_PA0 CPU_PA1 CPU_PA2 CPU_PA3 CPU_PA4 CPU_PA5 CPU_PA6 CPU_PA7 7 8 9 10 11 12 13 14 D0 D1 D2 D3 D4 D5 D6 D7
3 2 1
CPU_ADC0 CPU_ADC1 CPU_U2RXD CPU_U2TXD CPU_ADC4 CPU_ADC5 CPU_ADC6 CPU_ADC7
LCD Module
7101UART2 PB[5.. 7]
1 3 5 7 9 11 13 15
2 4 6 8 10 12 14 16
LCD_VL
C3 104pF LCD_VL LM358
1 2 3 4
JP13
R18 10K JP15 A
Title CPU_PWM0 CPU_PWM1 CPU_PWM2 CPU_SPI_CLK CPU_SPI_RXD CPU_SPI_TXD 1 3 5 7 9 11 2 4 6 8 10 12
A
CPU_PWM
Peripheral C24 105pF C25 104pF
Size B Date: File: Number Revision 4-August-2003 Sheet 3 of 4 C:\Documents and Settings\bo kang.ST
AI09612
2 3
1
4
5
6
1 6
VCC
2 CON3 CON1
CPU_CTRL V+ C1+ C1 T1IN T1OUT R1OUT R1IN T2IN T2OUT R2OUT R2IN V GND 15 RXD1 TXD1 8 RXD1 7 TXD1 13 RS232_RXD0 14 RS232_TXD0 C2+ 4 C2 5 VCC 16 VCC
3 UART2
4
5
CON2 C23 334pF 2
CPU_COMM 1
CPU_P1
U8
D
CPU_U1TXD CPU_U1RXD 10 9 6 12 11
Figure 26. Input/Output
CPU_RD CPU_PSEN CPU_WR CPU_ALE 5V 5V 3.3V_RST GND VREF
C22 334pF 3
C21 334pF
1 6 RS232_RXD0 2 7 RS232_TXD0 3 8 4 9 5
D
CPU_PB7 CPU_PB6 CPU_PB5 CPU_PB4 CPU_PB3 CPU_PB2 CPU_PB1 CPU_PB0 CPU_PD2 CPU_PD1 CPU_PC7 CPU_TDO CPU_TDI CPU_TERR CPU_TSTAT CPU_PC2 CPU_TCK CPU_TMS
CPU_P4
UART1
C20 334pF
1 CPU_U2RXD 3 6 CPU_U2TXD 4 5 2
CPU_PA7 CPU_PA6 CPU_PA5 CPU_PA4 CPU_PA3 CPU_PA2 CPU_PA1 CPU_PA0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CPU_ADC0 CPU_ADC1 CPU_U2RXD CPU_U2TXD CPU_ADC4 CPU_ADC5 CPU_ADC6 CPU_ADC7 CPU_AD7 CPU_AD6 CPU_AD5 CPU_AD4 CPU_AD3 CPU_AD2 CPU_AD1 CPU_AD0 CPU_PWM0 CPU_PWM1 CPU_PWM2 CPU_PCA0CLK CPU_SPI_CLK CPU_SPI_RXD CPU_SPI_TXD CPU_SPI_SEL 3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 30 29 28 27 26 25 Reset 24 23 22 21 CPU_DEBUG 20 CPU_ADDR_DATA GND 19 CPU_A11 18 CPU_A10 17 CPU_A9 16 CPU_A8 15 CPU_U1RXD 14 CPU_P3 CPU_U1TXD 13 CPU_INT0 12 CPU_INT1 11 CPU_P3.4 10 CPU_P3.5 9 CPU_I2CSDA 8 CPU_I2CSCL 7 VCC 6 VCC 5 GND 4 X2 3 2 1
ST3232 RS232 Interface Circuit
1 6 2 7 3 8 4 9 5
C CON30 CON30
CON30
VCC
IrDA Interface Circuit (disable shutdown) U9 TFDU4203
4 VCC VCC 7 TXD 3 2 RXD
C
Connector Encoder, Button, & LED
RS232_TXD0 RS232_RXD0 4 2 3 1 RXD1 TXD1
JP17 C32 104pF
VCC
VCC 8 7 6 5
R19 5
R9 4k7
0
R20 10
GND 1 8 GND SD 6 5 GND GND
C31 104pF
C34 4.7F
1 2 3 4
ENCODER
3 2 1 4 5 5 3 2 1 * 4
JP4 R5 R3 10K 10K
B
CPU_PB2 CPU_PB3 CPU_PB4
6 4 2
5 3 1
RS232, IrDA
B
C2 103P
C1 103P
Power Supply
J1
R14 1K5 R13
4 1 4
LED_TWO
1N4004
GND
VCC
1 SWITCH
D5
VUNREG 1
U6 78M05-5V
V IN VOUT 3
5V
LED_ONE
1
1K5 JP5
CPU_PD2 CPU_PD1 2 4 3 2 3 2 1 3
JP16 KEY2 SW PUSH-BUTTON
5V VCC 3.3V 3 2 1
5V 3
U5 LD1117-3.3V
GND
2
C30 220F
C26 104pF
D4 POWER
3.3V
KEY1 SW PUSH-BUTTON
C29 10F
VIN
VOUT
2
R17 1K C27 104pF
1
C28 10F A
Title Size B Date: File:
A Input/Output
Number Revision 4-August-2003 Sheet 4 of 4 C:\Documents and Settings\bo kang.ST
AI09613
2
1
3
4
5
6
AN1943 - APPLICATION NOTE
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AN1943 - APPLICATION NOTE
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