AN2010 APPLICATION NOTE
Interference Control during Mixed-Signal (Analog and Digital) Board Design
In a mixed-signal circuit, using both analog and digital components, the fast speed digital circuit section is always a potential source of noise, especially for the sensitive analog circuit section. The typical CMOS digital device has a very low quiescent current, but study shows that simultaneous switching noise (SSN, also known as ground bounce), caused by CMOS circuit switching current, forms the major contribution to the overall circuit noise. This application note describes how to deal with these problems, using an Analog-to-Digital converter as an example. The 90C7101 ADC Verification board is an internal verification tool, used by ST, and is not publicly available. However, it is used here as an illustrative example, since the PCB design rules are applicable to any board design. The 90C7101 Turbo-Lite microcontroller is a mixed-signal SOC chip that incorporates an Analog-to-Digital Converter (ADC), an 8-bit microcontroller, and various peripherals. The on-chip converter consists of an 8-input analog multiplexer, and a 10-bit binary successive approximation ADC. To achieve the 10-bit resolution, special attention should be paid to minimize the interference between digital and analog circuits. Figure 1. 90C7101 ADC Block Diagram
VREF
AVREF
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 Select Control ADCOUT - 10 Bits Analog MUX 10-Bit SAR ADC
ACON Register ADAT1 Register
ADAT0 Register
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TABLE OF CONTENTS
Figure 1. 90C7101 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 INTERFERENCE ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Current Flow through the Reactive Parasitic Components of a CMOS Output . . . . . . . . . 3 Figure 3. Current Flow through a CMOS Invertor, while its Output is Switching . . . . . . . . . . . . . . . 4 Figure 4. Lumped Parasitic Model of 90C7101 Power Lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 GENERAL DESIGN GUIDE FOR ADC CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 90C7101 ADC VERIFICATION BOARD DESIGN CONSIDERATION . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. ADC Verification Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Separate Power Supply Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 R educed Digital Switching Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Track Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 APPENDIX A.COMPONENT PLACEMENT AND SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Figure 7. Figure 8. Figure 9. Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 90C7101 ADC Verification Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 90C7101 ADC Verification Board MCU PSD Schematic. . . . . . . . . . . . . . . . . . . . . . . . . 10 90C7101 ADC Verification Board Power Supply Schematic . . . . . . . . . . . . . . . . . . . . . . 11
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 1. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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INTERFERENCE ANALYSIS
Figure 2. illustrates the circuit model of a CMOS output pad. CMOS devices operate by charging and discharging a capacitive load. When the output changes state from High to Low or Low to High, a current flows in the output loop. This current determines the output edge rate. Figure 2. Current Flow through the Reactive Parasitic Components of a CMOS Output
PCB Power
LPower LInput LOutput
I(t) LGnd CL
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Figure 3. shows a CMOS inverter. When a High (H) signal is applied at the input, the upper p-channel transistor is off and the lower n-channel transistor is on. The output is pulled to ground (Low) through the conducting n-channel. Similarly, when a Low (L) signal is applied at the input, the n-channel is off and the p-channel is on, pulling the output high through the conducting p-channel. When changing states from High to Low, the p-channel begins to turn off and the n-channel begins to turn on. In the threshold region (VIL < Vinput < VIH), both these transistors are partially ON, causing a through current, ICC, to flow from VCC to GND. A similar situation exists when the output switches from Low to High. Figure 3. Current Flow through a CMOS Invertor, while its Output is Switching
PCB Power
LPower
In
Out ICC
LGnd
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When the switching current flows over the parasitic inductor on the power lane, a noise voltage is generated. The 90C7101 features an 8-bit microcontroller which can work, at a maximum of 40MHz, with a memory bus cycle as short as 100ns. It is essential to isolate SSN caused by microcontroller section out of the analog section. 90C7101 has been designed to minimize digital-analog crosstalk by providing separated power and ground pins for its analog and digital sections. The analog section has dedicated analog supply (AV CC and AGND) as well as reference voltage input (VREF).
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To make full use of 10-bit resolution of 90C7101's ADC, special attention should be paid to the PCB design. Figure 4. illustrates a common circuitry connection with parasitic impedance shown at each power lane. Figure 4. Lumped Parasitic Model of 90C7101 Power Lane
90C7101 Input
VREF
Analog Section
A-D
Digital Section
+
AGND CA AVCC DGND CA DVCC
L1
L2
L3
L4
P1 L5 RS VS CS + L6
P2
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In Figure 4.:
P1 is the joint point of analog ground and digital ground, while P2 is the joint point of analog power and digital power. L1 and L3 represent parasitic inductor of the copper tracks that connect AGND to P1 and DGND to P1 respectively. L2 and L4 represent parasitic inductor of the copper tracks that connect AVCC to P2 and DVCC to P2 respectively. L5 and L6 represent parasitic inductor of the copper track that connects P1 to power supply negative end and P2 to power supply positive end respectively. R s represents the internal serial resistance of power supply.
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Each of these parasitic impedances has a different impact on the distribution of the SSN, depending on the route of the switching current. Taking the power supply's negative terminal as the reference point, the sw itching current flows over L3-P1-L5-Rs-L6-P2-L4. P1 and P2 are made noisy by a voltage drop on L5 and L6, respectively, which will further affect the analog circuit. Voltage drops at L3 and L1 make the analog and digital sections work at different ground levels, which will further affect the signal interface between the analog and digital sections ("A-D" in Figure 4.). L3 restrains the switching current of the digital section. However, the limited current source leads to a low slew rate of the digital circuit, which may cause a timing error in curtain conditions. L2, on the other hand, has the benefit of isolating the high-frequency switching noise out of the analog section. As the analog section often consumes a small, low-frequency current, L2 does not affect the normal operation of the analog section in the same way that L3 does to the digital section.
GENERAL DESIGN GUIDE FOR ADC CIRCUIT
The common approach to isolating SSN interference is through rigorous decoupling and grounding. The following discussion lists some basic rules that need to be observed.
U se a separate analog and digital ground plane. Ensure that the connection between each supply pin, and the corresponding power/ground plane, is as short as possible. In a single supply system, use the negative terminal of the capacitor, Cs, as the star point of the analog and digital ground plane, and the positive terminal of the capacitor as the star point of the analog and digital power plane. In this way, any common ground impedance will be eliminated by its parallel connection with Cs. The 90C7101 AGND terminal should serve as a star point for all analog ground connections, such as any reference voltages, and analog input signals. The 90C7101 DGND terminal should serve as a star point for all digital ground connections. U se two capacitors which differ in value by at least a factor of ten (typically 1F and 0.1F) to decouple the IC power pins. U se three capacitors (typically 100F, 4.7F, 0.1F) to decouple the power supply. U se SMD Tantalum capacitors for values greater than 4.7F, and COG or X7R capacitors for those less than 2.2F. The use of Z5U capacitors in high-resolution mixed-signal circuit is not recommended. Keep all bypass capacitors as close to the power pins of the device as possible. An inductor may be inserted into the L2 branch if necessary.
90C7101 ADC VERIFICATION BOARD DESIGN CONSIDERATION
To verify the resolution of the ADC at the board level, it is necessary to create an extremely clean environment that isolates any possible digital interference from the analog circuit. The 90C7101 ADC verification board adopts the following approaches to eliminating the digital-to-analog crosstalk.
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Figure 5. ADC Verification Board Block Diagram
90C7101 PSD Voltage Reference Analog Section Input Amplifier
AGND AVCC AVCC AGND DVCC DGND
Digital Section
UART
CLOCK
DGND DVCC
AGND
DGND1
DGND2
L
Vreg1 (3.3V)
G
Vreg2 (3.3V)
Vreg0 (5V)
Power Plug
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Separate Power Supply Scheme The verification board is designed to amount separated voltage regulators as shown in Figure 4.. VREG1 is dedicated to service the 90C7101, and VREG2 powers the other digital section, which includes the PSD, the oscillator, and the UART level shifter. The oscillator and the UART level shifter are either high frequency or high power. A dedicated regulator is essential to isolate these highly-noisy components from the IC under test. The voltage reference adopts MAX6129_EUT30, which features a 3V output, 0.4% accuracy, and 4mA output source current. The reference is directly sourced from the 5V power supply. Reduced Digital Switching Current The SSN source switching current greatly depends on the capacitive load on the 90C7101's output pad. To reduce the capacitive load, the verification board has been designed to be a minimum system for the 90C7101 microprocessor, consisting mainly of the PSD and oscillator. The sampled ADC data may be sent out, for monitoring, through the serial interface. All input-only pads are pulled up, and all unused bidirectional pads are configured in output mode by the firmware. Power Track Layout The ground terminals, of the three regulators, are joined together at point-G, which is the voltage reference point for the whole board. It is also the star point of the analog and digital power planes. The ground pins, of the analog and digital circuit sections, are connected to point-G through a separate, low impedance, power plane. This reduces the digital-to-analog crosstalk to minimum.
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APPENDIX A. COMPONENT PLACEMENT AND SCHEMATICS
Figure 6. Board Layout
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1 6
2
3
4
5
D
D
Power Power. SC H
Figure 7. 90C7101 ADC Verification Board Layout
C
MCU MCU.SCH
C
B
B
A Titl e Size B Dat e: File: 2 3 4 5 8 -J un -2 0 0 4 Sheetof D:\ ww Pro jects \Prot el\ Ver iADC.d db \ 6 1 3 Drawn By: China MMCC
A
90C7101 ADC Verification Board
Nu mber Rev i sio n
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2
3
1
4
710 1 U A RT0
39 40 92 93 43 94 45 95 51 53 55 57
1
3 OUT VREF GND 7 10 1 Clock J P_ VREF 1 2 3 CON3 9 0C71 0 1 7 10 1_ PSEN 7 10 1_ ALE 7 10 1_ RD 7 10 1_ WR 8 34 TDO F_TDO F_TCK F_TMS 7 10 1JTAG 9 0C7 1 0 1 35 14 12 1 3 MAX4 489 AVCC1 U9 _R 5 .1 k 4 U9 _C 0 .1 u U1 _C3 47u Pin ¸ 30 0¸ 40 0 3 3 7 3 ¸ 1 .5 ¸ 2 .6 PP 7 4 ¸ 2 .6 ¸ 1 .5 PP 1 3 ¸ C ¸ SB + NU 1 5 ¸ C ¸ SB NU DVCC1 U1 _C4 1u U1 _R2 1 .5 k U1 _C5 0.0 1u DVCC1 J P2 ADC5IN PSD_A1 4 1 3 An al og i npu t opti on 2: Low-no i se vol tage follower. 2 3 2 4 HEAD R 2X2 E 7 10 1 ADC5 7 10 1 _A14 U2_C1 1u ADC_IN2 13 15 2 DVCC2 ADC_IN2 J P_ AIN J PAIN_ R1 3 00 ADC_IN1 J P4 3 2 1 CON3 7 101 ADC0 7 101 ADC1 7 101 ADC2 7 101 ADC3 7 101 ADC4 7 10 1 ADC5 7 10 1 ADC6 7 10 1 ADC7 ADC0/ T2/ P1 .0 ADC1/ T2x /P1 .1 ADC2/ RXD2/ P1 .2 ADC3/ TXD2 /P1 .3 ADC4/ SPISCLK/P1 .4 ADC4/ SPIRX / P1 . 5 D ADC6/ SPITXD/ P1 .6 ADC7/ SPISSEL/P1. 7 D G N D ( Co re) D G N D ( IO ) DVCC 340 0 _ U SBD + 340 0 _ U SBD TDI TDO TDO??? TCK TMS TMS??? DEBUG 8 7 9 17 18 31 10 ADC5IN 8 U9 A 63 65 67 69 71 73 81 86 PSEN ALE RD RD??? WR 5 X1 X2 XTAL1 XTAL2 59 60
NC
IN
U1 _AC2 10u
U1 _AC1 0 .1 u F
7 101 _ VREF
91 89 90 AVCC AGND VREF
RX D 1 /P3 .0 T X D 1 /P3 .1 RX D 1 /P3 .0 T X D 1 /P3 .1 I N T 0/ P3 .2 I N T 0/ P3 .2 I N T 1/ P3 .3 I N T 1/ P3 .3 C0 /P3. 4 C1 /P3. 5 I 2CSD A /P3 .6 I 2CSCL /P3 .7
2
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2 6 3 4 5 DVCC2 J _UART U8 DVCC2 2 V+ C1 + C1 T1i n R1 ou t T2i n R2 ou t FLASH_ LINK DVCC2 FL_R1 FL_R2 1 0k 1 0k FL_R3 1 0k U8 won't be assembled until board no VST3 23 2 GND 15 R2 in 8 DVCC2 T2o u t 7 R1 in 1 3 RS23 2 _ RXD0 T1o u t 1 4 RS23 2 _ TXD0 C2 + 4 U8_C5 0 .1 u C2 5 RS23 2_ TXD0 VCC 1 U8_C3 0 .1 u 3 11 U8_R1 12 10 9 6 U8_C4 0 .1 u 14 12 DGND DGND 10 7 10 1R STIN 8 6 4 2 TER R GND GND R ST TSTAT CNTL TR ST TDO TCK TMS VCC TDI GND J EN DVCC2 FL_R 4 70 U1_R1 1 00 Vrx_ C3 0.0 1u Low-no i se voltage reference. Serial type. U1 AVCC1 TP_ AGND U3 U1_C1 4 .7 u U1 _C2 0 .1 u RST_OUT RST_IN 7 101 RSTOUT 8 3 7 101 RSTI N 8 8 7 10 1R STOUT 4 8 1 16 26 15 DVCC2 38 FL_C 1 0 .0 1 u FL_ C2 1u FL_ D DVCC2 C RED 13 11 9 7 5 3 1 1 00 RST_PB SW_ PB RST_C 1 05 P 7 101 UART0TXD 7 101 UART0RXD 16 X1 RST_ R 1 0k 7 10 1 RSTIN RST_ D 1 N41 4 8 U8_C2 0 .1 u U8 _C1 0.1 u U8 _C6 2 2u RS23 2_ RXD0 DVCC2 D 1 6 2 7 3 8 4 9 5
1
X1
DVCC2 4 1 2
VCC OE GND
OSC_OUT
3
X1_R1
2 00
D
OSC
DVCC2
X1 _C1 1u
X1_C2 0 .0 1 u
AN2010 - APPLICATION NOTE
RS232 Interface Circuit
7 10 1 UART0 TXD 7 10 1 UART0 RXD
F_TDO F_TCK F_TMS DVCC2 F_TDI DGND
C
5V
Vrx _ L
1 mH
Vrx _ C1 1 00 u
Vrx _ C2 1u
U2 RESET GND GND GND Vcc Vcc PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 29 28 27 25 24 23 22 21
4
NC
MAX6 129 _ EUK3 0 -T
AVCC1 7 101 _ VREF VREF
AD0 /P0. 0 AD1 /P0. 1 AD2 /P0. 2 AD3 /P0. 3 AD4 /P0. 4 AD5 /P0. 5 AD6 /P0. 6 AD7 /P0. 7 AD8 /P2. 0 AD9 /P2. 1 AD1 0/ P2 .2 AD1 1/ P2 .3 AD1 2/ P2 .4 AD1 3/ P2 .5 AD1 4/ P2 .6 AD1 5/ P2 .7
41 42 44 46 52 54 56 58 62 64 66 68 70 72 74 75
7 10 1_ AD 0 7 10 1_ AD 1 7 10 1_ AD 2 7 10 1_ AD 3 7 10 1_ AD 4 7 10 1_ AD 5 7 10 1_ AD 6 7 10 1_ AD 7 7 10 1_ A8 7 10 1_ A9 7 10 1_ A10 7 10 1_ A11 7 10 1_ A12 7 10 1_ A13 7 10 1_ A14 7 10 1_ A15
710 1 _ AD0 710 1 _ AD1 710 1 _ AD2 710 1 _ AD3 710 1 _ AD4 710 1 _ AD5 710 1 _ AD6 710 1 _ AD7
30 31 32 33 34 35 36 37
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
B
38 37 36 34 33 32 20 19 T2/ TCM0/ P4 .0 T2x / TCM1 /P4 .1 RXD2/ TCM2/ P4 .2 TXD2/ PCA0 /P4 .3 SPISCLK/TCM3 /P4 .4 SPIRXD/TCM4/ P4 . 5 SPITXD/ TCM5 / P4 .6 SPISSEL/PCA1/ P4 . 7 84 6 85 87 82
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
7 6 5 4 3 2 52 51 F_TMS F_TC K J TAG
B
Figure 8. 90C7101 ADC Verification Board MCU PSD Schematic
AVCC1
710 1 _ A8 710 1 _ A9 710 1 _ A10 710 1 _ A11 710 1 _ A12 710 1 _ A13 PSD_ A1 4 710 1 _ A15
39 40 41 42 43 44 45 46 710 1 _ WR 4 7 710 1 _ RD 5 0 710 1 _ PSEN 4 9 710 1 _ ALE 1 0
AIN1 _ R1 1k AVCC1
AIN1 _R2 3k
ADC_IN1
15 J PAIN_ C1 1 3 11 0 .1 u 9 7 5 3 1
16 14 12 10 8 6 4 2
AD8 AD9 AD1 0 AD1 1 AD1 2 AD1 3 AD1 4 AD1 5 CNTL0 CNTL1 CNTL2 PD0 PSD83 4 F2 V
PC0 PC1 PC2(VSTBY) PC3 PC4 PC5 PC6 PC7 PD1 PD2
20 19 18 17 14 13 12 11 9 8
F_TDI 8 34TDO
AIN1 _ D TS43 1 -Z
AIN1 _ C1 1 0u
AIN1_ C2 0 .1 u
AIN1 _R3 1 0k
TP_ ADCIN
U2 _C2 0.0 1u
U2_C3 1u
U2 _C4 0 .0 1 u
A
A Titl e Size B Dat e: File: 4 5
An al og input option 1: For t es t only.
90C7101 ADC Verification Board
Nu mber Rev i sio n
MCU, PSD
8 -J un -2 0 0 4 Sheetof D:\ ww Pro jects \Prot el\ Ver iADC.d db \ 6 2 3 Drawn By: China MMCC
1
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1
2
3
4
D
D
J1 D5 1 Vin G ND U6 _C2 1 00 u U6 _C4 1u U6 _R 1K U6 _C3 0 .0 1 u Vo ut SWITCH 1 N40 0 4 U6 _C1 2 20 u F 2 3 V_ UNREG 5V
SW1
U6 7 8M 05 -5 V
C
U6 _LED RED
C
DVCC1
5V G ND Vin 1 00 u H U5 _C2 0 .0 1 u U5 _C3 1 00 u U5 _C4 1u AV1 _C1 1 00 u AV1 _C2 1u AV1 _C3 0 .0 1 u Vo ut 2 AV1 _L
U5 LD11 1 7 -3 .3 V AVCC1
3
B
1
B
TP_ AGND0
J P1 U7 LD11 1 7 -3 .3 V Vin GND CON3 Vo ut 2 J P1 _ C2 0 .0 1 u 1 2 3 DVCC2 J P1 _ C3 1u J P1 _ C4 1 00 u F
Figure 9. 90C7101 ADC Verification Board Power Supply Schematic
5V
3
1
TP_ DGND1 CB1 Titl e
A
DG ND
A GND
Size A4 Dat e: File:
90C7101 ADC Verification Board
Nu mbe r Rev i sio n
A
Power Supply
8 -J un -2 0 0 4 D:\ ww\ Pro jects \Pro tel\ VeriADC.d db 3 4 Sheet 3 of 3 Drawn By: China MMCC
1
2
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REVISION HISTORY
Table 1. Document Revision History
Date 15-Oct-2004 Version 1.0 First Issue Revision Details
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If you have any questions or suggestions concerning the matters raised in this document, please refer to the MPG request support web page: http://www.st.com/askmemory
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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