TA0316 TECHNICAL ARTICLE
GreenFIELD-STW21000 RECONFIGURABLE MICRO-CONTROLLER
1 Product Highlights
bs O
System-On-Chip integrating an ARM926 Micro-Controller, embedded SDRAM and an Embedded FPGA array for Supervision and Control tasks ARM926: 32/16-bit RISC Architecture with instruction set for maximum performance, flexibility and high code density running at 300 MHz, and with AMBA Bus Architecture operating at ½ CPU Frequency. Built-in Memory Management Unit for OS Support 32 kBytes L1 Program Cache and 16kBytes L1 Data Cache Embedded FPGA Array: 150kGates ASIC Equivalent running at 200MHz 16 Mbit embedded SDRAM Two 10-bit 8-Channel Analog-to-Digital Converters with sampling rate of 1 Msps Four 10-bit Single Channel Analog-to-Digital Converters with sampling rate of 1 Msps Three 10-bit Digital-to-Analog Converters withsampling rate of 1 Msps External Memory Controllers with DDR SDRAM and Static Devices Support Dual 16-channel DMA Engines Five Master/Slave I2C Bus Interface Six 32-bit General Purpose Timer Units - Single Watchdog Unit Real Time Clock Dual UARTs Vectored Interrupt Controllers Ethernet MAC Four HDLC Controllers 16-bit General Purpose I/O On-Chip Emulation / Real-Time Embedded Trace Watchdog Power-On Reset Module with Power Supply Voltage Monitoring Synchronous Serial Port, including SPI and Microware compatible Development tools available
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
TA0316/0405
1/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316
2 Overview / Description
The GreenFIELD-STW21000 System-On-Chip is a low-cost, versatile high performance and reconfigurable micro-controller able to manage control tasks within complex Telecommunication Infrastructure equipment such as Base Transceiver Stations. The GreenFIELD ASSP is designed to be extremely flexible and it can be used in many places within Telecom Equipment. It can fulfill control tasks as well as monitoring. Figure 1 shows a block diagram of the GreenFIELD. The Embedded FPGA technology offers a high degree of flexibility. It allows the GreenFIELD to be reconfigured. The Embedded FPGA can be used to remap I/Os or to implement specific custom logic. Figure 1. GreenFIELD ASSP Block Diagram
Debug ETM9 Multi Port Memory Controller Static Memory Controller Vectored Interrupt Controller Ethernet MAC Ethernet MAC DMA DMA
DMA 1
M S M M
DMA 2
S M
926
Transfer Cross Bar
AHB - APB
2x UAR T
M SP 5 x I 2C
6x 10-bit ADC
6x32-bit Timers 16-bit GPIO Watch Dog
Sys tem C ontro lle r 3x 10-bit D AC
16 Mbit Embedded DRAM
POR
RTC
3 Architecture Overview
The GreenFIELD micro-controller includes an ARM926 micro-controller, used as a master for the complete system. It allows the setup of peripherals within the system, as well as the control of the data flow. The GreenFIELD used with external Flash Devices can boot in stand-alone mode. The Embedded FPGA can be setup using an external Serial Flash, with the help of an I2C or SPI Bus Interface. The DMA Controller, allows data exchanges between specific parts of the system such as the High Speed Communication Peripherals, or the ADC/DAC converters. The GreenFIELD bus architecture is based on the Multi-Layer AHB. This bus architecture provides a large amount of bandwidth in the system, and prevents the bus architecture from being a bottleneck. An 16MBit memory provides data storage capability shared among the CPU, and I/O peripherals. It allows storage of a collection of data coming from HDLC Controllers, Ethernet or other DMA-based peripherals.
bs O
let o
od Pr e
ct u
(s)
Ob -
4x HDLC
so
te le
AHB2MEM
2 kB x 16 DPRAM
ro P
uc d
2 kB x 16 DPRAM
s) t(
Reconfigurable Interface (150 kGates)
100
2 kB x 8 2 kB x 8 2 kB x 8 2 kB x 8 DPRAM DPRAM DPRAM DPRAM
2/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316
The Embedded FPGA offers 150k Gates of reconfigurable logic, which can represent simple custom interfaces, as well, as more complex logic designs. The FPGA Array is connected to the rest of the system, through built-in AHB Interfaces. It is connected to specific system parts such as Interrupt Controller, timer, Clock Generation, System Controller, etc... DPRAM Memories are available around the FPGA Macro, to allow processing storage or data exchange between the Embedded FPGA prototyped logic and the rest of the system.
4 PrimeXSysTM Overview
The GreenFIELD ASSP is based on the ARMTM PrimeXSysTM open platform built around the ARM926TM core and including a set of Peripherals and an AMBA Multi-Layer AHB system bus (Transfer Cross bar) for maximizing the throughput. Figure 2 shows the main PrimeXSysTM blocks Implementation within the GreenFIELD ASSP. Colored blocks show enhancements provided to the PrimeXSysTM platform.
4.1 ARM926TM CORE The ARM926TM Core combines the industry-leading performance and very low power consumption of the ARM9ETM technology, with support for virtual memory addressing, which is required by many of the leading operating systems. The ARM926TM core also incorporates independently configurable 32K-byte Instruction and 16K-byte Data Caches. The built-in Memory Management Unit provides virtual memory features required by Operating Systems. The ETM (Embedded Trace Module) is provided to monitor the ARMTM Core buses and to pass compressed information via the trace port to the Trace Port Analyzer tool. The debug tools retrieve data from the analyzer, reconstruct an historical view of the processor's activity including data accesses, as well as configuring the Macro cell via the JTAG port. 4.2 PrimeXSysTM BLOCK DIAGRAM
Figure 2. PrimeXSysTM
Debug ETM9
O
bs
let o
.
Pr e
926
32-bit Ti mers 16-b it GPIO Watch Dog
Syst em Con troller 3x 10-bit DAC
ARM
du o
Multi Port Memory Controller
(s) ct
Stati c Memory Controll er
so Ob DMA 1
M S M M S
te le
ro P
uc d
s) t(
Vectored Interrupt Control ler
DMA 2
M
Ethernet MAC Ethernet MAC DMA DMA
Transfer Cross Bar
2 kB x 16 DPRAM 2 kB x 16 DPRAM
AHB - APB UART MSP 2xIC
6x 10-bit ADC
2
16 Mbit Embedded DRAM
POR
4x HDLC
150kGates Embedded FPGA
2 kB x 8 2 kB x 8 2 kB x 8 2 kB x 8 DP RAM DPRAM DPRAM DPRAM
AHB2MEM
RTC
3/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316
5 GreenFIELD Description
5.1 SYSTEM ARCHITECTURE The System has been designed around an AMBA Multi-Layer AHB backbone, built as multiple Transfer cross bars. These cross bars allow any input port to address any of the output port, allow a number of masters to address the same set of slave peripherals. Because of its structure, input ports can do parallel accesses, if it's targeting different output ports. Concurrent accesses to the same output port, is managed by the cross bar arbiter. This cross bar provides a large amount of bandwidth in the system, and prevents the bus architecture from being a bottleneck. Figure 3 shows the GreenFIELD Bus Structure. The ARM926TM provides separate Instruction and Data Bus interfaces; enabling simultaneous access for Instruction fetches and Data operations e.g. allowing instruction cache line fills to be performed in parallel with data accesses to system peripherals. The ARM926TM can fetch instructions from external memory through an External Memory Controller, from internal DRAM memory. GreenFIELD implements 4 main slave parts accessible via the Transfer Cross Bar. The embedded FPGA is accessible from any of the masters, using a build-in AHB interface, converting AHB protocol to a simple Memory Bus protocol, usable in the FPGA Array. The 16 Mbit embedded DRAM memory, splitted in 2 x 8 Mbit banks, can be used to store data from High Speed peripherals such as Ethernet, Multi-channel Serial ports, or HDLC controller and are accessible in parallel. It can be used to store ARMTM instructions/data as well. The Embedded DRAM blocks include a page caching technique, used to increase the bandwith. A set of standard peripherals, used for Operating System support as well, is accessible through an AHB-to-APB bridge. Those peripherals include UARTs, 32-bit Timers, Watchdog, SPI and I2C Interfaces, GPIOs, and System Controller. Within this set of peripherals, six Analog-to-Digital and three Digital-to-analog converters, are available to offer monitoring and control capabilities. ADCs and DAC are 10-bit resolution, working with a sample rate of 1 MSPs. The last set of peripherals is dedicated to High Speed communication, and includes MultiChannel Serial Port, Ethernet MAC and HDLC interfaces.The DMA engines can hanfle data flow to the dual bank 8 Mbit memories or the external devices, through the use of External Memory Controllers. In order to manage system Interrupts; GreenFIELD includes Interrupt Controllers, able to support high priority sources, thanks to the vectored interrupt mechanism. Interrupts sources are internal peripherals; external interrupts, as well as I/Os coming from the Embedded FPGA. The GreenFIELD provides multiple boot modes. Beside classical boot mode, GreenFIELD offers a stand-alone mode of operation. It provides the capability to boot the chip without the help of an external clock source, by using an internal generated clock (Oscillator). The system uses, then, a boot engine (Boot FSM) to load the ARMTM boot routine and the Embedded FPGA bit stream from the I2C or SPI interfaces, using Serial Flash devices.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
4/14
ETM
ARM926 DMA 1 DMA 2
M-AHB#0 S-AHB M-AHB#1 S-AHB M-AHB#0 S-AHB M -AHB#1 M-AHB S-APB M -AHB S-APB
Figure 3. GreenFIELD Bus Structure
BSW-A
8-Mbit eDRAM
8-Mbit 8-Mbit eDRAM eDRAM
Real T ime Clo ck 10-bit ADC 10-bit ADC 10-bit ADC 10-bit ADC 32-bit T imer 16-bit GPIO
AHB2AHBlite AHB2AHBlite AHB2M EM
bs O
Ethernet MAC DMA Ethern et MAC DMA
Debug
let o
VIC VIS-AHB C
AHB-APB 10-bit ADC 10-bit DAC
Boot FSM
BSW-B BSW-C
Pr e
AHB-APB
du o (s) ct
AHB-APB AHB-APB AHB-APB
DPRAM
Test & Config
so Ob 10-bit ADC 10-bit DAC MS P I2C
UART HDLC
I2C
te le
10-bit DAC
DPRAM
HDLC
#1
#0
#2
S -AHB
Embedded FPGA
ro P
Multi Port Memory Controller
HDLC
DPRAM DPRAM DPRAM DPRAM
HDLC
uc d
Static Memory Co ntroller
Oscillator
System Controller
PoR
Wat chdog
s) t(
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316
5/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316
The GreenFIELD includes an Embedded FPGA array, composed of 7168 Logic Elements over 56 clusters. 1 Cluster includes 128 Logic Elements. Overall, the Array is equivalent to 150k ASIC Gates. The macro architecture is a multi-stage hierarchical Interconnect Network ensuring a predictable and bounded delay between any programmable element and/or I/Os. A Logic Element is composed of 4 inputs and 1 output SRAM programmable element, including a 4 input LUT and a general-purpose storage element.
Figure 4. eFPGA Implementation
I/Os other Logic Blocks
Muxed I/Os
2 kB x 16 DPRAM 2 kB x 16 DPRAM
Test & Config
AHB
bs O
Figure 4 shows how the Embedded FPGA is implemented in the GreenFIELD. An AHB Slave interface allows accessing the eFPGA logic, from any of the master in the system. This interface could be used to control/Configure the prototyped logic. Two 2kbytes x 16-bit Dual-Port RAMs are available to transfer data between prototyped logic and data flow peripherals such as DMA controllers. Four additional DPRAMs (2kbytes x 8-bit) are available to the prototyped logic, as local storage RAM. A Test & Configuration interface is available to load the FPGA logic inside the Macro. Specific GreenFIELD IP Blocks, such as the Interrupt Controller, DMA Engines, have set of signals connected to the Embedded FPGA Macro, allowing interactions with the system. The macro architecture is based on LUT. The interconnect is built using a Global Network ensuring a predictable and bounded delay between any programmable element and/or I/Os. It is a scalable point-to-point distant connection, or point to n-point local connections. Figure 5 shows the Embedded FPGA Macro Architecture. The Global Routing Network links Clusters together and to peripheral I/Os. The Local Routing Network links Logic Elements together and to the Global Routing Network. No specific Clock signal is required, allowing the use of any of the Input / Output to route clock signals. A built-in interface is used for FPGA programming allowing the ARMTM, the DMA to setup the FPGA content.
let o
AHB System Bus
Embedded FPGA
Optional Ext Clock
Clock Inputs from System Controller
2 kB x 8 2 kB x 8 2 kB x 8 2 kB x 8 DPRAM DPRAM DPRAM DPRAM
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
AHB Slave
From / To Other Logic Blocks
6/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316 Figure 5. Embedded FPGA Macro Architecture
Em bedded FPGA MACRO
CLUSTER
Lo g ic Ele me n t Log ic Ele me n t
CLUST ER
Lo g ic Ele me n t Log ic Ele me n t
LOCAL ROUTING NETWORK
LOCAL ROUTING NETWORK
GLOBAL ROUTINGNETWORK
I
I
I
I
OO
OO
Programming & Test
A Logic Element is composed of 4 inputs and 1 output SRAM programmable element, including a 4 input LUT and a general-purpose storage element. Storage element may receive initialization value, clock and clock enable from cluster-wide global signals. Figure 6 shows a Logic Element Structure. The Embedded FPGA is directly connected to a 2Kbytes SRAM, which can be used for data processing. The Memory interface to access this SRAM is userdefined and can be configured following the application requirements.
Figure 6. Logic Element Structure
Input 1 Input 2
bs O
let o
Input 4
Input 3
Pr e
du o
(s) ct
LUT
so Ob -
te le
ro P
uc d
s) t(
S
D Q
FF/LATCH
Ce L R S Ck
Global CLK Enable Global Initialisatio n
1
0
Global CLK
0
7/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316 5.2 DDR SDRAM External Memory Interface The DDR SDRAM External Memory Interface is a multi-port memory controller which is connected to the ARM926TM Instruction and Data Busses as well as on the DMA Controller. The External Memory Interface is used by the ARMTM sub system to access its Program, and Data. The External Memory Interface offers the following features: AM BA 32-bit AHB Compliancy Dynamic Memory Interface support including DDR SDRAM, low-power SDRAM, Micron SyncFlash, and Micron VsyncFlash. Asynchronous Static Memory device support including RAM, ROM, and Flash, with or without asynchronous page mode. Software support for 8 and 16-bit NAND flash Read and Write Buffers to reduce latency and to improve performance 8-bit, 16-bit wide static memory support 16-bit wide data bus SDRAM and SyncFlash memory support. 16-bit wide data bus DDR SDRAM support Static Memory features include: Asynchronous page mode read Programmable wait states Bus turnaround cycles Output enable, and write enable delays Extended wait states Two Chip Selects for Dynamic memory and four chip selects for static memory devices Dynamic control of Power-Saving Modes 5.3 Static Memory Controller The Static Memory Controller provides the following features: Support of static-mapped devices including RAM, ROM flash and burst ROM Asynchronous page mode read operation in non-locked memory subsystems Asynchronous burst mode read access from burst mode ROM and flash devices 8-bit wide external memory data paths Programmable Wait States Programmable Output Enable and Write Enable delays External Asynchronous wait control Configurable Size at Reset for Boot Memory Bank using external control pins
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
5.4 Interrupt Controller The Interrupt Controller provides a simple software interface to the interrupt system. It improves interrupt latency by providing vectored interrupt support for high-priority interrupt sources. The Interrupt Controller has the following features: 64 Standard interrupts (IRQ) 32 Vectored Interrupts (VIRQ)
8/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316
Hardware Interrupt Priority Definition IRQ and FIQ (Fast Interrupt Request) Generation Software Interrupt Generation Raw Interrupt Status Interrupt Request Status Interrupt Masking Privileged mode Support
5.5 DMA Controller The DMA (Direct Memory Access) controller allows data movement from and to internal memory, internal peripherals or external devices. These data transfers occur in the background of CPU operations. GreenFIELD implements two instances, having up to 16 DMA Channels available for data transfer. The following features are available for each instance: 16 DMA Channels. Each channel can support an unidirectional transfer 16 DMA Hardware or Software Requests Hardware Channel Priority Programmable DMA burst Size Internal Four word FIFO per channel. Supports 8, 16 and 32-bit Wide Transactions Interrupt Masking and Raw Interrupt Status 5.6 Ethernet MAC The Ethernet MAC peripheral is designed to run according to the IEEE 802.3 and 802.3u specifications that define the 10 Mbps and 100 Mbps Ethernet Standards. It includes: Single DMA Channel to manage transfers from Ethernet block to Memory. Collision Detection in Half-Duplex mode (CSMA/CD protocol) Support for control frames in Full Duplex mode (IEEE 802.3x) IEEE 802.3 Media Independent Interface (MII), and General Purpose Serial Interface (GPSI) Pream ble generation and removal Autom atic 32-bit CRC generation and checking Complete Status for transmission and reception packets
bs O
5.7 UART The two UART peripherals provide serial-to-parallel and parallel-to-serial data conversion. The UART includes a programmable baud rate generator that provides a common transmit and receive internal clock. This UART offers similar functionality to the industry standard 16C550 UART device. 5.8 Real Time Clock The Real Time Clock is a 32-bit counter, incremented on successive rising edge of its input clock. The counter is free running and cannot be loaded. The counter is not connected to the global system reset and operates in all low-power modes, requiring an external back-up power supply and clock. The RTC can be programmed to generate periodic interrupts.
9/14
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316 5.9 32-bit Timer Several timers are available within the System. Six timers are dedicated to the ARMTM subsystem, within the Core APB. Each timer is a 32-bit wide counter with selectable pre-scale. The pre-scale allows either the system clock to be used directly, or the clock divided by 16 or 256 may be used. Three modes of operations are available, free-running, periodic timer and one-shot timer. In periodic timer mode the counter will generate an interrupt at a constant interval. In free-running mode the timer will overflow after reaching its zero value and continue to count down from the maximum value. In one-shot mode, the Timer generates an interrupt once. The Six timers are connected to the Vector Interrupt Controller (VIC). 5.10 GPIO The GPIO peripheral provides 16 programmable inputs or outputs. An interrupt interface is provided to configure any number of pins as Interrupt Sources. Interrupts can be generated depending on Level or Transition Value of a pin. 5.11 I2C The I2C block provides a Master or Slave interface operation modes. It can perform arbitration in master mode to allow it to operate in multi-master systems. In slave mode, it can interrupt the processor when it recognizes its own 7-bit or 10-bit address or the general call address. 5.12 WatchDog T0he watchdog timer provides a way to recover from software crashes. The watchdog generates a regular interrupt, depending on a programmed value. This value is contained in a 32-bit counter register. The watchdog monitors the interrupt and asserts a RESET signal if the interrupt remains un-serviced for the entire programmed period. The watchdog unit can be disabled or enabled following requirements. 5.13 Analog-to-Digital Converters The GreenFIELD includes two 8-channel and four single-channel 10-bit Analog-to-Digital converters, with sampling rates of up to 1 Msps. The 8-channel ADC provides the capability to sample one, two, four or up to eight different input sources (8 channels). The sampling rate is dependent on the number of channels used and goes from 125 Ksps (8 Channels mode) up to 1 Msps (Single Channel Mode). ADCs inputs are single-ended or differential. The input range in single-ended mode is from 0 to 2.4 V. It is from -2.4V to 2.4V in differential mode Its absolute accuracy is 20mV (single-ended) or 40mV (differential). ADC implements a Low-Power mode with fast wake-up time. The Integral non-linearity (INL) parameter is < 2 LSb and the Differential non-linearity (DNL) parameter is < 1.6 LSb.
bs O
5.14 Digital-to-Analog Converters GreenFIELD includes as well, three 10-bit Digital-to-Analog converters, delivering 1 Msps. DAC outputs are single-ended or differential. The output range from 0 to 2V in single ended mode. It is from -2V to 2V in differential mode. Its driving capability is 5k // 100pF. Its absolute accuracy is 40 mV in single ended mode and 80mV in differential mode. It implements a LowPower mode with fast wake-up time. The INL parameter is < 2 LSb and DNL parameter is < 0.9 LSb. The Internal Reference voltage (1.215V) is available via an external pin. This reference voltage is buffered and able to drive a 5k // 100pF load.
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
10/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316 5.15 PLL & System Controller The System Controller is in charge of the clock generation and the power management. It offers several low-power modes (ILDE modes). The System controller provides also the capability to switch-off / switch-on individually and dynamically the clock provided to peripherals of the GreenFIELD. The GreenFIELD System Clock, used to clock the complete chip, can come from multiple sources. The System Clock is the main clock input to the System Controller, which then dispatch the clocks to the complete chip. The System Clock source can be an external oscillator or an external crystal, connected to a dedicated set of pins. The System Clock source can come also from the Embedded FPGA, allowing controlling the clock generation, using a custom logic mapped in the Embedded FPGA Macro. To allow this custom clock management, an internal clock (oscillator) provides the capability to start-up the chip without the help of external crystal or oscillator circuitry. This internal oscillator is based on capacitor charge and discharge with a fix current, and does not require any external components. It's absolute frequency is 500 kHz 200 kHz. The frequency drift is 5%. 5.16 Power On Reset A dedicator supervisory controller is used to monitor the power supply voltages (3.3V and 2.5V I/O Power Supply and 1.2V Core Power Supply) of the GreenFIELD, allowing to issue a RESET signal whenever the power supply voltage falls below a preset threshold. The RESET signal is used to RESET on-chip system as well as off-chip system. The reset thresholds are set at 2.63V (3.3V Power Supply), at 2V (2.5V Power Supply) and at 0,95V (1.2V Power Supply). The RESET signal stay asserted at least for 150ms after the supply voltage risen up above the threshold. 5.17 Multi Channel Serial Port The Multi Channel Serial Port (MSP) is a synchronous receive and transmit serial interface. The MSP provides the following features: Full Duplex communication with double-buffered data register M ulti Channel Transmit and Receive of up to 128 channels Elem ent (data) sizes of 8, 10, 12,14, 16, 20, 24 and 32-bits, LSB or MSB first -Law and A-Law companding. Independent framing and clocking for receive and transmit. Direct interface to SPI
bs O
5.18 HDLC Controller GreenFIELD includes four Single-Channel HDLC controllers. Single-Channel HDLC is a Protocol Controller, which handles a full duplex channel, with a Serial Interface for packet data transfer. On transmit channel, HDLC controller handles Flag insertion, bit stuffing, and 16-bit or 32-bit FCS. On receive channel, it handles flag delineation, bit de-stuffing, 16-bit or 32-bit CRC verification and length checking.
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
11/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316
6 Development Support
ST Microelectronics provides a complete set of development tools around the GreenFIELD ASSP, to evaluate the product performance, develop, debug and integrate Application Code on the GreenFIELD Product.
6.1
SOFTWARE DEVELOPMENT TOOLS
6.1.1 ARM Software Development Tools ARM Development Tools include an Integrated Development Environment tool, the C/C++ Compiler, Assembler and Linker Code Generation, the Instruction Set Simulator and the OSaware Debugger application for Simulation and Emulation Debug. 6.1.2 RTOS Development Tools To develop around the RTOS, we provide a comprehensive suite of software tools for application-level debugging and analysis of embedded applications. It includes Runtime Debugging, System and Process information viewing, Manual Process Control, System Event Tracing and Monitoring, Memory Analysis and Message Search, CPU usage analysis and more. 6.2 SUPPORT SOFTWARE LIBRARY The GreenFIELD ASSP is provided with a complete set of software libraries, which includes ARMTM Device Drivers, as well as the GreenFIELD Starter Kit BSP (Board Support Package). 6.2.1 OPERATING SYSTEM SUPPORT ST provides a Real-time Kernel, which combines a simple, elegant approach to the problems of distributed computing with a unique set of fault-tolerant mechanisms, high performance and true real-time behavior. It is a fully pre-emptive kernel with priority-based scheduling, optimized to provide high rates of data throughput yet compact enough for use in most embedded systems.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
12/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316 6.3 FPGA DEVELOPMENT TOOLS To design and program the Embedded FPGA Array, a comprehensive and standard development flow, allows the use of 3rd Party tools for Synthesis. The mapping on the Embedded FPGA array is performed by dedicated proprietary tools, which take advantage of the FPGA technology to obtain optimal results. Figure 7. Embedded FPGA Design Flow
RTL
FRONT END
Translation Libraries
Gate Libraries Operators
SYNTHESIS
Logic Blocs Netlist
EDIF VERILOG
COMPILER
Configuration Files
Simulation Model Generator
Static Timing Analyzer
Binary Generator
Simulation Model
Static Timing Analysis Report
6.4
HARDWARE DEVELOPMENT TOOLS
6.4.1 Starter Kit The GreenField Starter Kit is used to evaluate the GreenFIELD ASSP performance, as well as to develop Software Application. It offers a basic set of peripherals in addition to the GreenFIELD built-in peripherals. The starter kit is usable as a stand-alone board, or as a daughter card. In that case, multiple daughter cards can be plugged on a System Application Backbone (mother board), which represents the System to prototype.
bs O
6.4.2 JTAG Probe / Trace Port The JTAG Probe is the device doing the link between the Host Computer running debugging tools, and the GreenFIELD ASSP. The Trace Port device is used to capture the Real Time Trace, coming out from the Embedded Trace Module, allowing Real Time Debug, with Software Development tools.
let o
Pr e
du o
(s) ct
Ob -
DESIGN VERIFICATION
so
te le
Programming Bit Stream
ro P
uc d
s) t(
GreenFIELD
13/14
GreenFIELD-STW21000 TECHNICAL ARTICLE TA0316
The present note which is for guidance only, aims at providing customers with information regarding their products in order for them to save time. As a result, STMicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connection with their products.
bs O
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. Nomadik is a trademark of STMicroelectronics All other names are the property of their respective owners 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
14/14
|
