AN557 APPLICATION NOTE
EASY APPLICATION DESIGN WITH THE L4970A, MONOLITHIC DC-DC CONVERTERS FAMILY
The L497XA series of high current switching regulator ICs exploit Multipower-BCD technology to achieve very high output currents with low power dissipation up to 10A in the Multiwatt power package and 3.5A in a DIP package .
THE TECHNOLOGY The technology architecture is based on the vertical DMOS silicon gate process that allows a channel length of 1.5 micron ; using a junction isolation technique it has been possible to mix on the same chip Bipolar and CMOS transistors along with the DMOS power components (Fig. 2). Figure 1 shows how this process brings a rapid increase in power IC complexity compared to conventional bipolar technology. In the 70's class B circuits and DC circuits allowed output power in the range of 70W. By 1980, with the introduction of switching techniques in power ICs, output powers up to 200W were reached ; with BCD technology the output power increased up to 400W.
November 2003
1/52
AN557 APPLICATION NOTE
Figure 1. BCD process and increase in power ICs complexity.
Figure 2. Cross Section of the BCD Mixed Technology.
THE STEP-DOWN CONFIGURATION Fig. 3 shows the simplified block diagram of the circuit realizing the step-down configuration. This circuit operates as follows : Q1 acts as a switch at the frequency f and the ON and OFF times are suitably controlled by the pulse width modulator circuit. When Q1 is saturated, energy is absorbed from the input which is transferred to the output through L. The emitter voltage of Q1, VE, is Vi-Vsat when Q is ON and -VF (with VF the forward voltage across the D diode as indicated) when Q1 is OFF. During this second phase the current circulates again through L and D. Consequently a rectangular shaped voltage appears on the emitter of Q1 and this is then filtered by the L-C-D network and converted into a continuous mean value across the capacitor C and therefore across the load. The current through L consists of a continuous component, ILOAD, and a triangular-shaped component super-imposed on it, IL, due to the voltage across L.
2/52
AN557 APPLICATION NOTE
Figure 3. The Basic Step-down Switching Regulator Configuration
Fig. 4 shows the behaviour of the most significant waveforms, in different points of the circuit, which help to understand better the operation of the power section of the switching regulator. For the sake of simplicity, the series resistance of the coil has been neglected. Fig. 2a shows the behaviour of the emitter voltage (which is practically the voltage across the recirculation diode), where the power saturation and the forward VF drop across the diode era taken into account. The ON and OFF times are established by the following expression : TO N V o = ( V i V s a t ) ------------------------------T +T
ON OFF
Fig. 4b shows the current across the switching transistor. The current shape is trapezoidal and the operation is in continuous mode. At this stage, the phenomena due to the catch diode, that we consider as dynamically ideal, are neglected. Fig. 4c shows the current circulating in the recirculation diode. The sum of the currents circulating in the power and in the diode is the current circulating in the coil as shown in Fig. 4e. In balanced conditions the IL+ current increase occuring during TON has to be equal to the IL decrease occurring during TOFF. The mean value of IL corresponds to the charge current. The current ripple is given by the following formula : ( Vi V s a t ) Vo V o + VF + I L = I L = --------------------------------------- TO N = ------------------- T O F F L L It is a good rule to respect to IoMIN IL/2 relationship, that implies good operation in continuous mode. When this is not done, the regulator starts operating in discontinuous mode. This operation is still safe but variations of the switching frequency may occur and the output regulation decreases. Fig. 4d shows the behaviour of the voltage across coil L. In balanced conditions, the mean value of the voltage across the coil is zero. Fig. 4f shows the current flowing through the capacitor, which is the difference between IL and ILOAD. In balanced conditions, the mean current is equal to zero, and IC = IL. The current IC through the capacitor gives rise to the voltage ripple. This ripple consists of two components : a capacitive component, VC, and a resistive component, VESR, due to the ESR equivalent series resistance of the capacitor. Fig. 4g shows the capacitive component VC of the voltage ripple, which is the integral of a triangular-shaped current as a function of time. Moreover, it should be observed that vC (t) is in quadrature with iC(t) and therefore with the voltage VESR. The quantity of charge Q+ supplied to the capacitor is given by the area enclosed by the ABC triangle in Fig. 4f :
3/52
AN557 APPLICATION NOTE
Figure 4. Principal Circuit Waveforms of the figure 1 Circuit.
4/52
AN557 APPLICATION NOTE
1 T I L Q = -- -- ------22 2 Which therefore gives: I Q -V C = --- = ------L 8fc C Fig. 4h shows the voltage ripple VESR due to the resistive component of the capacitor. This component is VESR (t) = iC (t) × ESR. Fig. 4i shows the overall ripple Vo, which is the sum of the two previous components. As the frequency increases (> 20kHz), which is required to reduce both the cost and the sizes of L and C, the VESR component becomes dominant. Often it is necessary to use capacitors with greater capacitance (or more capacitors connected in parallel to limit the value of ESR within the required level. We will now examine the stepdown configuration in more detail, referring to fig. 1 and taking the be-haviour shown in Fig. 4 into account. Starting from the initial conditions, where Q = ON, vC = Vo and iL = iD = 0, using Kirckoff second principle we may write the following expression: Vi = vL + vC (Vsat is neglected against Vi). dIL dIL V i = L ------- + v C = L ------- + V o (1) dt dt which gives : dIL ( Vi V ) ------- = ------------------o-- (2) -dt L The current through the inductance is given by : (Vi V ) I L = ------------------o-- (3) -L When Vi, Vo, and L are constant, IL varies linearly with t. Therefore, it follows that : (V i V )TO N + -I L = ------------------o-------------- (4) L When Q is OFF the current through the coil has reached its maximum value, Ipeak and because it cannot very instantaneously, the voltage across the ased to allow the recirculation of the current through the load. When Q switches OFF, the following situation is present: vC(t) = Vo, iL (t) = iD (t) = Ipeak And the equation associated to the following loop may be written : dIL V F + L ------- + v C = 0 (5) dt where : v C = V o dIL ( VF + Vo ) ------- = ------------------------ (6) dt L It follows therefore that : V F + Vo i L ( t ) = ------------------- t (7) T
5/52
AN557 APPLICATION NOTE
The negative sign may be interpretated with the fact that the current is now decreasing. Assuming that VF may be neglected against Vo, during the OFF time the following behaviour occurs : Vo I L = ------ t (8) L therefore : Vo + I L = ------ T O F F (9) L But, because IL+ = IL if follows that : Vo TO F F ( Vi V ) TO N ------------------o-------------- = ---------------------L L which allows us to calculate Vo: TO N TO N V o = V i ------------------------- = V i ---------- (10) TO N TO F F T where T is the switching period. Expression (10) links the output voltage Vo to the input voltage Vi and to the duty cycle. The relation-ship between the currents is the following : TO N I i D C = I o D C ---------- (11) T
EFFICIENCY The system efficiency is expressed by the following formula : Po % = ------ 100 Pi where Po = VoIo (with Io = ILOAD) is the output power to the load and Pi is the input power absorbed by the system. Pi is given by Po, plus all the other system losses. The expression of the efficiency becomes therefore the following : P - = ------------------------------------------o------------------------------------- (12) P o + Ps a t + PD + PL + P q + p s w DC LOSSES Psat :saturation losses of the power transistor Q. These losses increase as Vi decreases. TON Vo P s a t = V s a t I o ---------- + V s a t I o ------ (13) T V
i
Vo TN --where ----O--- = ------ and Vsat is the power transistor saturation at current Io. T Vi PD : losses due to the recirculation diode. These losses increase as Vi increases, as in this case the ON time of the diode is greater.
Vi Vo Vo P D = V F I o ----------------- = V F I o 1 -----V V
i
(14)
i
6/52
AN557 APPLICATION NOTE
where VF is the forward voltage of the recirculation diode at current Io. PL : losses due to the series resistance RS of the coil PL = RS Io2 (15) Pq: losses due to the stand-by current and to the power driving current: Pq = Vi Iq, (16) in which Iq is the operating supply current at the operating switching frequency. Iq includes the oscillator current. SW ITCHIN G LOSSES Psw: switching losses of the power transistor : tr + tf P s w = V i I o -----------2T The switching losses of the recirculation diode are neglected (which are anyway negligible) as it is assumed that diode is used with recovery time much smaller than the rise time of the power transistor. We can neglect losses in the coil (it is assumed that IL is very small compared to Io) and in the output capacitor, which is assumed to show a low ESR. Calculation of the inductance value, L Calculation TON and TOFF through (4) and (9) respectively it follows that : I L L T O N = ----------------Vi V o
+
I L L T O F F = --------------Vo
-
But because : TON + TOFF = T and IL+ = IL = IL, it follows that : I L L I L L T O N = ----------------- + --------------- = T (17) V i Vo Vo Calculating L, the previous relation becomes : ( Vi Vo ) Vo L = ----------------------------- T (18) V i I L Fixing the current ripple in the coil required by the design (for instance 30% of Io), and introducing the frequency instead of the period, it follows that : ( V Vo ) Vo L = --------i-----------------------V i 0. 3 I o f where L is in Henry and f in Hz Vi × 0.3 × Io × f Calculation of the output capacitor C From the output node in fig. 3 it may be seen that the current through the output capacitor is given by: ic (t) = iL (t) Io
7/52
AN557 APPLICATION NOTE
Figure 5. Equivalent Circuit Showing Recirculation when Q1 is Turned Off.
From the behaviour shown in Fig. 4 it may be calculated that the charge current of the output capacitor, within a period, is IL/4, which is supplied for a time T/2. It follows therefore that : I L T I L T I V C = ------- -- = ----------- = ------L (19) -4C 2 8C 8fc but, remembering expression (4) : Vo ( Vi V ) TO N + -I L = ------------------o-------------- and T O N = ------ T Vi L therefore equation (19) becomes : ( Vi V ) V -- V C = ------------------o--------o 2 8 Vi f L C Finally, calculating C it follows that : ( Vi V ) Vo C = ----------------------o------------- (20) -2 8 V i V C f L where : L is in Henrys C is in Farads f is in Hz Finally, the following expression should be true : V m a x --E S R m a x = --------C---------- (21) I L It may happen that to satisfy relation (21) a capacitance value much greater than the value calculated through (20) must be used. TRANSIENT RESPONSE Sudden variations of the load current give rise to overvoltages and undervoltages on the output voltage. Since ic = C (dvc/dt) (22), where dvc = Vo, the instantaneous variation of the load current Io is supplied during the transient by the output capacitor. During the transient, also current through the coil tends to change its value. Moreover, the following is true : d iL v L = L ------- (23) dt where diL = Io vL = Vi Vo for a load increase for a load decrease vL = Vo
8/52
AN557 APPLICATION NOTE
Calculating dt from (22) and (23) and equalizing, it follows that : d iL d vC L ------- = C --------dt iC Calculating dvC and equalizing it to Vo, it follows that : L I o V o = --------------------------- (24) for + Io C ( V i Vo ) L I o V o = ------------- (25) for - Io C Vo From these two expressions the dependence of overshoots and undershoots on the L and C values may be observed. To minimize Vo it is therefore necessary to reduce the inductance value L and to increase the capacitance value C. Should other auxiliary functions be required in the circuit like reset or crowbar protections and very variable loads may be present, it is worthwhile to take special care for minimizing these overshoots, which could cause spurious operation of the crowbar, and the under-shoot, which could trigger the reset function. DEVICE DESCRIPTION For a better understanding of how the device functions, a description will be given of the principle blocks that compose the device. The block diagram of the device is shown in fig.6 POWER SUPPLY The device contains a stabilized regulator (Vstart = 12V) that provides power to the analogic and digital control blocks as well as the section of the bootstrap. The Vstart voltage also powers the blocks that operates the internal reference voltage of 5.1V, with a precision of 2%, necessary for the feedback. OSCILLATOR, SYNC. AND VOLTAGE FEED-FORWARD FUNCTIONS The oscillator block generates a sawtooh wave signal that sets the switching frequency of the system. This signal, compared with the output voltage of the error amplifier, generates the PWM signal that will then sent to the power output stage. The oscillator also contains the voltage feedforward function that, being completely integrated, does not require additional external components to function. The VFF function operates with supply voltages from 15V to 45V. The V/t of the sawtooh is directly proportional to the supply voltage Vi. As Vi increases, the conduction time (ton) of the power transistor decreases in such way as to provide to the coil, and therefore to the load, the product Volt x Sec constant. Figure 6. Block Diagram of the 10A Monolithic Regulator L4970A.
2 2
9/52
AN557 APPLICATION NOTE
Figure 7. Voltage Feeforward Waveform.
V2
Vi=30V Vi=15V Vc t
V7 Vi=30V Vi=15V t
D93IN006
Fig. 7 shows the duty-cycle varies as a result of the changes in slope of the ramp with the input voltage Vi. The output of the error amplifier should not change to maintain the output voltage in regulation. This function allows for the increase of speed in response to the rapid change of the supply voltage and for a greatly reduced ouput ripple at the mains frequency. In fact, the slope of the ramp is modulated by the ripple, generally present in the order of several volts on the input of the regulator, particularly when the solution with a mains transformer is used. Fig. 8 shows the simplified electrical diagram of the oscillator. A resistor, connected between the Rosc pin and GND, sets the current that is internally reflected in the pin Cosc, in order to charge the external capacitor to which it is connected. The voltage to the Rosc pin is not fixed, but is tied to the instantaneous value of Vi; this is needed to achieve the feedforward voltage function, in which the slope of the ramp is directly proportional to the supply voltage. A comparator senses the voltage at the Cosc capacitor. When the voltage reaches the value present at the inverting input of the comparator, the output from the comparator goes high and is sent to the two transistors Q1 and Q2. Q1 is responsible for discharging the external Cosc capacitor with a current of approx. 20mA, while Q2 imposes at the inverted input of the comparator a voltage of 2Vbe (approx. 1.3V) that is the low-threshold of the ramp. Some useful formulas for calculating the various parameters of the oscillator block are: Figure 8. Oscillator Circuit.
Vi 2R
1 Rosc
3
R
2R
Cosc PWM COMP.
+ CLOCK
Q1
R
Q2
D93IN007
10/52
AN557 APPLICATION NOTE
1) Oscillator charge current: Vi 9 V b e I C H A R G E = ------------------------ (For 15V < Vi < 45V) Ros c 2) Oscillator discharge current: IDISCH = 20mA 3) Peak voltage ramp: Vi 9Vb e V t h H = ------------------------ + 2 V b e Rosc This formula is obtained in the following way: indicating with Ve the voltage of the emitter of the NPN transistor connected to Vcc, and V- the voltage at the inverted input of the comparator, one has: V V e = ----i V b e (a) 3 V e 2 Vb e V = ------------------------- R + 2 V b e (b) 3R by substituting (a) into (b), one obtains: V ----i V b e 2 V b e Vi 9 Vb e 3 V = ---------------------------------------------- + 2 V b e = ------------------------ + 2 V b e 3 9 4) Valley voltage ramp: Vth-L = 2Vbe 5) Switching frequency: 9 f S W = ------------------------Ro s c C o s c It should be noted that formula (5) does not take into account the discharge time of Cosc which cannot be neglected when one is working at frequencies equal or higher than 200KHz. The discharge time is also tied to the value of Cosc itself. Analitycally one has: 6) Vt h H Vt h L T D I S C H = -------------------------------------- C o s c 20 m A
from which is obtained the more closely approximate expression of the oscillator frequency: 7) 1 f S W = -------------------------------------------------------R o s c Co s c ----------------------------- + T D I S C H 9
During the discharge time of Cosc, a clock pulse is generated internally that is made subsequently available on the Sync. pin and that can be used to synchronize other regulators. (3 devices of the same family maximum). The Sync. pulse generated has a typical range of 4.5V and the current availability is 4.5mA. In general, it is better that the Sync pulse is at least 300-400ns in order to be able to synchronize a range of existing regulators; to obtain this result, values of suggested capacitors, in different test circuits, have
11/52
AN557 APPLICATION NOTE
been selected. The typical duration of the synchronizing pulse with the suggested values of Cosc are as follows:
L497X Family (MULTIWATT PACKAGE) Cosc (nf) - Rosc = 16K 0.68 1 1.2 1.5 2.2 3.3 4.7 Sync (ns) 140 230 2 70 3 30 4 50 6 80 1100
L497X Family (POWERDIP PACKAGE) Cosc (nf) - Rosc = 30K 1.2 1.5 2.2 3.3 4.7 Sync (ns) 230 280 420 600 900
Obviously, synchronize pulses of eccessive duration can greatly reduce the max duty-cycle and produce distortions in the sawtooth of the synchronized regulator working as slave. P.W.M. Comparing the sawtooth signal generated by the oscillator and the output of the error amplifier, generates the PWM signal which is sent to the driver of the output power stage. The PWM signal, in the path towards the output stage, also encounters a latch block to prevent other pulses from being sent at same period to the output, possibly damaging the power stage. In the PWM block, a duty-cycle limiter has also been introduced. Such a limiter is obtained by taking advantage of the synchronizing pulse generated, the power output stage is inhibited. Even if the error amplifier gives a large signal to the peak of the ramp, the power stage will not be able to operate in DC, but will be switched off at each clock pulse. The max. obtainable duty-cycle is higher than 90%; this, however depends on the working frequency and the value of Cosc. Using the formulas 6) and 7) a precise calculation can be done. SOFT START The Soft Start function is essential for a correct startup of the device and for an output voltage that, at the sw itch on, increases in a monotonous mode without dangerous output overvoltages and without overstress for the power stage. Soft Start operates at the startup of the system and after an intervention of the thermal protection. Fig. 9 shows the simplified diagram of the startup functions. The function is carried out by means of an external capacitor connected to the Soft Start pin, which is charged with a constant current of about 100A to a value of around 7V. During the charging time, the output of the error transcon-ductance amplifier, because of Q1, is forced to increase at the same rising edge time of the external softstart capacitor Css.
12/52
AN557 APPLICATION NOTE
Figure 9. Soft Start Circuit.
Figure 10. Soft Start Waveforms.
CLAMPED ERROR AMPLIFIER OUTPUT Vc
t OUTPUT CURRENT t SOFT START TIME
D93IN011
The PWM signal begins to be generated as soon as the output voltage of the error amplifier crosses the ramp; at this point the output stage begins to commutate, slowly increasing its ON time (see fig. 10). The charge of the Css capacitor, as already mentioned, begins each time the device is supplied with power and after which an anomalous condition is created, as the intervention of thermal protection or of the undervoltage lockout. CALCULATING THE DUTY-CYCLE AND SOFT-START TIME Let us suppose that the discharge time of the oscillator capacitor, Cosc, is neglected. This is an approx. valid for switching frequencies up to 200KHz. Let us indicate with Vr the output voltage of the error amplifier, and with Vc the voltage of the oscillator ramp. Figure 11. Soft Sart Time Waveform.
13/52
AN557 APPLICATION NOTE
The PWM comparator block commutates when Vr = Vc. Therefore: 8) from which is obtained 9) V i 9 Vb e Vp p V r = V c = --------- t = ------------------------ t T 9T Vr T (V 9 V e) t = --------------------------i---------------b-----9
The time t obtained from this equation is equal to the ON time of the power transistor. The corresponding duty-cycle is given by: 10) Vr T (V 9V ) Vr ( V 9 V b e ) Vo t -----D = --o-n = --------------------------i---------------b-e-- = -----------------i---------------------- = -----T Vi 9T 9
Consequently, after leaving the discharged capacitor of Soft Start, the output of the regulator will reach its value when the voltage across the Css capacitor, charged with constant current, has reached the value Vr - 0.5V. The time necessary in order that the output rises from zero to the nominal value is given by: 11) ( V r 0.5 V ) t s t a r t u p = C s s ---------------------------I
ss
in which Css is the Soft Start capacitor and Iss the Soft Start current. Considering Soft Start time as tss, the required time for the Soft Start capacitor to change itself approx from (2Vbe - 0.5V) = (1.2V - 0.5V) to Vr - 0.5V, is: 12) By taking Vr from (10): 13) and substituting it in (12), we obtain: 14)
( V r 1. 2 V ) t s s = C s s ---------------------------Is s
Vo 9 V r = ------ -----------------------V i Vi 9 V b e
C s s Vo 9 t s s = --------- ------ ------------------------ 1.2 V I s s Vi Vi 9 Vb e
UNDERVOLTAGE LOCKOUT The device contains the protection block of under-voltage lockout which keeps the power stage turned-off as long as the supply voltage does not reach at least 12V. At this point the device starts up with Soft Start. The function of undervoltage is also provided with an hysteresis of 1V to make it better immune to the ripple present on the supply voltage. ERR OR AMPLIFIER The error amplifier is a transconductance type and deliver an output current proportional to the voltage inbalance of the two inputs. The simplified diagram is presented in fig 12.The principal characteristics of this uncompensated operational amplifier are the following: Gm = 4mA/V, Ro = 2.5Mohm, Avo = 80dB, Isourcesink = 200A, Input Bias Current = 0.3A. The frequency response of the op. amp. is given in fig. 13. Ignoring the high frequency response and hypothesizing that the second pole is below the 0 dB axis in the all the conditions of loop compensation, it is possible to make a first approximation with the equivalent circuit of fig. 14
14/52
AN557 APPLICATION NOTE
Figure 12. Error Amplifier Circuit.
Figure 13. Open loop gain (error amplifier only)
Figure 14. Error amplifier equivalent circuit.
In which: 15)
Rc A v ( s ) = G m --------------------------- where Co = 3pF 1 + s R o Co
The error amplifier can be easily compensated thanks to the high output impedance (see fig. 14) The resulting transfer function is as in the following: (16) R o ( 1 + s Rc Cc ) A v ( s ) = G m --------------------------------------------------------------------------------------------------------------------2 s Ro C o R c Cc + s ( Ro C c + R o Co + R c C c ) + 1
15/52
AN557 APPLICATION NOTE
Figure 15. Compensation network of the error amplifier
The Bode diagram is shown in fig.16. Figure 16. Bode plot showing gain and phase of compensated error amplifier
The compensation circuit introduces a pole at low frequency and a zero that is generally calculated to be put in the proximity of the resonance frequency of the output LC filter. The second pole at high frequency generally falls in a zone of no interest (for the system stability, one must consider the zero introduced by ESR characteristic of the output capacitor. Not all the designers agree on this solution). If necessary, however, one can turn to more sophisticated compensation circuitry. An example is shown in fig. 17. Figure 17. One pole, two zero compensation network
Such a circuit introduces a pole at low-frequency and two zeros. 17 1 Z 1 = ----------------------------2 R1 C 1 1 Z2 = ----------------------------2 R2 C2
16/52
AN557 APPLICATION NOTE
It must be remembered, however, that because of the high output impedance of the error amplifier, a second pole is also present: 18) P 2 = ----G------------ m 2 C1
We normally suggest a high value for R1 to reduce the value of the capacitor C1 and allocate the pole P2 at the highest possible frequency. The essential limitation to the max value of R1 is the offset introduced by the input bias current of the error amplifier. In the case of output voltage regulated higher than 5.1V, an external divider should be introduced. It's than possible to introduce a second zero using the following network: Figure 18. Compensation network for output voltages higher than 5.1V
Two zeros and two poles are introduced: 19) 1 Z 1 = --------------------------2 Ro Cc 1 P 1 = --------------------------2 R o Cc R1 R2 Where R x = --------------------R1 + R2 1 Z2 = ----------------------------2 R 1 C1 1 P2 = ---------------------------2 Rx C1
APPLICATION EXAMPLE Consider the block diagram of fig. 19, representing the internal control loop section, with the application values: Fswitch = 200KHz, L = 100H, C = 1000F, Po = 50W, Vo = 5.1V, Io = 10A and Fo = 500Hz. Gloop = PWM × Filter Figure 19. Block diagram used in stability calculation
17/52
AN557 APPLICATION NOTE
Figure 20. Frequency behaviour of the circuit of fig. 19
The system requires that DC gain is maximum to achieve good accuracy and line rejection. Beyond this a bandwidth of some KHz is usually required for a good load transient response. The error amplifier transfer function must guarantee the above constrainst. A compensation network that could be used is shown in fig. 21. ( 1 + s R 1 C1 ) ( 1 + s R 2 C2 ) A ( s ) = --------------------------------------------------------------------C1 s R 1 C1 (1+s --------Gm Figure 21. Compensation network.
Figure 22. Bode plot of the regulation loop with the compensation network of fig. 21.
dB
ACSJ 40
Gloop
PWM+FILTER 20
50Hz
500Hz
5Kz
50KHz
D93IN012
18/52
AN557 APPLICATION NOTE
The criterium is to define Z1, Z2 close to the resonant pole of the output LC filter. The Gm/2C1 pole must be placed at a frequency at which open loop gain is below 0dB axis (fig. 22). CURRENT LIMITING A complete regulation system will be equipped with a good current limiter able to protect from load breaking and operator error controlls. The current limiting function is totally integrated and does not require any external component. The output current is sensed by an internal low-value resistor, in series with the drain of the DMOS vertical power transistor.. A precision current limitation of 10% relative at the peak current is guaranted. During overcurrent situation the pulse by pulse current limitation produce an output stage switching frequency reduction. The block diagram of the current limiting is shown in fig. 23. Figure 23. Current protection circuit.
In overcurrent situation the comparator send a signal at the flip-flop set input, an inhibit pulse is immediatly generated from it and sended at the output stage switching off the power mos. A reset pulse input in generated from an 40KHz internal oscillator. After the first reset pulse the control loop will start to regulate the system an the output current will increase following the principal oscillator frequency. If overcurrent condition is still present the current limiting will be activate again. This type of current limiting ensure a constant output current in overload or short circuit condition and allow a good reliability at high frequency (500KHz) reducing the problems relative at the internal signal delay through the protection blocks. The inductor current in overload condition in shown in fig. 24. Figure 24. Overload inductance current.
19/52
AN557 APPLICATION NOTE
The 40KHz internal oscillator is synchronized with the principal one. If the system work with a oscillator tracks the principal oscillator frequency. In this way the switching frequency will not increase in overload situation. A particular care has to be taken in the inductor value in order to avoid problems during overload or short circuit conditions. A critical situation is present with high switching frequency, (more than 200KHz) where a small inductor value is used and with high capacitive load. In order to return in nominal condition after a short circuit the inductor ripple at 40KHz with the nominal output voltage and current has to be lower than the current limitation value. Example Let us consider L4970A, 10A. (the same approach can be used for all the family). The inductor ripple current is given by the following formula: (Vi V ) V -I L = ------------------o------------o Vi fs w L where fsw = 40KHz 10% In order to get the maximum inductor ripple current, the previous formula becomes: ( Vi a x Vo m a x ) Vo m a x --I L = --------m----------------------------------------------------Vi m a x fs w m i n L The current limitation for L4970A will start to work at 13A. therefore: I L I l i m min > I o n o m + ------2 where Ionom = 10A for L4970A. POWER FAIL-RESET CIRCUIT The L4970A include a voltage sensing circuit that may be used to generate a power on power off reset signal for a microprocessor system. The circuit senses the input supply voltage and the output generated voltage and will generate the required reset signal only when both the sensed voltages have reached the required value for correct system operation. The Reset signal is generated after a delay time programmable by an external capacitor on the delay pin. Fig 25 shows the circuit implementation of Reset circuit. The supply voltage is sensed on an external pin, for programmability of the threshold, by a first comparator. The second comparator has the reference threshold set at slightly less the ref. voltage for the regulation circuit and the other input connected internally at the feedback point on the regulated voltage. When both the supply voltage and the regulated voltage are in the correct range, transistor Q1 turns off and allows the current generator to charge the delay capacitor discharges completely before initialization of a new Reset cycle. The output gate assures immediate take of reset signal without waiting for complete discharge of delay capacitor. Reset output is an open collector transistor capable of sinking 20mA at 200mV voltage. Fig 26 shows reset waveforms.
20/52
AN557 APPLICATION NOTE
Figure 25. Power fail and reset circuit.
Figure 26. Reset and power fail and reset circuit.
Vi RISING P.FAIL THRESHOLD TURN-ON THRESHOLD FALLING P.FAIL THRESHOLD TURN-OFF THRESHOLD 10V t
11V
t Vo=5.1V RISING RESET THRESHOLD 5.1V 5V 4.9V 100mV HISTERESIS t
FALLING RESET THRESHOLD OUTPUT RESET
t tDR DELAY RESET tDR POWER FAIL TIME
D93IN013
Figure 27. Power stage circuit.
21/52
AN557 APPLICATION NOTE
POWER STAGE The simplified diagram of the output stage is shown in the fig. 27. The power stage and the circuit connected with it are by far the most important and critical components when one wants to obtain good performance at high switching frequency. The power transistor must have excellent characteristics from the point of view of both the switching speed and the robustness. The transistor DMOS, with its intrinsic characteristics of elevated speed, no second breakdown phenomenom and easy driving proves to be particularly suitable for this type of application that normally works at high frequency. For a properly driving of the DMOS gate it is necessary to use an external bootstrap capacitor. When the voltage Vs is low the Cboot capacitor is charged through the internal diode D1, at the value of voltage equal to that of Vstart, which is about 12V; the next step oversees that Q3 is turned off, Q2 is driven in gate by Q1 so that Q1 can go in saturation, and its source can go up rise towards Vi. Cboot maintains its charge and guarantees a voltage equal Vi+12V at the gate of Q7, so that can enter into region of low resistance. At this point the diode D1 turns on to be inversely polarized, disconnecting the 12V section from that of the driving power stage. When Q2 is ON the driven current of the power stage requires from the bootstrap capacitor a typical current of 400uA. When Q2 is Off a current of 2.5mA is required to mantain Q2 in that state. This current however is not delivered from the bootstrap capacitor, but rather from the internal regulator of 12V, while the output current flowing in the freewheeling diode. The circuit described is capable of obtaining commutation, rise and fall time, a typical value of 50ns. In principle, it would have been feasible to reduce furthermore the commutation time whithout any reliability problems. This was not believed to be advantageous since it would not have been of any benefit if one thinks of the trr time of the catch diode (with trise of 50ns also the Schottky diodes begin to show limitations) and of the conseguent increase of different disturbances caused bt too higly elevated dI/dt. The following table shows the main features of the DMOS transistor. Figure 28. Gate-charge curve for the power
Table 1. BVDSS > 60V R DS(ON) = 100m R DS(ON) = 150m VTH = 3V
22/52
at ID = 1mA at ID = 10A at ID = 10A at ID = 1mA Tj = 25C Tj = 150C
VGS = 0V VGS = 10V VGS = 10V
AN557 APPLICATION NOTE
THERMAL SHUTDOWN The thermal protection intervenes when the junction temperature reaches 150C; it intervenes directly on the output stage turning it off quikly and in the meantime discharging the soft start capacitor. The reference voltage and the oscillator will continue to work regularly. The thermal shutdown has a hysteresis, after its intervention, it is necessary to wait for the junction temperature to lower around 30C before the device will begin to work properly again. The device restart to work by using the soft start function. Table 2. High Current Switching Regulator ICs.
L497X FAMILY Parameter Max. Input Operating Voltage Output Voltage Range Max. Output Current Power Switch RDSON at 25C Switching Mode Control System Max. Switching Freq. Efficiency VINPUT = 35V VOUT = 5.1V Current Limiting Soft Start Reset and Power Fail Synch Crowbar Package Max. Rth j-case (pin) Rth j-amb Multiwatt15 1C/W 35C/W Multiwatt15 1C/W 35C/W Multiwatt15 1C/W 35C/W 10A 7A L4970A 50V L4977A 50V L4975A 50V L4974A 50V L4972A 50V L4972AD Surf. Mount. 50V
5.1V (2%) to 40V 5A 0.13 typ. Continuous Mode, Direct Duty Cycle Control with Voltage Feed-Forward 500KHz 10A 80% at 200KHz 500KHz 7A 80% at 200KHz 500KHz 5A 85% at 200KHz Yes Yes Yes No Powerdip 16+2+2 12C/W 60C/W Powerdip 16+2+2 12C/W 60C/W SO20L 6C/W 80C/W 200KHz 3.5A 8 5% at 100KHz 200KHz 2A 85% at 100KHz 200KHz 2A 85% at 100KHz 3.5A 2A 2A
Constant Current
APPLICATIONS Even though the regulators of the L4970A family has been designed to work only in step down configuration we will see next how these regulators can be use in large range of applications. In same cases the L4970A device will be used as an example for the entire family assembled in Multiwatt package and the L4974A will be used for the types in powerdip package. Anyway the suggested applications can be extended to any other device of the family by adjusting if necessary the external components using the given equation for the calculation. Typical Application The Fig. 29 shows the electrical diagram of the typical application, complete with all the auxiliary functions. The same application suggested in the data sheet as test circuit and is the same used for the final dynamic test. All our devices are 100% tested both in static and dynamic conditions. Included in the dynamic test are obviously the external components: the coil, catch diode and output capacitor which have been defined for all regulators. Shown below are the electrical diagrams of 5 devices that compose the family of this regulator complete
23/52
AN557 APPLICATION NOTE
with the value of the external components and with the relative pcb layout. Output voltages higher than 5.1V are possible using an output resistive divider. For Vo > 24V, for safety reasons it must be avoided the zero load condition. In the application with high current, connected to the output divider are added two other resistances that permit the separation of sensing and forcing, in such way as to compensate the fall of voltage on the connecting cables between the output and the load. Connecting directly the output to the feedback pin a 5.1V 2% is obtained. The following table can be help for a rapid calculation of a resistor divider to obtain some of the most standard output voltage. Figure 29. L4970A Typical Application Circuit.
Figure 30. Test and Evaluation Board Circuit
TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 10A ; fSW = 200KHz) Vo RIPPLE = 30mV (at 10A) with output filter capacitor ESR 60m Line regulation = 5mV (Vi = 15 to 50V) Load regulation = 15mV (I o = 2 to 10A) For component values, refer to test circuit part list.
24/52
AN557 APPLICATION NOTE
PAR TS LIST
R1 = 30K R2 = 10K R3 = 15K R4 = 16K R5 = 22 0,5W R6 = 4K7 R7 = 10 R8 = see tab. A R9 = OPTION R10 = 4K7 R11 = 10 D1 = MBR 1560CT (or 16A/60V or equivalent) L1 = 40H core 58071 MAGNETICS 27 TURNS Ø 1,3mm (AWG 16) COGEMA 949178 C9 = 2.2nF KP1830 C10 = 220nF MKT C11 = 2.2nF MP1830 **C12, C13, C14 = 220F 40VL EKR C15 = 1F Film * C1, C2 = 3300F 63VL EYF (ROE) C3, C4, C5, C6 = 2.2F C7 = 390pF Film C8 = 22nF MKT 1817 (ERO)
* 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR
Table A
V0 12V 15V 18V 24V R10 4.7K 4.7K 4.7K 4.7K R8 6.2K 9.1K 12K 18K
Table B SUGGESTED BOOTSTRAP CAPACITORS
Operating Frequency f = 20KHz f = 50KHz f = 100KHz f = 200KHz f = 500KHz Bootstrap Cap.c10 680nF 470nF 330nF 220nF 100nF
25/52
AN557 APPLICATION NOTE
Figure 31. P.C. Board (component side) and Components Layout of the Circuit of Fig. 30.
Figure 32. P.C. Board (back side) and Components Layout of the Circuit of Fig. 30.
26/52
AN557 APPLICATION NOTE
Figure 33. Test and Evaluation Board Circuit.
TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 2A ; fsw = 100KHz); Vo RIPPLE = 30mV (at 1A); Line regulation = 12mV (Vi = 15 to 50V); Load regulation = 7mV (Io = 0.5 to 2A); for component values Refer to the fig. 32 (Part list). PAR TS LIST
R1 = 30K R2 = 10K R3 = 15K R4 = 30K R5 = 22 R6 = 4K7 R7 = see tab. A R8 = OPTION * C1, C2 = 1000F 63V EYF (ROE) C3, C4, C5, C6 = 2.2F 50V C7 = 390pF Film C8 = 22nF MKT 1837 (ERO) C9 = 2.7nF KP1830 (ERO) C10 = 0.33F Film C11 = 1nF **C12, C13, C14 = 100F 40VL EKR (ROE) C15 = 1F Film D1 = SB 560 (or equivalent)
L1 = 150H core 58310 MAGNETICS 45 TURNS 0.91mm (AWG 16) COGEMA 949181
* 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR
Table A
V0 12V 15V 18V 24V R10 4.7K 4.7K 4.7K 4.7K R8 6.2K 9.1K 12K 18K
Note: In the Test and Application Circuit for L4972D are not mounted C2, C14 and R8.
Table B - SUGGESTED BOOTSTRAP CAPACITORS
Operating Frequency f = 20KHz f = 50KHz f = 100KHz f = 200KHz f = 500KHz Bootstrap Cap.c10 680nF 470nF 330nF 220nF 100nF
27/52
AN557 APPLICATION NOTE
Figure 34. Component Layout of fig. 33. Evaluation Board
Figure 35. Board and Component Layout of the ciruit of fig. 33.
28/52
AN557 APPLICATION NOTE
Figure 36. Test and Evaluation Board Circuit.
TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 3.5A ; fsw = 100KHz); Vo RIPPLE = 30mV (at 1A); Line regulation = 12mV (Vi = 15 to 50V); Load regulation = 7mV (Io = 0.5 to 3.5A); for component values Refer to the fig. 35 (Part list). PARTS LIST
R1 = 30K R2 = 10K R3 = 15K R4 = 30K R5 = 22 R6 = 4K7 R7 = see tab. A R8 = OPTION * C1, C2 = 1000F 63V EYF (ROE) C3, C4, C5, C6 = 2.2F 50V C7 = 390pF Film C8 = 22nF MKT 1837 (ERO) C9 = 2.7nF KP1830 (ERO) C10 = 0.33F Film C11 = 1nF **C12, C13, C14 = 100F 40VL EKR (ROE) C15 = 1F Film D1 = SB 560 (or equivalent)
L1 = 150H core 58310 MAGNETICS 45 TURNS 0.91mm (AWG 16) COGEMA 949181
* 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR
Table A
V0 12V 15V 18V 24V R10 4.7K 4.7K 4.7K 4.7K R8 6.2K 9.1K 12K 18K
Note: In the Test and Application Circuit for L4974D are not mounted C2, C14 and R8.
Table B - SUGGESTED BOOTSTRAP CAPACITORS
Operating Frequency f = 20KHz f = 50KHz f = 100KHz f = 200KHz f = 500KHz Bootstrap Cap.c10 680nF 470nF 330nF 220nF 100nF
29/52
AN557 APPLICATION NOTE
Figure 37. Component Layout of fig. 36. Evaluation Board
Figure 38. Board and Component Layout of the ciruit of fig. 36.
30/52
AN557 APPLICATION NOTE
Figure 39. Test and Evaluation Board Circuit
TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 5A ; fSW = 200KHz); Vo RIPPLE = 30mV (at 10A) with output filter capacitor ESR 60m; Line regulation = 5mV (Vi = 15 to 50V); Load regulation = 15mV (Io = 2 to 5A); For component values, refer to test circuit part list. PAR TS LIST
R1 = 30K R2 = 10K R3 = 15K R4 = 16K R5 = 22 0,5W R6 = 4K7 R7 = 10 R8 = see tab. A R9 = OPTION R10 = 4K7 L1 = 80H R11 = 10 * C1, C2 = 3300F 63VL EYF (ROE) C3, C4, C5, C6 = 2.2F C7 = 390pF Film C8 = 22nF MKT 1817 (ERO) C9 = 2.2nF KP1830 C10 = 220nF MKT C11 = 2.2nF MP1830 **C12, C13, C14 = 220F 40VL EKR C15 = 1F Film core 58930 MAGNETICS 47 TURNS Ø 1,13mm (AWG 76) COGEMA 949178
D1 = MBR 760CT (or 7.5A/60V or equivalent)
* 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR
Table A
V0 12V 15V 18V 24V R10 4.7K 4.7K 4.7K 4.7K R8 6.2K 9.1K 12K 18K Bootstrap Cap.c10 680nF 470nF 330nF 220nF 100nF
Table B - SUGGESTED BOOTSTRAP CAPACITORS
Operating Frequency f = 20KHz f = 50KHz f = 100KHz f = 200KHz f = 500KHz
31/52
AN557 APPLICATION NOTE
Figure 40. P.C. Board (component side) and Components Layout of the Circuit of Fig. 39.
Figure 41. P.C. Board (back side) and Components Layout of the Circuit of Fig. 39.
32/52
AN557 APPLICATION NOTE
Figure 42. Test and Evaluation Board Circuit
TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 7A ; fSW = 200KHz); Vo RIPPLE = 30mV (at 7A) with output filter capacitor ESR 60m; Line regulation = 5mV (Vi = 15 to 50V); Load regulation = 15mV (Io = 2 to 7A); For component values, refer to test circuit part list. PARTS LIST
R1 = 30K R2 = 10K R3 = 15K R4 = 16K R5 = 22 0,5W R6 = 4K7 R7 = 10 R8 = see tab. A R9 = OPTION R10 = 4K7 L1 = 40H R11 = 10 * C1, C2 = 3300F 63VL EYF (ROE) C3, C4, C5, C6 = 2.2F C7 = 390pF Film C8 = 22nF MKT 1817 (ERO) C9 = 2.2nF KP1830 C10 = 220nF MKT C11 = 2.2nF MP1830 **C12, C13, C14 = 220F 40VL EKR C15 = 1F Film core 58071 MAGNETICS 27 TURNS Ø 1,3mm (AWG 16) COGEMA 949178
D1 = MBR 1560CT (or 16A/60V or equivalent)
* 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR
Table A
V0 12V 15V 18V 24V R10 4.7K 4.7K 4.7K 4.7K R8 6.2K 9.1K 12K 18K Bootstrap Cap.c10 680nF 470nF 330nF 220nF 100nF
Table B - SUGGESTED BOOTSTRAP CAPACITORS
Operating Frequency f = 20KHz f = 50KHz f = 100KHz f = 200KHz f = 500KHz
33/52
AN557 APPLICATION NOTE
Figure 43. P.C. Board (component side) and Components Layout of the Circuit of Fig. 42.
Figure 44. P.C. Board (back side) and Components Layout of the Circuit of Fig. 42.
34/52
AN557 APPLICATION NOTE
Resistors value for standard output voltages.
Vo (V) 12 15 18 24 Rx (k) 4.7 4.7 4.7 4.7 Ry (k) 6.2 9.1 12 18
Figure 46. Oscillator waveform and sync. pulse for Vi = 15V
Rx corresponds to R9 for L4974A and L4972A Ry corresponds to R10 for L4970A, L4977A and L4975A Rx corresponds to R7 for L4974A and L4972A Ry corresponds to R8 for L4970A, L4977A and L4975A The suggested switching frequency, and used in the dynamic tests, is 200KHz for the Multiwatt package (MW) and 100KHz for the powerdip plastic package (PDIP). The maximum switching frequency allowed is 500KHz. For the types in plastic package (Powerdip), the lower switching frequency suggested is only depended by the minor dissipating power of a plastic package versus a "power package" because it is well known that switching losses are directly proportional to the commutation frequency. Higher sw itching frequencies are possible if limited output current is required and the operating ambient temperature are lower than 70C. Infact the oscillator of the devices assembled in dual in line is completely equivalent to Multiwatt package. The most important external components which need a little more attention (because a properly dimensioning affects on the performance of the application) are the input and output capacitors, the freewheeling diode and the coil. Figure 45. Oscillator waveform and sync. pulse for Vi = 35V
Figure 47. Oscilloscope photograph showing the short circuit output voltage and current waveforms.
INPUT OUTPUT CAPACITORS The output voltage ripple Vo, essentially depends on the current ripple in the coil and the ESR of the output capacitor at the switching frequency. The capacitor that present a low ESR are capable of supporting higher current ripples. Today, the majority of the constructors of elec-trolithic capacitors offer in their data book also a wide range of "low ESR" types generally suggested for switching power supply application. In our case EKR and EKE series (ROE) has been preferred. Such a series capacitors are designed for applications at high frequency, 200KHz, and built to have a low ESR in order of supporting high current ripple. In order to minimize the effects caused by the ESR of the capacitors on the output voltage ripple 3 capacitors of 220uF/40V (for high output current application) are connected in parallel.
35/52
AN557 APPLICATION NOTE
It is necessary much attention also into the choice input capacitors. Also them be at low ESR, because they must sustain high current ripples. Such current ripples in presents of an inadeguate ESR, would produce a heating of the capacitor itself (which could affect on the reliability of the component, since in general it is sensitive to temperature. Therefore choosing input capacitor at low ESR is necessary for problems of reliability. In fact such capacitors, when used in applications that make use a mains transformer, must support quite elevated peak current for short periods a double the mains frequency and the same time be capable to deliver the instantaneous peak of energy to the load at the switching frequency. Some other considerations of a general nature can be done on low ESR capacitors. For example of equal value and type (i.e.: 220F - EKR), the ESR of the capacitor decreases at the increasing of its value voltage rating, just like its RMS current. Still, two capacitors of the same value, connected in parallel, withstand an RMS current higher then the only one of double value, and with the same voltage rating. When however, more capacitors are connected together in parallel, it is important to design with care the layout of the printed circuit, in order to distribute as eventy as possible amongst between the different capacitors the total current ripple. This is used to avoid dangerous current unbalances in the distribution of the total current between the various capacitors charging some more others, that could damage the reliability of the system. Often it is very difficult to know exactly the RMS current flowing throught the capacitors. To know if the operating condition is a "safe"operating condition or not, a measurement of the package temperature of the capacitor should be done. The following table 3 and 4, included in the dat-abook of electrical Roederstain, shows the maximum RMS current sustainable by the EKR and EKE capacitor versus the ambient temeperature and overtemperature allow ed on the capacitor package. Table 3. Low-voltage electrolytic capacitors for switch-mode power supplies with low impedance values, radial, polarized styles
Dimensions D x L (mm) (nominal dimensions) Dissipation factor tan (100Hz; 20C) Lim. Values Impedance Z () (10KHz; 20C) (Lim. values) Impedance Z () (10KHz; 20C) (Lim. values) Admissible ripple curr. (mA/100Hz) 85C Admissible ripple curr. (mA/eff/10100Hz) 85C
Rated cap. (F)
Rated volt. (V DC)
E KR 100 220 470 100 220 470 100 220 470 100 220 470 10 10 10 16 16 16 25 25 25 40 40 40 8.7 x 12.7 10 x 12.7 10 x 20 10 x 12.7 10 x 16 12.5 x 20 10 x 12.7 10 x 16 12.5 x 20 10 x 16 12.5 x 20 12.5 x 30 0.12 0.12 0.12 0.11 0.11 0.11 0.09 0.09 0.09 0.08 0.08 0.08 0.85 0.39 0.20 0.60 0.32 0.16 0.5 0.25 0.13 0.4 0.17 0.09 0.65 0.31 0.18 0.40 0.25 0.13 0.35 0.17 0.09 0.23 0.13 0.08 160 300 530 200 350 600 250 450 650 450 650 1000 250 450 800 300 550 900 400 700 1000 700 1000 1500
36/52
AN557 APPLICATION NOTE
Table 3. Low-voltage electrolytic capacitors for switch-mode power supplies with low impedance values, radial, polarized styles (continued)
Dimensions D x L (mm) (nominal dimensions) Dissipation factor tan (100Hz; 20C) Lim. Values Impedance Z () (100KHz; 20C) (Lim. values) Impedance Z () (100KHz; -10C) (Lim. values) Impedance Z () (100KHz; -40C) (Lim. values) Admissible ripple curr. (mA)100Hz) 105C
Rated cap. (F)
Rated volt. (V)
E KE 22 33 47 100 220 330 330 470 100 220 220 330 470 100 220 330 470 100 100 220 330 470 10 10 10 10 10 10 10 10 16 16 16 16 16 25 25 25 25 35 35 35 35 35 5 x 11 5 x 11 5 x 11 5 x 11 6.3 x 11 8 x 11.5 8.5 x 12.5 8 x 11.5 6.3 x 11 8 x 11.5 8.5 x 12.5 8 x 11.5 10 x 12.5 6.3 x 11 8 x 11.5 10 x 12.5 10 x 16 8 x 11.5 8.5 x 12.5 10 x 12.5 10 x 16 10 x 20 0.19 0.19 0.19 0.19 0.19 0.19 0.19 0.19 0.16 0.16 0.16 0.16 0.16 0.14 0.14 0.14 0.14 0.12 0.12 0.12 0.12 0.12 1.30 1.30 1.30 1.30 0.60 0.33 0.33 0.33 0.60 0.33 0.33 0.33 0.25 0.60 0.33 0.25 0.19 0.33 0.33 0.25 0.19 0.14 3.90 3.90 3.90 3.90 1.80 0.99 0.99 0.99 1.80 0.99 0.99 0.99 0.75 1.80 0.99 0.75 0.57 0.99 0.99 0.75 0.57 0.42 20 20 20 20 9.80 5.80 5.80 5.80 9.80 5.80 5.80 5.80 3.20 9.80 5.80 3.20 2.20 5.80 5.80 3.20 2.20 1.50 154 154 154 1 54 260 400 400 400 260 400 400 400 510 260 400 510 635 400 400 510 635 860
Table 4. Admissible ripple current
Ambient Temp. u in ×C 40 45 50 55 60 65 70 75 80 85 90 95 100 105 Admissible % of the 85C value 220 % 210 % 200 % 190 % 180 % 170 % 155 % 140 % 120 % 100 % 90 % 80 % 70 % 60 % Surface Temp. in C 55 59 63 67 70 74 77 81 84 88 92 97 101 106 Admissible % of the 105C value 230 % 220 % 210 % 200 % 190 % 180 % 170 % 160 % 150 % 140 % 130 % 120 % 110 % 100 % Surface Temp. in C 55 60 64 68 72 76 80 84 88 92 96 100 104 108
37/52
AN557 APPLICATION NOTE
CATCH DIODE Because of quickly rise and fall time of the current (about 40-50ns) the use Schottky diode is reccomanded. Ultra-fast diodes with 30-50ns of trr (reverse recovery time) are not considered sufficiently fast for this family of converters, since they would give too elevated peaks of current at the turn on of the internal power transistor, so high thatcould affect the reliability of the complete system, as well as drastically reduce the efficiency. The oscilloscope photographs show the Output Voltage and Output Current waveforms obtained with diode having different trr value. Figure 48. Schottky Diode. support a max. input power voltage of 55V (for specific applications, Schottky diodes with a reverse breakdown voltage higher or equal to the maximum supply voltage should be used), with current rating and packaging to satisfy all the conditions of duty cycle, and therefore also of power dissipation. C OI L Concerning the coil, a molypermalloy toroidal cores has been suggested, so that it would be easy for everybody to obtain samples, wrap them with a right number of turns in order to evaluate and correlate the measurements and performance of the devices. In addition since the devices are dynamically tested 100% in production, with a "jig" of testing which uses the same coil suggested in the applications, in the case of contests for example on a guaranteed parameter like the efficiency, should be easier to solve the objections; in this case should be remembered that changing the magnetic material, the dimension, the wire and the number of the winding, also change the losses in the coil reducing the total efficiency of the application. This can be easily verify using for example toroidal cores in iron powered rather that those suggested in molypermalloy. Moreover, it is important to dimension properly the coil in order to avoid its saturation, a good choice is to dimension that its saturation; current is not equal to the maximum nominal current capable to deliver to the load, but rather higher by about 20% then the maximum guaranted current of the device, in short circuit condition. Only in this way it is possible to guarantee that the coil never saturate in all the possible working conditions, i.e.: in presence of a load transient, in short circuit in output and in the case of elevated temperature of the magnetic part. At last, it should be remembered that the suggested inductors values, are referred to the inductors values that the coil must have at the maximum output current of the application. Oscilloscope Photographs showing the device output voltage and current waveforms obtained with different inductor.
Figure 49. Ultra Fast Diode (trr < 100ns).
In the test circuits used for this family of converters, Schottky diodes from 60V (breakdown reverse voltage) are suggested since the device can
38/52
AN557 APPLICATION NOTE
Figure 50. Waveforms for L = 50H Anyway some general rules should be observed in order to avoid any "poor functioning". These rules include: a) the catch diode, that further to be the suggested type in the test circuit, it has to be assembled on the printed circuit very close to the output of the regulator, in order to minimize the leakage inductance and avoid over voltage due to the long connection: b) The inductor, avoiding the saturation at the maximum current guaranted by the current limitation of the device. If oscillations on the output voltage at low ambient temperature (i.e.: below 0C) are originated an output low ESR capacitor has to be used. Oscillations on the output al low frequency indicate instability of the control loop; in this case a changing of the network compensation is suggested (see Error Amplifier section). LOW COST APPLICATION The fig. 53 shows the low cost application of a power supply of 10A and 5.1V. In comparison of the complete application (and this is valid for all the devices of the family) the external components relative to the reset and power fail functions can be missed. When a lower output voltage ripple is not required it is possible to eliminate the capacitors connected at the reference voltage pin of 5.1V (i.e.: pin 14 for Multiwatt package. pin 13 for plastic package) The reset input pin is suggested to connect it to ground. The soft start capacitor value can be reduced to 100nF for 5V output voltage.
Figure 51. Waveforms for L = 230H
Figure 52. Waveforms in case of core saturation
39/52
AN557 APPLICATION NOTE
Figure 53. Low Cost Application Circuit.
POWER SUPPLY COMPLETE WITH MAINS TRANSFORMER The fig. 54 shown a power supply with mains 110/220Vac transformer, diode bridge and filter capacitor with output voltage adjustable between 5.1V. and 24V. Output capacitors have to be chosen with low ESR in order to reduce the output ripple.Particular care has to be taken for input filter capacitors, in fact they have to support high current spikes at mains frequency and at the same time current peak bigger than the output current at the switching frequency. Therefore they must be chosen with low ESR and able to substain high current ripple in order to guarantee a good reliability to all the system. The trasformer can be chosen with a single winding and 4 diodes or a center tap with only 2 diodes with higher reverse voltage. A cost reduction of the trasformer can be reached using an active power factor corrector. It work at low voltage and the external components are relatively cheap, more details can be obtained looking on the power factor corrector application note. POWER SUPPLY WITH MAINS HIGH FREQUENCY PREREGULATOR. When it is necessary to eliminate the mains trasformer at 50/60Hz for reasons like weight, dimensions or cost, a high frequency preregulator can be used. A ferrite trasformer reduces the rectifier and filtered mains voltage in a convenient voltage to supply directly the device, providing for the isolation requirements. Using a free running solution or one of the voltage/current mode controller available, it is possible to compensate the input variation while the output voltage variations due to the load are usually very low. Some examples regarding how to use this regulator in off-line power supply are now showed: Flyback Topology Using a flyback topology with single or double transistors is possible to fix a single output voltage of 3540V; it can be a bit increased if using a backup battery of 48 nominal Volts. From this preregulator (10%) tolerancevoltage is possible to get one or more indipendent outputs, with its own current limitation and thermal protection. Moreover a possibility to syncronize more devices together is available, remembering to fix the master frequency at least 5% higher than the others device (working as slave) one. In case of necessity is possible to synronize devices on the trasformer secondary with the swith-cing frequency of the controller (See Fig. 55).
40/52
AN557 APPLICATION NOTE
Figure 54. Typical power supply showing the mains transformer.
Figure 55.
Forward Topology Further is showed an smps forward circuit, where the dc-dc converter is used as post-regulator for an auxiliary output, (35V.) while the main one (5.1V. or 3.3V) is controlled directly with the feedback (See Fig. 56). Using a PFC preregulation When an optimized power factor is required it is possible to use the following two pricinple diagram that make use of an active power factor corrector. 1) using the standard boost topology (Fig. 57) 2) using a flyback topology (Fig. 58) The idea is that to generate a stabilized voltage, around 30V - 35V, already isolated, avoiding to use an isolation after the PFC section.
41/52
AN557 APPLICATION NOTE
Figure 56.
Figure 57.
Figure 58.
POWER SUPPLY WITH 0 TO 25V ADJUSTABLE OUTPUT VOLTAGE a) It is a classical solution with high performance that make use of a negative reference voltage equal to the value of the internal voltage of the device (5.1V). To generate this negative reference voltage, it is useful to equip the mains trnsformer with another secondary winding at a low voltage of around 8Vac and capable of delivering a few dozen of mA. During the phase of starting up and stopping of the mains, it is important to avoid generating oscillations around the value of the output voltage , including the zero voltage. For this reason a network consisting of two NPN signal transistors TR1 and TR2 and some resistors has been introduced. The transistor TR2 remains is saturation when TR1 is off, untill the output voltage of the negative regulator reaches 4.3V At this point TR1 goes in saturation, sending off TR2. In this way the soft start is
42/52
AN557 APPLICATION NOTE
blocked and the device begins to work starting in soft start. Switching off the mains voltage, the regulator generating the negative volatge is still in regulation when the input voltage of the switching converter has already dropped below the turn on threshold. Carefull attention must be given therefore to calculate the input capacitor of the two sections in order to avoid possible malfunctioning during the turning on and turning off. b) a solution that presents a cheaper costs and tha doesn't use a negative reference voltage is the following: Setting the cursor "P" to the adjustable resistance at 0V, using R1 and R2 the maximum output voltage can be fixed. In this case we set R1 = 24Kohm and R2 = 4K7ohm. In R1 the maximum flowing current will be limited at 1mA; with 1mA flowing in R1, Vo = 30V. Now by reducing the current in R1 the output voltage Vo can be adjusted till to 0V. Figure 59.
Figure 60.
43/52
AN557 APPLICATION NOTE
The current, flowing in backward, to have 0V it will be: Vr e 5.1 V I1 = ---------f = ------------ = 0.21 m A R1 24 K VR2 = R2 · 0.21 = 4.7k · 0.21 = 1V Therefore, when the cursor "P" reaches Vref + 1V the output voltage goes to zero. At this point we are able to define as well the values of P1 and R3. When the "P" cursor is completely moved to high, there should be 6V of dropping to "P", and in this way 0.6mA will flow. The current flowing in R3, considering that the voltage at pin 15 has a typical value of 12V, it will be of 0.8mA. In this case the R3 value will be 7K5ohm. 3.3V / 10A DC-DC CONVERTER When an output voltage lower to the reference voltage of 5.1V must be stabilized with a good result from stability and regulation point of view, and not having available the not-inverting input of the error amplifier, it is possible to use an external reference. In this case a TL431C reference has been chosen, which is cheaper and widespread used. In this case more than a simple reference, it is a true shunt regulator, containing a reference, an error amplifier and a transistor capable of absorbing a max current of 100mA. Such component can be compensated like a common OP/AMP, and therefore in our application can substitute both the internal reference and the error amplifier. The fig. 61 represents the electrical diagram of the application at 3.3V. The operating input voltage is between 12V (due to the internal UVLO) and 35V, with a minimum operating sw itching frequency of 100KHz. The maximum operating input voltage is limited only 35V because the minimum "ON" time, which should not be reduced below 1 microsecond. At input voltage of 35V, output voltage of 3.3V and fs=100KHz the Ton time is already about of 1 microsecond. Figure 61.
12V
L4970A
7
CORE TYPE 58071 MAGNETICS
D93IN001
44/52
AN557 APPLICATION NOTE
Infact we have: To n Vo V o = V i -------- therefore: T o n = ------ T T Vi The inductor can be calculated using the usual formula, that is: ( Vi V ) V L = ------------------o------------o -V i I L f s w with IL = 10% Iomax, L = 30H When one operates with input voltage below of 5V, it' very difficult to obtain a good efficiency. In our case having the conduction losses and switching losses of the internal power transistor fixed by both external operating electrical condition and the electrical characteristics of the itself power transistor, since integrate, it's necessary to optimize the losses of the catch diode, using new type at lower forward voltage drop, as soon as available on the market or by appropriately over-dimensioning. In some case a Power MOS used as a synchro-nouos switch can contribute to elevate the overall efficiency of the system. Following are citated the principle results obtained by using our evaluation board: The same solution, obviously can be applied also to the other types of the family, adjusting if needed the compensation network and the coil. Figure 62. Efficiency vs. Input Voltage
(%) 85 Io=5A 80 Io=7A 75 Io=10A 70 Vo=3.3V fsw=100KHz
D93IN002
Efficiency vs. Input Voltage
Vi (V) 12 15 20 25 30 35 Io = 10A % Io = 7A % Io = 4A % 70.9 72.1 72.9 72.9 71.9 68.3 76.2 76.7 77.3 77.2 76.4 75.9 82 82 81.2 80.6 79.6 78.5
Figure 63. Load Transient Response
Figure 64. Load Transient Response
65
60 0 5 10 15 20 25 30 35 Vi(V)
Output voltage ripple vs inductor value. Co = 1000F/10V - EKR; ESR = 10m
L VOmax L = 30H L = 50H L = 60H L = 100H 80mV 60mV 40mV 25mV
45/52
AN557 APPLICATION NOTE
CURRENT GENERATOR Often it is required to generate constant current , fixed or adjustable, for various applications, such as chemical process, lamp powering, battery charger for lead acids, ni-cd and ni-me-hyd batteries. Figure 65. Constant Current Generator and battery chargers.
220nF Vi40V 11 18 17 2200 F 2.7nF 5 8 1 150H 20 330 9 Vo=12V/1A
L4972A
7 R2 2.4K 13
390pF
30K
2.2F
15K
0.1F 10K Q2
30K
1K STPS640
Rx 100K
470F
22nF
Q1
R1 50
D93IN003A
Rsense 100m
Figure 66.
9
L4972A/74A
+
E/A PWM
5.1
OUTPUT STAGE
6
-
11 1 10 15 14 8
2
4.7K +
LM358
100
Rs V+ 100
V+ Rs 5.1 100 100+4.7K 100nF
D93IN004
Iomax=
V+=
~100mV
In this paragraph some suggestions will be given for how to abtain generators of constant current, more or less sophisticated according to the need. The examples given are time by time applicable to the different devices of this family of regulators, with the necessary adjustement according to the current required by the application. The diagram of fig. 66 propose a simple solution that makes use of two esternal small signal-transistor
46/52
AN557 APPLICATION NOTE
best if matched in Vbe, and some other passive components. For a cost reduction Q1 can be substitute by a simple diode 1N4148. The divider composed by R2 and R1 fixes a voltage at the whished voltage value (for example 50 -100mV) on the Q2 emitter. Q2 will be reversed bias untill the emitter voltage of Q1 will raech the same value as itself. At this point Q2 will be direct bias and will begin to absorb current from its collector; in the moment in which Q2 will enter into conduction, a variation Vsc at the current sense resistor will give a variation of the Q2 current equal to: V C I C Q 2 = --------S----R1 When the current absorbed by Q2 will reach the maximum current delivered by the error amplifier output (or by the current of the soft-start if this pin is prefered to use), the error amplifier will fall out of regulation and its output voltage will begin to decrease reducing, conseguentely, the duty cycle; then the regulator will begin in this way to behave as a generator of current instead of voltage. The emitter voltage of Q2 is fixed by the following formula:
VREF R1 V E Q 2 = --------------------- R 1 = 5.1 V --------------------R1 + R2 R1 + R2
A general criterium, is that of fixing the divider "R1R2" in such way as to make a current flow that is greater than the necessary lowering the output voltage of the error amplifier. The maximum current delivered by the output of the transconduttance error amplifier is 200mA; the current that has to flow in the divider R1R2 should be around of 2-3mA to have a very precise inter-vation or around only 1mA for slightly more soft interventions. By varying the value of R2, the point of intervention of the current limitation will be moved. The resistor Rx contributes to introducing a more or less accentuate foldback effect, on the output current. In the following table suggest a few values of Rsense according to the nax output current.
Rsense (m) 10 15 30 50 100 Io (A) 10 7 5 3.5 2 Device L4970A L4977A L4975A L4974A L4972A
The criterium used to defined the value of the sense resistor is essentially tied to the max power dissipated by the resistance, as well as to the market availability. If the mains objective is to maximize the efficiency when (delivering for example 10A), it is convenient to use two current transformers instead of a dissipative resistor, one in series to the source of the internal DMOS and one in series to the catch diode. Using such solution, a quite simple and fine regulation of the current is possible to implement. Figure 66 shows a current generator solution with high precision on the current, using an op/amp instead of two small signal transistors. Higher input voltage. Since the maximum operating input voltage of this family is 50V, when one of these devices must be supplied with more elevated voltages, it is necessary to introduce a preregulator. Fixing the output voltage of the preregulator of 45V, the power dissipation of the preregulator is: Pd = Ii · VCE = Ii · (Vi - 45)
47/52
AN557 APPLICATION NOTE
In the buck converter, the average input current is: To n Vo I i = I o -------- = I o -----T V
i
DESIGN EXAMPLE FOR L4974A
(a) Vo = 5.1V Io = 3.5A Po = 17.85W Ii = 0.388A Vo = 12V Io = 3.5A Po = 42W Ii = 0.933A (b)
W ith an operating input voltage of 60V the preregulator will dissipate: Pd = 5.82W The overall efficiency will be: n = 68% Figure 67. Design Example for L4974A
Pd =13.4W
n = 70%
220nF
Vi=50 to 70V
BDW23C
11
1 150H Vo=5V
L4974A
3K 3300F 50V 2200 F 47V 10F 8 17 18 5 7
20 9
SB560 15K 2.2F 2.7nF 30K 390pF 22nF 3x 100F EKR
D93IN005
Up Down Converter In some applications it is required to stabilize a voltage starting from an input voltage which can be lower or higher then the output regulated voltage. In this case a well known buck-boost topology is suggested. The fig. 68 which shows the electrical diagram of the up-down converter, makes use of the L4974A to generate an output voltage of 12V at 3A. For output current lower or higher than 3A other devices of this family can be used. For input voltage less than 20V the zener diode can be avoided. Such circuit can also be used as a simple step-up. In this case there is a structure of the "asymmetrical two transistor converter" type, that in the case of a short circuit is automatically protected since the internal transistor turn-off, disconnecting the power supply. This doesn't happen in the classical step-up converter topology, in which, during the short circuit only the power transistor is protected, but the current in the coil and the freewheeling diode is not limited. Negative Output Voltage Often it becomes necessary, in the multioutput power supplies, to generate negative voltages with current
48/52
AN557 APPLICATION NOTE
higher than 1A maintaining an elevated efficiency of the system. Such outputs must have a good precision and stability and must be protected from short circuiting. With the application circuit suggested below, one the aime is to satisfy the performance listed above, and to contributing to the simplification of the power trasformer, both at 50Hz and at high frequency. It's important to remember not to exceed the absolute maximum voltage ratings of the device. In this case the differential voltage applied to the device is the sum of the maximum input voltage (positive) and of that controlled output negative. Figure 68.
220nF 150H 20 12K 9 1K 7 SB560 56nF 4.7K 3x 100F EKR
12V
11
1
SB560
Vo=18V/3A
L4974A
1000 F 8 17 5,6 18 15,16
2.2F
2.7nF
390pF
15K 30K 22nF
Dz 20V
D93IN008A
Figure 69. Circuit for negative output voltage
220nF 100H 20 6.2K 9 7 SB560 390pF 4.7K -12V 2.2F 2.7nF 30K 15K 22nF 470F
12V
11
1
L4974A
1000 F 8 17 5,6 18 15,16
D93IN009
Linear low drop post regulation In some application it becomes necessary to generate stable, precise fixed or adjustable output voltages at high efficiency and with a truly negligible output ripple. Summarizing a regulator that offers the quality of a linear type of control with the efficiency of a switching regulator. The fig. 70 shows the diagram of a sw ithcing preregulator at high efficiency followed by one or more series regulators of the type very "low drop", or in the case of elevated current, by a discret low drop solution.
49/52
AN557 APPLICATION NOTE
Figure 70.
L7805 5V/1A
L1 HIGH POWER PREREGULATOR
L2 L7812 C2
12V/1A
5V/0.4A L4805
D93IN010A
L2 and C2 are necessary to reduce the switching frequency spikes
LAYOUT CONSIDERATIONS Both for linear and switching power supplies when the current exceeds 1A a careful layout becomes important to achieve a good regulation. The problem becomes more evident when designing switching regulators in which pulsed currents are over imposed on dc currents. In drawing the layout, therefore, special care has to be taken to separate ground paths for signal currents and ground paths for load currents, which generally show a much higher value. When operating at high frequencies the path lenght becomes extremely important. The paths introduce distributed inductances, producing ringing phenomena and radiating noise into the surrounding space. The recirculation diode must be connected close to output pin, to avoid giving rise to dangerous extra negative voltages, due to the distributed inductance. HEA TSINK DIMENSIONING The heatsink dissipates the heat produced by the device to prevent the internal temperature from reaching values which could be dangerous for device operation and reliability. Integrated circuits in plastic package must never exceed 150C even in the worst conditions. This limit has been set because the encapsulating resin has problems of vitrification if subjected to temperatures of more than 150C for long periods or of more than 170C for short periods. In any case the temperature accelerates the ageing process and therefore influences the device life. A well designed heatsink should keep the junction temperature between 90C and 110C. Fig 71 shows the structure of a power device. As demonstrated in thermo-dynamics, a thermal circuit can be considered to be an electrical circuit where R1, R2 represent the thermal resistance of the elements (expressed in C/W) (see fig. 72).
C1, C2 I V are the thermal capacitance (expressed in C/W). is the dissipated power. is the temperature difference with respect to the reference (ground). This circuit can be simplified as shown in fig. 74, where:
CC
Ch
Rjc
is the thermal capacitance of the die plus that of the tab. is the thermal capacitance of the heatsink is the junction case thermal resistance is the heatsink thermal resistance
Rth
50/52
AN557 APPLICATION NOTE
Figure 71. Thermal contact resistance depends on various factors such as the mounting, contact area and planarity of the heatsink. With no material between the device and heatsink the thermal resistance is around 0.5C/W;; with silicone grease roughly 0.3C/W and with silicone grease plus a mica insulator about 0.4C/W. See fig. 75. In application where one external transistor is used together, the dissipated power must be calculated for each component. The various junction temperature can be calculated by solving the circuit shown in fig. 75. This applies if the dissipating elements are fairly close with respect to the dissipator dimensions, otherwise the dissipator can no longer be considered as a concentrated constant and the calculation becomes difficult. This concept is better explained by the graph in fig.77 which shows the case (and therefore junction) temperature variation as a function of the distance between two dissipating elements with the same type of heatsink and the same dissipated power. The graph in fig. 77 refers to specific case of two elements dissipating the same power, fixed on a rectangular aluminium plate with a ratio of 3 between the two sides. The temperature jump will depend on the total dissipated power and on the devices geometrical positions. We want to show that there exists an optimal position between the two devices: d = 1 · side of the plate -2 But since the aim of this section is not that of studing the transistors, the circuit can be further reduced as shown in figure 74. Figure 74. Figure 75.
Figure 72.
Figure 73.
Figure 76.
If we now consider the ground potential as ambient temperature, we have: Tj = Ta + (Rjc + Rth) Pd a) T T R j c Pd R t h = ----j-----------a---------------------Pd b)
51/52
AN557 APPLICATION NOTE
Figure 77.
Figure 78.
Fig. 78 shows the trend of the temperature as a function of the distance between two dissipating elements whose dissipated power is fairly different (ratio 1 to 4). This graph may be useful in applications with two devices in MTW package are synchronized.
REFERENCES: 1) AN244 "Designing with the L296 monolithic power switching regulator". 2) Table1 (see page 36-37/52) EKR & EKE Roederstein Low Voltage Electrolytic Capacitors.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
52/52
|
