APPLICATION NOTE
INITIALIZATION OF THE ST9
Pierre Guillemin and Alan Dunworth
INTRODUCTION The ST9 family offers the microprocessor designer a wide variety of architectural features configurable to the user's specific application requirements. Central to all these configurations is a multiple register based microcomputer core to which may be added on-chip, powerful peripheral components including A/D Convertors, Serial Communication Interface units (SCI's), and 16-bit Multifunction timers with input capture/output compare capabilities. The availability, on-chip, of these application-specific units obviates the need for external interface design as well as offering high-speed and good reliability. The particular peripherals incorporated on-chip may themselves be individually configured to offer a wide variety of functional (architectural) alternatives. This configuration is typically implemented by simple software routines included in the power-on- or system- reset routines. The sole difficulty which the user may initially encounter stems, in fact, from the power and versatility of this approach to system design. The large number of available options means that the user must specify a large number of system parameters by initializing control register contents for the specific peripheral units. The objective of this Application Note is to suggest to the user a programming structure and philosophy to aid in the initial configuration of the system. The approach is illustrated by a number of specific examples selected from the wide range available for the ST9030, ST9040 families, but are applicable to all ST9s. System Reset After processor Reset the control and status registers, located on the group F pages (0-63) are forced to preset values which define a default Reset configuration for the ST9 system. By way of example the internal clock frequency (INTCLK) is set to the internal crystal oscillator (or externally applied clock frequency, if supplied) divided by two without prescaling, and the individual pins of Parallel Ports 0,1, and 6 are set to bidirectional Pullup mode (for systems with on-chip ROM). On releasing the external RESET signal the processor PC is loaded with the contents of the Reset Vector stored in address locations 0 and 1. This causes a jump to a Reset routine in which the designer may reconfigure the ST9 system as appropriate to the requirements of his particular application, by loading suitable values into the system registers. The number of registers to be initialized may be considerable for a representative ST9 system. Additionally, the application-specific interrupt routines will, in general, involve the m nipulation of substantial system a resources, e.g. read/write of data registers, and test/reset of status, mask, and control registers. The associated programming task may appear daunting in prospect on firstacquaintance with the ST9 system. Conceptually, the organization of the associated software is relatively simple and straightforward as may be recognized by grouping under four headings the programming steps involved in the initialization of ST9 peripherals and the organization of interrupt service routines.
AN413 / 1292
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a) ST9 Core System Configuration Certain core system resources are common to all on-chip peripherals and may be specified in a common routine which is invoked at System Reset. Such common resources include clock configuration, system and user stack specification, global interrupt masking, processor priority setting, parallel port bit-by-bit specification, and setting of external memory wait-cycles. The setting up of the interrupt vector table, and certain global masking or enabling operations, may also be included under this heading. b) Individual On-chip Peripheral Configuration The configuration of on-chip peripherals, e.g. Multifunction Timers, A/D Converters, etc., involves the loading of suitable bit-patterns into group F page registers. This enables the specification of input and output signals, determination of the peripheral's mode of operation, and the selection of internal or external clock and control signals. c) Individual On-chip Peripheral Initialization The initialization of a particular on-chip peripheral may involve the setting or clearing of device-specific enable and masking bits, specification of interrupt priority levels, clearing of status/flag values, and the loading of data and/or limit registers. d) Organization of Interrupt Service Routines This will normally include context-saving and restoring of the PC and system status, plus the working-register and page-pointer registers, together with the values of any working registers used in the routine. The routine proper may include testing of status flag bits, and the reading and writing of data registers associated with the particular device. Finally, the interrupt pending bits should be cleared, the context restored, and individual masking and enabling bits restored to the appropriate values. In practical programming terms there will normally be a single routine invoked on system RESET which carries out the core system configurations listed under heading a) above. For each individual peripheral there will typically be a single routine which carries out the configuration andinitialization operations listed under headings b) and c). There will also be one or more interrupt routines associated with each peripheral, e.g. the A/D converter may require in general two interrupt routines, one for End of Conversion, and one for out of range operation (i.e. Analog Watchdog operation) on channels 6 and 7. An example of a core-system configuration is given in Appendix B, and Appendices C,D,E, and F give configuration/initialization examples, and Interrupt routines for the Timer, A/D Convertor, SCI unit, and Timer/Watchdog respectively. There is not space in a short note to discuss these programmes in detail on a line by line basis. Instead the approach will be to list, for each device, the resources which need to be taken into consideration when configuring, initializing, and servicing the particular device. An example will then be given of the specific use of each such resource. With this background, the interested user should be able to follow in detail those listings most relevant to his particular application area.
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ST9 BASIC SYSTEM CONFIGURATION Tables A.1 and A.2 in Appendix A lists the registers which should be loaded with specified bit-patterns in order to initialize the ST9 to a basic system configuration. A demonstration routine which carries this out for a representative ST9 system is listed in Appendix B. The main routine, RESET_START, is invoked at system Reset. Also shown in Appendix B are the Assembler Declarations and directives which enable the Interrupt Vector Address Table to be set up in program memory. The Vector Address Table The ST9 implements an interrupt vectoring structure that allows the on-chip peripheral to identify the location of the first instruction of the Interrupt Service Routine (ISR). Each interrupt module has a specific Interrupt Vector Register (IVR) mapped on the register file pages. When the interrupt request is acknowledged, the peripheral interrupt module provides, via the IVR, the vector to point to the address of the Interrupt Service Routine in the Vector Table. The Interrupt Vector table containing the list of addresses of the Interrupt Service Routine must be located in the first 256 locations of program memory. The first 6 locations of Program memory are reserved as follows:
Address 0 1 2 3 4 5 Content Address high of Power on Reset routine Address low of Power on Reset routine Address high of Divide by Zero Trap Subroutine Address low of Divide by Zero Trap Subroutine Address high of Top Level ISR Address low of Top Level ISR
Note that since the above locations are fixed by the hardware no associated IVR register is involved. For certain interrupt modules more than one interrupt routine may be required. For example the A/D Convertor has separate interrupts for the End of Conversion and Channel 6/7 analog underflow/overflow conditions. In such cases the IVR register specifies the more significant, and the interrupt module hardware specifies the less significant bits of the Vector Table address. The following Assembler outline shows how the corresponding Vector table entries may be est blished. a ADC_IT_VECT:= 30h . .org ADC_IT_VECT .word ADC_WDG .word ADC_EOC . ADC_WDG: ; Code for the Analog Watchdog Routine is included here ; Note that in the example in Appendix B ; the System Reset routine is invoked for out of ; range conditions on Channels 6 and 7 . iret ADC_EOC: ; End of A/D conversion interrupt routine included here iret
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PORT INITIALIZATION The ST9 has up to a maximum of 64 lines dedicated to input/output. These lines, grouped into eight 8-bit ports, can be independently programmed to provide parallel input/outputs with or without handshake or may be used to connect in/out signals to/from the peripherals (e.g. Core, Timers, SCI units, etc.) present on the chip. The functional allocation of the Ports to support system tasks may be summarised as follows:
Port 0 1 2 3 4 5 6 Functions
Usable as I/O Port (without handshake) or as multiplexed low-address and data lines for external memory. Usable as I/O Port (without handshake)or as high-address lines for external memory. Usable as I/O Port (without handshake)or for SPI functions; Also INT1, INT2, and INT3 inputs. Usable as I/O Port (without handshake)or for Timer functions. Usable as I/O Port (with or without handshake) Usable as I/O Port (with or without handshake). Usable as I/O Port (without handshake) Usable as I/O Port (without handshake) or for SCI functions. Also used for INT4, INT5, and INT6 inputs or for Control signals for slow external memory
7
Ports 0, 1, and 6 are automatically initialized on system Reset to correspond to the installed on-chip memory. Ports 2, 3, 4, 5, 6, and 7 need to be initialized (if available) to satisfy the specific application requirements for external I/O, plus any alternative function assignments of port pins, and internal interconnections. Table A.3, Appendix A, lists the complete set of Port Configuration registers together with their addresses. Example: C7 F5 F5 F5 0A FC 05 FD 0F FE 05 spp ld ld ld P3C_PG P3C0R,#0 0 0101b P3C1R,#00001111b P3C2R,#0 0 0101b
In this example Port 3 pins 4, 5, 6, and 7 are configured as bidirectional pins, with weak pull-up output and TTL inputs. Pins 0 (T0INA) and 2 (T0INB) are configured as TTL inputs, and Pins 1 (T0OUTA) and 3 (T0OUTB) are configured as Alternate Function Push-pull outputs.
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MULTIFUNCTION TIMER CONFIGURATION The ST9 Multifunction Timer is configured by loading suitable control-bit patterns in the groupe F page register TCR, TMR, ICR, OACR, and OBCR (see Table A.4 in Appendix A). Note that registers EIMR and CICR provide global control functions common to all on-chip peripherals and are hence initialized conveniently in the basic system configuration routine. The External Input Control Register, ICR, controls input source selection (internal/external), input mode selection (falling/rising edge sensitive, etc.), counter mode of operation (continuous, one-shot, etc.), and input function (Gate, Trigger, up/down control, etc.). Example: F5 FA 54 ld T_ICR,#01010100b This instruction selects the external input A as a falling-edge-sensitive Trigger input, and the B input is a normal Port I/O pin. The Multifunction Timer Control Register, TCR, controls counter clear and prescaler reload operations as well as providing a counter enable control bit and counter status flags. Example: F5 F8 48 ld T_TCR,#01001000b This instruction halts the counter operation but provides for subsequent UP counting with counter clear and Prescaler reload on Reg0 or Reg1 capture. The Multifunction Timer Mode Register, TMR, selects the clock source for the counter-prescaler input, enables Retrigger or Continuous mode, and controls register load/capture operations. Example: 98 8C ld T_TMR,#10001100b This pattern enables output 1 and disables output 0, disables bivalue modes, and selects Reg0 for capture and Reg1 for monitor. Retriggerable continuous mode is selected. The Output Control Register, OACR, links the output T0OUTA to counter overflow/underflow and Compare events, and provides for subsequent Set, Reset, or Toggle of the external output. The on-chip event (OCE) may be linked to a COMP0 event. Example: F5 F5 1B ld T_OACR,#00011011b In this example T0OUTA is preset to 1, and is subsequently set by COMP0, toggled by COMP1, and Reset by OVF. The OCE signal is generated by a successful CMP0 compare event. The Output Control Register, OBCR, links the output T0OUTB to counter overflow/underflow and Compare events, and provides for subsequent Set, Reset, or Toggle of the external output. The on-chip event (OCE) may be linked to a counter overflow/underflow event. Example: F5 F6 83 ld T_OBCR,#10 0 011b In this example T0OUTB is preset to 1, and is subsequently reset by COMP0, and set by OVF and COMP1. The OCE signal is generated by a counter overflow/underflow event.
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MULTIFUNCTION TIMER INITIALIZATION Initialization of the Multifunction Timer requires loading of the Prescaler register and the two Comparison registers. The timer Status register should be cleared, the Vector Table entry should be set, and the Multifunction Timer counter actions enabled. The interrupt/DMA priority levels should be set and the mask bits should be adjusted as appropriate to the application. Further, if DMA operations are specified, DMA address and counter registers will require initialization. The Prescaler Register, PRSR, holds the preset value for the 8-bit prescaler. Example: BC 00 ld T_PRSR,#00h This defines a division ratio of 1 and the maximum counter clock is generated (INTCLK/3). The Multifunction Timer Flags Register, FLAGR, contains flags which register successful capture or comparison events together with OVF/UNF and overrun conditions. Example: 15 FE FD and T_FLAGR,#~ocm0 This example resets the overrun bit for COMP0 operations. The Interrupt Vector Register, IVR, should be loaded with the 5 most significant bits of the Multifunction Timer's interrupt vector address in program memory. The interrupt source (compare, capture, or OVF/UNF) provides the least significant 3 bits to provide the correct vector link. Example: F5 F2 10 ld T0_IVR,#T0_IT_VECT In this example IVR is loaded with the start address (10h) of the block of 8 words in the vector table allocated to the 5 different Multifunction Timer interrupts.
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MULTIFUNCTION TIMER INITIALIZATION (Continued) The Interrupt/DMA Control Register, IDCR, is used to set the Interrupt and DMA priority levels, and the DMA transfer source and destination. It also enables Swap mode and contains End of Block condition flags. Example: F5 F3 D6 ld T0_IDCR,#11000110b In this example the priority level is set at a value of 6, and the Swap mode is disabled. The DMA capture channel source is REG0, and the DMA compare channel source is CMP0. The Interrupt/DMA Mask Register, IDMR, contains a global Multifunction Timer Interrupt enable plus individual DMA and Interrupt enable bits for overflow as well as successful capture and comparison events. Example: F5 FF 04 0F FF 80 ld or T_IDMR,#0 0 0100b T_IDMR,#gtien
The first instruction sets the interrupt enable on CMP0, and the second instruction globally enables all Multifunction Timer interrupts. The DMA Counter Pointer Register, DCPR, defines the DMA area and source, and specifies the location of the DMA length register. Example: F5 F0 4C ld T0_DCPR,#CPT_LG_DMA The DMA length register is 4Ch = rr12 = RR76 and the transfer occurs to/from Program/Data memory. The DMA Address Pointer Register, DAPR, defines the DMA area and source, and specifies the location of the DMA address register. Example: F5 F1 48 ld T0_DAPR,#CPT_AD_DMA The DMA address register is 48h = rr8 = RR72. In conjunction with the DPCR value in the above example it specifies Program memory for the buffer.
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A/D CONVERTOR CONFIGURATION/INITIALIZATION Configuration of the A/D convertor requires loading of 4 registers only, CLR, CRR, ICR, and IVR (Table A.6), and initialization of this device involves, apart from global masking, loading of two double (t reshold h registers). Hence a single routine can be written to cover both the configuration and initialization aspects of A/D Convertor use. The Control Logic Register, CLR, defines the Analog channel conversion start address, selects internal/external triggers, and enables continuous or single conversion and power up/down modes. This register also contains a start/stop status/control bit. Example: F5 FD 04 ld AD_CLR,#0 0 0100b In this example, the conversion scan starts with channel 0 when enabled, powers up the A/D convertor, halts conversion, and specifies single conversion scan mode. Please note that before enabling any A/D conversion, it is mandatory to set the low bit of Control Logic Register at least 60s before the first conversion start. This is in order to correctly bias the analog section of the converter. The Interrupt Vector Register, IVR, defines the most significant 6 bits of the vector table byte address. It thus points to the first of two word addresses which correspond to the analog watchdog and End of conversion interrupt routines. Example: F5 FF 32 ld AD_IVR,#ADC_ITEOC_VECT In this example, an address of 50 (decimal) is loaded into IVR. Hence a subsequent A/D convertor EOC interrupt will cause a Vector Table access at location 50. The Interrupt Control Register, ICR, contains the priority level specification, the two source interrupt flags (Analog Watchdog and EOC) and their individual masking bits. Example: F5 FE 20 05 FE 20 ld or AD_ICR,#0010 0 0b AD_ICR,#0 0 0110b
In this example, the priority level is first set at 0, End of Conversion interrupts are enabled, and theAnalog Watchdog interrupt is masked. The second instruction then sets the priority to a level of 6. If the Analog Watchdog is enabled (bit 6 in ICR) it will be necessary to load the threshold registers for channels 6 and 7. In this case access will be made in the interrupt routine to register CRR. The Compare Result Register, CRR, contains 4 flags showing the results of comparison operations between the current values of data registers 6 and 7, and the upper and lower threshold registers.
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SCI UNIT CONFIGURATION The list of registers to be initialized when configuring the SCI unit is given in Table A.9. The functions of these registers, and some illustrative examples of their use, are as follows: The Character Configuration Register, CHCR, is used to define the serial frame format. Example: AC E3 ld S_CHCR,#E3h This example defines a serial frame as follows: 8 data bits, 1 stop bit, even parity, and address input if the character matches the contents of the Address Register. The Clock Configuration Register, CLCR, is used to specify the transmitter, receiver, and Baud Rate clock sources, and the clock divisor ratio. It also enables Auto Echo and Loopback test modes. Example: BC 80 ld s_clcr,#txclk In this example, the Transmitter and Receiver clocks are provided by the Baud Rate Generator. Each data bit period will be 16 clock periods (asynchronous mode), and the Auto Loop and Loopback modes are disabled. The Baud Rate Generator Register, BRGR, specifies a 16-bit division ratio. Example: BF DC 00 4E ldw s_brgr,#DIV_9600 This example specifies a division ratio yielding 9600 Bauds with a 24 Mhz external clock. Writing to a Baud Rate Generator Register immediately disables and resets both the SCI Baud Rate generator, the transmitter and receiver circuitry. After writing to the remaining Baud Rate Generator Register, the transmitter and receiver circuits are enabled. The Baud Rate Generator will load the new value and start counting. To initialize the SCI, user should first initialize one Baud Rate Generator Divisor Register. This will reset all SCI circuitry. Initialize all other SCI registers for the desired operating mode. To enable the SCI, initialize the remaining Baud Rate Generator Register. The Address Compare Register, ACR, contains an 8-bit value which may be used as a match against which a received address may be tested to set the Receive Address Pending bit. Example: 5C 0D ld s_acr,#RETURN This will cause the Receive Address Pending bit to be set if an End of Command character bit-pattern is received.
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SCI UNIT CONFIGURATION (Continued) The Interrupt Vector Register, IVR, defines the most significant 5 bits of the vector table byte address. It thus points to the first of four vector table word address entries. Example: 4C 00x ld s_ivr,#SCI_IT In this example, after the external symbol has been linked in, the Vector Table entry address will be loaded into IVR at execution time. The Interrupt Mask Register, IMR, contains five interrupt masking bits and two End of Block DMA status bits. It also selects the shift register or holding register as source of the transmitter register empty interrupt. Example: 6C 05 ld s_imr,#0 0 0101b In this example the interrupt pending bits are reset, the Transmitter data interrupt is masked, and the Receiver data, data error, and address interrupts are unmasked. The Interrupt/DMA Priority Register, IDPR, specifies the Interrupt/DMA priority, selects one of four Address modes, and controls the emission of Break characters and enables address/9th bit data mode. It also provides mask bits for Receive and Transmit DMA transfers. Example: 9C 04 ld s_idpr,#04h In this example a priority level of 4 is specified, and Transmitter DMA requests are masked.
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SCI UNIT INITIALIZATION The list of registers to be initialized when initializing the SCI unit is given in Table A.10. The functions of these registers, and some illustrative examples of their use, are as follows: The Receiver DMA Transaction Counter Pointer Register, RDCPR, contains the register file address of the receiver DMA transaction counter. In addition it determines whether the DMA transfers occur in the register file or in memory. Example: An example of the use of this register is provided below (see RDAPR example). The Receiver DMA Destination Address Pointer Register, RDAPR, contains the register file address of the receiver DMA data destination. In addition, in conjunction with bit 0 of RDCPR, it determines whether the DMA transfers occur in Program or Data memory. Example: 00 00 00 00 2C 1C F5 F5 FF A0 02 03 03 02 03 0F 02 00 LNG-DMA_SCI := 0Fh DEPART_DMA_SCI := 0A0h NUM_RDAP := 2 NUM_RDCP := 3 ld S_rdcpr,#NUM_RDCP ld S_rdapr,#NUM_RDAP ld R#NUM_RDCP,#(LNG_DMA_SCI) ld R#NUM_RDAP,#(DEPART_DMA_SCI)
In this program sequence the DMA transaction counter and Address Pointer register addresses are defined to be R3 and R2 respectively. These two registers are initialized for a block of size 15 bytes starting at register address A0, i.e. R160. The Transmitter DMA Transaction Counter Pointer Register, TDCPR, contains the register file address of the transmitter DMA transaction counter. In addition it determines whether the DMA transfers occur in the register file or in memory. Example: An example of the use of this register is provided below (see TDAPR example). The Transmitter DMA Destination Address Pointer Register, TDAPR, contains the register file address of the transmitter DMA data destination. In addition, in conjunction with bit 0 of TDCPR, it determines whether the DMA transfers occur in Program or Data memory. Example: 00 00 00 00 2C 3C F5 F5 FF A0 06 07 07 06 07 0F 06 00 LNG-DMA_SCI := 0Fh DEPART_DMA_SCI := 0A0h NUM_TDAP := 6 NUM_TDCP := 7 ld S_TDCPR,#NUM_TDCP ld S_TDAPR,#NUM_TDAP ld R#NUM_TDCP,#(LNG_DMA_SCI) ld R#NUM_TDAP,#(DEPART_DMA_SCI)
In this program sequence the DMA transaction counter and Address Pointer register addresses are defined to be R7 and R6 respectively. These two registers are initialized for a block of size 15 bytes starting at register address A0, i.e. R160.
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TIMER/WATCHDOG UNIT CONFIGURATION Configuration of the Timer/Watchdog requires loading of the 6 registers listed in Table A.11, Appendix A. Timer/Watchdog unit Configuration The Timer/Watchdog Control Register, WDTCR, contains a start/stop bit, and is also used to select input, output, and counter modes, as well as input and output enable bits. Example: BC 80 ld wdtcr,#80h In this example the Timer starts counting down in continuous mode, and the input and output sections are disabled. The Wait Control Register, WCR, as well as specifying the number of wait states for access to off-chip program and data memory enables the Watchdog function. Example: CC 40 ld wcr,#wden In this example the Watchdog action is disabled, and the number of wait states are set to zero. The External Interrupt Vector Register, EIVR, contains a bit, TLIS, which is used to control the Top Level Interrupt source (Timer/Watchdog EOC or External NMI). A second bit IAOS is used to select the Timer/Watchdog as an interrupt source on channel A0 (INT0). This register is also used to supply the 4 most significant bits of the External Interrupt Vector. Example: 6C 20 ld eivr,#EXT_IT_VECT In this example the Timer/Watchdog EOC generates an interrupt on channel A0 at each End of Count. The Top Level Interrupt is isolated from the NMI input and may be used for a Software Trap. The Timer/Watchdog Prescaler Register, WDTPR, contains an 8-bit value which is loaded into the Prescaler register. Example: 90 DA clr wdtpr The specified Prescaler value of zero leads to a minimum timer count period of 333ns, assuming a system clock running at 12MHz. The Timer/Watchdog High Register, WDTHR, and Timer/Watchdog Low Register, WDTLR, together contain a 16-bit value which is loaded into the counter at each End of Count. Example: BF F8 0B BB ldw WDTR,#3003 The specified count value leads to a count period of about 1 millisecond, (3003 x 333ns).
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TIMER/WATCHDOG UNIT INITIALIZATION The External Interrupt Priority Level Register, EIPLR, specifies the priority level of four pairs of external interrupts, a), A1,...D0, D1. It is thus used to set the priority of the Timer/Watchdog EOC interrupt routine, called via channel A0. Example: 5C FE ld eiplr,#0FEh In this example priority levels of 4 and 5 are specified for the pair INTA0, INTA1. The External Interrupts Pending Bit Register, EIPR, holds the eight interrupt pending bits for the external interrupts, including, in the present context, the Watchdog/Timer EOC interrupt. These bits are set by hardware action and reset by software during the service routine. Example: 90 D3 clr eipr In this example all the external interrupt pending bits are cleared. The External Interrupts Mask-Bit Register, EIMR, holds the eight interrupt mask bits for the external interrupts, including, in the present context, the Timer/Watchdog EOC interrupt. Example: 4C 01 ld eimr,#ia0 In this example the Timer/Watchdog End of Count on Channel A0 is unmasked.
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INTERRUPT SERVICE ROUTINE ORGANIZATION When an enabled interrupt is acknowledged the Interrupt machine cycle performs the following actions: (i) All maskable interrupts are disabled by clearing the EI bit of register CICR. (ii) The PC (two bytes) and the FLAGS register are saved on the System stack. (iii) The PC is loaded with the 16-bit vector stored in the Vector Table. On exit from the Interrupt service, using an IRET instruction the following operations are carried out: (iv) The FLAGR register is restored from the System stack. (v) The PC is restored from the System stack. (vi) The unmasked interrupts are enabled by setting the CICR.EI bit. In general additional resources must be saved and restored apart from thosehandled automatically by the system as listed above. In a typical case these additional resources will include the two Register pointer registers, the Page-pointer register, and any working registers used in the Interrupt routine. An outline for a suitable Interrupt service routine is hence as follows: Label_int: work_reg_page0 work_reg_page1 WDT_PG T0c_PG T0d_PG S_PG AD0_PG push push push spp srp0 srp1 push push push = = = = = = = (0Dh*2) (0Dh*2) + 1 0 9 10 24 63
RP0 RP1 PPR #T0d_PG #work_reg_page0 #work_reg_page1 r0 r1 rA ; ; ;Interrupt Service routine ;appears here, including ;read/write data registers ;test status flags ;clear interrupt pending flags rA r1 r0 PPR RP1 RP0
pop pop pop pop pop pop iret
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SUMMARY This Application Note has attempted to formalize and simplify the programming task of configuring and initializing an ST9 system. The resources to be controlled have been listed with brief examples of their use. Complete examples of ST9 configuration, initialization, and Interrupt Service routines are presented in a set of Appendices. These programs have been written for an ST9030 but can be readily adapted where necessary for use with other versions.
REFERENCES (1) "ST9 Technical Manual", SGS-THOMSON Microelectronics. (2) Application Note AN411, SYMBOLS.INC Standard Definitions of ST9 Registers and Register-bits.
APPENDICES A. ST9 Core and Peripheral Configuration/Initialization Registers. A.1. System Configuration: System Registers. A.2. System Configuration: Paged Registers. A.3. Port Configuration Registers. A.4. Multifunction Timer Configuration/Initialization Registers. A.5. Multifunction Timer Data/Status Register. A.6. A/D Configuration/Initialization Registers. A.7. A/D Channel Registers. A.8. A/D Threshold Registers A.9. SCI Configuration Registers. A.10. SCI Initialization Registers. A.11. Watchdog Timer Configuration/Initialization Registers. A.12. SPI Initialization. A.13. EEPROM Initialization. B. Examples of ST9 System Configurations. C. Examples of Multifunction Timer 0 Configurations. D. Examples of A/D Converter Configurations. E. Examples of SCI Configurations. F. Examples of Timer/Watchdog Configurations.
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APPENDIX A. ST9 CORE AND PERIPHERAL CONFIGURATION/INITIALIZATION A.1. System Configuration: System Registers
Mnem. CICR FLAGR RP0R RP1R PPR MODER USPHR USPLR SSPHR SSPLR Name Central Interrupt Control Register Flags Register Register Pointer 0 Register Pointer 1 Page Pointer Register Mode Register User Stack Pointer (high) User Stack Pointer (low) System Stack Pointer (high) System Stack Pointer (low) Reg. R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 Hex E6 E7 E8 E9 EA EB EC ED EE EF Pg. Reset Value (Hex) 87 XX XX XX XX E0 XX XX XX XX
A.2. System Configuration: Page Registers
Mnem. EECR EITR EIPR EIMR EIPLR EIVR NICR WCR Name EEPROM Control Register Mask Register External Interrupt Trigger-Event Register External Interrupt Pending Register External Interrupt Mask Register External Interrupt Priority Level Register External Interrupt Vector Register Nested Interrupt Control Register Wait Control Register Reg. R241 R242 R243 R244 R245 R246 R247 R252 Hex F1 F2 F3 F4 F5 F6 F7 FC Pg. 0 0 0 0 0 0 0 0 Reset Value (Hex) 87 XX XX XX XX E0 XX 7F
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A.3. Port Configuration Registers
Port Name Data Register Control Registers (PxC0-PxC2) Data Register Control Registers (PxC0-PxC2) Data Register Control Registers (PxC0-PxC2) Handshake Control Register Data Register Control Registers (PxC0-PxC2) Handshake Control Register Data Register Control Registers (PxC0-PxC2) Handshake Control Register Data Register Control Registers (PxC0-PxC2) Handshake Control Register Data Register Control Registers (PxC0-PxC2) Data Register Control Registers (PxC0-PxC2) Registers R224 R240-R242 R225 R244-R246 R226 R248-R250 R251 R227 R252-R254 R255 R228 R240-R242 R243 R229 R244-R246 R247 R251 R248-R250 R255 R252-R254 Hex E0 F0-F2 E1 F4-F6 E2 F8-FA FB E3 FC-FE FF E4 F0-F2 F3 E5 F4-F6 F7 FB F8-FA FF FC-FE Pg. (Hex) 2 2 2 2 2 2 3 3 3 3 3 3 3 3
0 1
2
3
4
5
6 7
RESET Values: Ports 2, 3, 4, and 5:
PcX0: 0 0 0000 PcX1: 0 0 0000 PcX2: 0 0 0000 Handshake Control Registers: 111111111
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A.4. Multi-Function Timer Configuration/Initialization Registers (MFT0)
Mnem. CICR TCR TMR ICR OACR OBCR IDMR DCPR DAPR IVR IDCR Name Central Interrupt Control Register Timer Control Register Timer Mode Register External Interrupt Control Register Output A Control Register 0 Output A Control Register 1 Interrupt/DMA Mask Register DMA Counter Pointer Register DMA Address Pointer Register Interrupt Vector Register Interrupt/DMA Control Register Reg. R230 R248 R249 R250 R252 R253 R255 R240 R241 R242 R243 Hex E6 F8 F9 FA FC FD FF F0 F1 F2 F3 Pg. 10 10 10 10 10 10 9 9 9 9 Reset Value (Binary) 10000111 0 0 0XXX 0 0 0000 0000XXXX XXXXXX0X XXXXXX0X 0 0 0000 XXXXXXXX XXXXXXXX XXXXXXXX 11000111
A.5. Timer Data/Status Registers (MFT0)
Mnem. REG0HR REG0LR REG1HR REG1LR CMP0HR CMP0LR CMP1HR CMP1LR PRSR FLAGR Name Capture/Reload Register 0 (High) Capture/Reload Register 0 (Low) Capture/Reload Register 1 (High) Capture/Reload Register 1 (Low) Compare Register Register 0 (High) Compare Register Register 0 (Low) Compare Register Register 1 (High) Compare Register Register 1 (Low) Prescaler Register Timer Flags Register Reg. R240 R241 R242 R243 R244 R245 R246 R247 R251 R254 Hex F0 F1 F2 F3 F4 F5 F6 F7 FB FE Pg. 10 10 10 10 10 10 10 10 10 10 Reset Value (Binary) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0 0 0000 0 0 0000
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INITIALIZATION OF THE ST9
A.6. A/D Configuration/Initialization Registers
Mnem. CRR CLR ICR IVR Name Compare Result Register Control Logic Register Interrupt Control Register Interrupt Vector Register Reg. R252 R253 R254 R255 Hex FC FD FE FF Pg. 63 63 63 63 Reset Value (Binary) 00001111 0 0 0000 00001111 XXXXXX10
A.7. A/D Channel Registers
Mnem. AD_D0R AD_D1R AD_D2R AD_D3R AD_D4R AD_D5R AD_D6R AD_D7R Name Channel 0 Data Register Channel 1 Data Register Channel 2 Data Register Channel 3 Data Register Channel 4 Data Register Channel 5 Data Register Channel 6 Data Register Channel 7 Data Register Reg. R240 R241 R242 R243 R244 R245 R246 R247 Hex F0 F1 F2 F3 F4 F5 F6 F7 Pg. 63 63 63 63 63 63 63 63
A.8. A/D Threshold Registers
Mnem. AD_LT6R AD_UT6R AD_LT7R AD_UT7R Name Channel 6 Lower Threshold Register Channel 6 Upper Threshold Register Channel 7 Lower Threshold Register Channel 7 Upper Threshold Register Reg. R248 R249 R250 R251 Hex F8 F9 FA FB Pg. 63 63 63 63
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INITIALIZATION OF THE ST9
A.9. SCI Configuration Registers
Mnem. IVR IMR ISR IDPR CHCR CCR BRGHR BRGLR Name Interrupt Vector Register Interrupt Mask Register Interrupt Status Register Interrupt/DMA Priority Register Character Recognition Register Clock Configuration Register Baud Rate Generator Divisor Register (High) Baud Rate Generator Divisor Register (Low) Reg. R244 R246 R247 R249 R250 R251 R252 R253 Hex F4 F6 F7 F9 FA FB FC FD Pg. 24 24 24 24 24 24 24 24 Reset Value (Binary) XXXXXXXX 0XX0 0 0 XXXXXXXX XXXXXXXX XXXXXXXX 0 0 0000 XXXXXXXX XXXXXXXX
A.10. SCI Initialization
Mnem. Name Receiver DMA Transaction Counter Register Receiver DMA Address Pointer Register Transmit DMA Transaction Counter Register Transmit DMA Address Pointer Register Address Compare Register Receive Buffer Register (Read only) Transmitter Buffer Register (Write only) Reg. Hex Pg. Reset Value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RDCPR RDAPR TDCPR TDAPR ACR RXBR TXBR
R240 R241 R242 R243 R245 R248 R248
F0 F1 F2 F3 F5 F8 F8
24 24 24 24 24 24 24
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A.11. Watchdog Timer Configuration/Initialization
Mnem. EIPR EIMR EIPLR EIVR WDTLR WDTHR WDTPR WDTCR WCR Name External Interrupt Pending Register External Interrupt Masking Register External Interrupt Priority Register External Interrupt Vector Register Watchdog Timer Low Register Watchdog Timer High Register Watchdog Timer Prescaler Register Watchdog Timer Control Register Wait Control Register Reg. R243 R244 R245 R246 R248 R249 R250 R251 R252 Hex F3 F4 F5 F6 F8 F9 FA FB FC Pg. 0 0 0 0 0 0 0 0 0 Reset Value (Binary) 0 0 0000 0 0 0000 11111111 XXXX0010 XXXXXXXX XXXXXXXX XXXXXXXX 00010010 01111111
A.12. SPI Initialization
Mnem. SPIDR SPICR Name SPI Data Register SPI Control Register Reg. R253 R244 Hex FD F4 Pg. 0 0 Reset Value (Binary) XXXXXXXX 0010 0 0
A.13. EEPROM Initialization (ST9040 only)
Mnem. EECR Name EEPROM Control Register Reg. R241 Hex F1 Pg. 0 Reset Value (Binary) 0 0 0000
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INITIALIZATION OF THE ST9
APPENDIX B. EXAMPLES OF ST9 PERIPHERAL CONFIGURATIONS . . ; ; ; ; ; sbttl " ST9030 registers addresses and contents " include "c:\st9\bin\symbols.inc" The reader should refer to the file containing the declaration of all the bits and registers of the ST9030 for the symbols used in the following listing. .nlist
;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * * ;* This program demonstrates the configuration of ST9 peripherals* ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * * ;* * ** * ** * ** * *** ;*RAM Declaration* ;* * ** * ** * ** * *** prescal_t0 := r2 ; Value of Timer 0 Prescaler val_capt_t0 := rr4 ; Value of Timer 0 Capture register nb_event_t0 := rr4 ; Number of Timer 0 event lg_dma := rr6 ; Length of DMA CPT_AD_DMA := RR8 ; DMA Address Register CPT_LG_DMA := RR8 ; DMA Counter Register ad_conv IT_T0_LEVEL IT_CAD_LEVEL := = = r3 4 6 ; conversion start address ; Timer 0 priority level ; A/D converter priority level
;* * ** * ** * ** * ** * **** ;*INTERRUPT VECTOR ADDRESSES* ;* * ** * ** * ** * ** * **** CORE_IT_VECT := 00h ; Core interrupt vectors T0_IT_VECT := 10h ; Timer 0 interrupt vectors EXT_IT_VECT := 20h ; External interrupt vectors ADC_IT_VECT := 30h ; A/D Converter interrupt vectors SCI_IT := 40h ; SCI interrupt vector ;* * ** * ** * ***** ;*STACK Declaration* ;* * ** * ** * ***** SSTACK := 223 USTACK := 191
; System stack address group D C ; User stack address group B
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APPENDIX B. EXAMPLES OF ST9 PERIPHERAL CONFIGURATIONS (Continued) ;* * ** * ** * ** * * ;*Group number names* ;* * ** * ** * ** * * BK0 := 0 BK1 := 1 BK2 := 2 BK3 := 3 BK4 := 4 BK5 := 5 BK6 := 6 BK7 := 7 BK8 := 8 BK9 := 9 BKA := 10 BKB := 11 BKC := 12 BKD := 13 BKE := 14 BKF := 15 BK_0 := BK0 * 2 BK_BDT:= BK2 * 2 BK_CAD:= BK5 * 2 BK_T0 := BK4 * 2 BK_SCI:= BK6 * 2 BK_F := BKF * 2
; ; ; ;
; free user group TWD group A/D group MFTimer 0 group SCI group. ; paged registers
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APPENDIX B. EXAMPLES OF ST9 PERIPHERAL CONFIGURATIONS (Continued) ;* * ** * ** * ** * ** * ** * ** * ** * **** ;*Declaration of the interrupt vector table* ;* * ** * ** * ** * ** * ** * ** * ** * **** .text ; start of program .org CORE_IT_VECT ; Core interrupt vector * * ** * ** * ** * *** .word DIV0 ; divide by 0 interrupt vector .word TOP_LEVEL_IT ; Top level interrupt vector .org T0_IT_VECT ; Timer 0 interrupt vector ; * * ** * ** * ** * **** ; unused addresses ; Timer 0 capture interrupt vector ; Timer 0 compare interrupt vector ; External interrupt vector ; * * ** * ** * ** * ** * * ; Watchdog Timer interrupt vector ; ADC interrupt vector ; * * ** * ** * ** * * ; Analog Watchdog interrupt vector ; End of conv. interrupt vector ; ; ; ; ; SCI interrupt vector * * ** * ** * ** * * unused addresses receiver interrupt Transmitter interrupt
.org T0_IT_VECT + 4 .word T0_CAP .word T0_COMP .org EXT_IT_VECT
WDT_IT:
.word
TEMPO
.org ADC_IT_VECT
.word RESET_START .word ADC_EOC .org SCI_IT .org SCI_IT + 4 .word REC_DATA .word TRA_HOLD
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INITIALIZATION OF THE ST9
APPENDIX B. EXAMPLES OF ST9 PERIPHERAL CONFIGURATIONS (Continued) ;* * ** * ** * ** * *** ;*Start of main module* ;* * ** * ** * ** * *** .org 100h RESET_START: ld MODER,#1110 0 0b ; start of code
; ; ; ; ; ; ; ; ;
CLOCK MODE REGISTER internal stack no prescaling external clock divided by 2 CENTRAL INTERRUPT CONTROL REGISTER priority level = 7 concurrent mode disable interrupt
ld
CICR,#10000111b
clr spp ld ld
FLAGR #WDT_PG WCR,#wden EIMR,#0
; ; ; ; ;
watch dog mode disabled, no wait states. mask all channel interrupts. at reset,Global Counter Enable bit is active.
ld SSPLR,#SSTACK + 1 ld USPLR,#USTACK + 1 call INIT_IO MAIN: jxt MAIN
; load system stack pointer ; load user stack pointer ; init I/O ports
; include your Main program here !
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INITIALIZATION OF THE ST9
APPENDIX B. EXAMPLES OF ST9 PERIPHERAL CONFIGURATIONS (Continued) ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** ;*Configuration of TIMER 0 I/O pins and A/D Converter I/O pins* proc INIT_IO [PPR] { ;. . .. . .... ;. . .. . .... P3.0 (T0INA) P3.2 (T0INB) INPUT TRISTATE TTL ;. . .. . .... P3.1 (T0OUTA) P3.3 (T0OUTB) OUTPUT ALTERNATE FUNCTION PUSH_PULL TTL spp #P3C_PG ; Port 3 control register page ld ld ld P3C0R,#00001111b P3C1R,#00001010b P3C2R,#0 0 0101b
;. . .. . .... end of init. P3 ;. . .. . .... INITIALIZATION OF A/D CONVERTOR INPUTS ;. . .. . .... P4.7 (AIN7) ALTERNATE FUNCTION OPEN DRAIN TTL ;. . .. . .... P4.6 (AIN6) ALTERNATE FUNCTION OPEN DRAIN TTL spp ld ld ld #P4C_PG P4C0R,#110 0 00b P4C1R,#110 0 00b P4C2R,#110 0 00b ; Port 4 control register page
;. . .. . ... end of init. P4 ;. . .. . ... INITIALIZATION OF SCI I/O ; P70: Input = Sin. ; P71: AF = Sout. ; P72: AF = Txclck. ; P73: AF = Rxclck. spp ld ld ld } #P7C_PG P7C0R,#00001111b P7C1R,#11111110b P7C2R,#0 0 0001b ; Port 7 control page. ; bit 0 (Sin): IN, TRI, TTL. ; bit 1,2,3 (Sout, Txck, Rxck): AF,PP,TTL. ; Others : OUT,PP,TTL.
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APPENDIX B. EXAMPLES OF ST9 PERIPHERAL CONFIGURATIONS (Continued) ;* * ** * ** * ** * ** * ** * ** * ** * ** * * ;*SECTION CODE FOR THE CORE INTERRUPT ROUTINE* ;* * ** * ** * ** * ** * ** * ** * ** * ** * * ;------------------------------------;*INTERRUPT ROUTINE FOR ZERO DIVISION* ;------------------------------------DIV0: nop ret ;------------------------------------ ;*INTERRUPT ROUTINE FOR TOP_LEVEL_IT* ;------------------------------------ TOP_LEVEL_IT: nop iret ;------------------------------------------ ;*INTERRUPT ROUTINE FOR TIMER WATCHDOG INT* ;------------------------------------------ TEMPO: nop iret
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APPENDIX C. EXAMPLES OF TIMER 0 CONFIGURATIONS ;* * ** * ** * ** * **** ;*DEFINE TIMER 0 MACROS* ;* * ** * ** * ** * **** .macroT0_START_IT ; start timer 0, enable interrupts spp #T0D_PG ; select Timer 0 data register page and T_TCR,#ccl ; counter clear bit or T_TCR,#cen ; counter enable bit or T_IDMR,#gtien ; global interrupt mask .endm .macroT0_START_DMA_CAP spp or or .endm .macroSTOP_T0 spp and and .endm ; ; ; ; stop Timer 0 select Timer 0 data register page global interrupt mask counter enable bit
; start timer 0, enable interrupts ; and DMA #T0D_PG ; select Timer 0 data register page T_IDMR,#( gtien | cp0d ) ; global interrupt mask T_TCR,#cen ; counter enable bit
#T0D_PG T_IDMR,#gtien T_TCR,#cen
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APPENDIX C. EXAMPLES OF TIMER 0 CONFIGURATIONS (Continued) ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * * proc GEST_T0_ITCAPT{ ;Configuration of Timer 0 for IT CAPTURE ;TCR: - stop count ; - clear on capture ; - up count ;TMR: - disable output ; - internal clock ; - disable bivalue mode ; - disable retrigger mode ; - disable REG1 mode ; - continuous mode ; - enable REG0 mode ;ICR: - EXTA Trigger ; - falling edge on EXTA ; - EXTB No Operation ;OACR-OBCR: - no operation ;IDMR: - Interrupt on capture REG0 ;DCPR: - reset value ;DAPR: - 00h ;IVR: - Interrupt vector 10h = T0_IT_VECT ;IDCR: - level 4 spp #T0D_PG ; Timer 0 data register page ld T_TCR,#01001000b ; TCR ld T_TMR,#00001010b ; TMR ld T_ICR,#01010100b ; ICR ld T_PRSR,prescal_t0 ; PRESCALER ld T_OACR,#11111100b ; OACR ld T_OBCR,#11111100b ; OBCR ld T_FLAGR,#00h ; FLAGR ld T_IDMR,#0010 0 0b ; IDMR spp #T0C_PG ; Timer 0 control register page ld T0_DCPR,#00h ; DCPR ld T0_DAPR,#0 ; DAPR ld T0_IVR,#T0_IT_VECT ; IVR interrupt vector 14h ld T0_IDCR,#IT_T0_LEVEL ; priority level 4 T0_START_IT } ; start Timer 0, enable interrupt
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APPENDIX C. EXAMPLES OF TIMER 0 CONFIGURATIONS (Continued) ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** proc GEST_T0_EVENT{ ; Configuration of Timer 0 into EVENT COUNTER MODE ; IT COMPARE is serviced when nb_event_t0 is reached ;TCR: ; ; ;TMR: ; ; ; ; ; ;ICR: ; ; ;OACR-OBCR: ;FLAG: ;IDMR: ;DCPR: ;DAPR: ;IVR: ;IDCR: ;COMP0 spp ldw ld ld ld ld ld ld ld #T0D_PG T_CMP0R,nb_event_t0 T_TCR,#00111000b T_TMR,#0 0 0010b T_ICR,#01000010b T_PRSR,prescal_t0 T_OACR,#11111100b T_OBCR,#11111100b T_IDMR,#0 0 0100b Stop count Up count Clear on compare Disable output 0-1 no Bivalue mode no Bicapture Internal clock Disable retrigger mode Continuous mode EXTB Ext.Clock Falling edge on EXTB EXTA I/O No operation reset value IT compare 0 00h 00h interrupt vector 10h = T0_IT_VECT priority level 4
; Timer 0 data register page ; COMP0 ; ; ; ; ; ; ; TCR TMR ICR PRESCALER OACR OBCR IDMR
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INITIALIZATION OF THE ST9
APPENDIX C. EXAMPLES OF TIMER 0 CONFIGURATIONS (Continued) spp #T0C_PG ld T0_DCPR,#0 ld T0_DAPR,#0 ld T0_IVR,#T0_IT_VECT ld T0_IDCR,#IT_T0_LEVEL T0_START_IT } ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** proc GEST_T0_DMA{ ;Configuration of Timer0 in IT CAPTURE associated to the DMA mode ;the length of DMA is given by lg_dma ;TCR: ; ; ;TMR: ; ; ; ; ; ;ICR: ; ; ;OACR-OBCR: ;IDMR: ;DCPR: ;DAPR: ;IVR: ;IDCR: spp ld ld ld ld ld ld Stop count no clear Up count disable interrupt no bivalue mode no capture external/internal clock disable retrigger mode continuous count EXTA TRIGGER Falling edge on EXTA EXTA no operation no operation no interrupt, DMA / CAPTURE REG0 DMA ext. data/program memory - DMA counter DMA external program memory - DMA address interrupt vector 10h = T0_IT_VECT interrupt dma priority level 4 ; ; ; ; ; ; ; select Timer 0 data register TCR TMR ICR PRESCALER OACR OBCR ; ; ; ; ; Timer 0 control register page DCPR DAPR IVR IDCR
#T0D_PG T_TCR,#01001000b T_TMR,#00001010b T_ICR,#01010100b T_PRSR,prescal_t0 T_OACR,#11111100b T_OBCR,#11111100b
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APPENDIX C. EXAMPLES OF TIMER 0 CONFIGURATIONS (Continued) ld ld spp ld ld ld ld ldw ldw T_FLAGR,#00h T_IDMR,#0010 0 0b #T0C_PG T0_DCPR,#CPT_LG_DMA T0_DAPR,#CPT_AD_DMA T0_IVR,#T0_IT_VECT T0_IDCR,#IT_T0_LEVEL CPT_LG_DMA,lg_dma CPT_AD_DMA,#0ff00h ; ; ; ; ; ; ; ; ; FLAGR IDMR select Timer 0 control register DCPR lg. DMA = 4ch = rr12 = RR76 DAPR ad. DMA = 48h = rr8 = RR72 IVR priority level 4
; init DMA counter ; DMA address in ROM is 0FF00h ; enable Interrupt. and DMA
T0_START_DMA_CAP
} ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; Example for Timer 0 and Timer 1 in parallel mode ; A Toggle is generated on T0OUTB and T1OUTB on each overflow ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ;* * ** * ** * **** ;initialize TIMER 0 ;* * ** * ** * **** TIMER0:: spp srp ld ld
#T0D_PG #BK_F t_tcr,#00011000b t_tmr,#10001000b
; select timer 0 register page ; select working register ; ; ; ; ; ; ; ; ; ; Counter clear Software Up Enable output 1 Disable output 0 Not bivalue mode REG 1 monitor counter value REG 0 Capture Internal clock Retrigger mode Continuous mode
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INITIALIZATION OF THE ST9
APPENDIX C. EXAMPLES OF TIMER 0 CONFIGURATIONS (Continued)
ld
t_icr,#00 ld t_prsr,#00 ld t_oacr,#11111100b ld t_obcr,#11110100b ld t_flagr,#00 ld t_idmr,#00
; ; ; ;
No action on input pins No prescaling No action on OUTPUT0 Toggle on OVF
.macroT0_START spp #T0D_PG or t_tcr,#cen .endm
; Start TIMER 0 ; select Timer 0 data register page ; counter enable bit
;* * ** * ** * **** ;initialize TIMER 1 ;* * ** * ** * **** TIMER1:: spp srp ld
#T1D_PG #BK_F t_tcr,#00011000b
; select timer 1 register page ; select working register ; Counter clear ; Software Up ; ; ; ; ; ; ; ; ; ; ; ; Enable output 1 Disable output 0 Not bivalue mode REG 1 monitor counter value REG 0 Capture Parallel mode Retrigger mode Continuous mode No action on input pins No prescaling No action on T1OUTA Toggle on OVF T1OUTB
ld
t_tmr,#10001100b
ld ld ld ld ld ld
t_icr,#00 t_prsr,#00 t_oacr,#11111100b t_obcr,#11110100b t_flagr,#00 t_idmr,#00
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INITIALIZATION OF THE ST9
APPENDIX C. EXAMPLES OF TIMER 0 CONFIGURATIONS (Continued) .macroT1_START spp and or .endm or loop ; Start ; ; ; TIMER 1 select Timer 1 data register page counter clear bit counter enable bit
#T1D_PG t_tcr,#ccl t_tcr,#cen
CICR,#10 0 000b { }
; Global counter enable
;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** ; INTERRUPT SUBROUTINES FOR TIMER 0 ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** ;These subroutines are serviced on TIMER 0 Interrupts. They come from: ; T0_IT_VECT + 4 for both - IT/CAPTURE ; and - DMA IT/CAPTURE end of block ; T0_IT_VECT + 6 for - IT/COMPARE
;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** ; Timer 0 CAPTURE Interrupt subroutine: ; - IT Capture on event on EXTA ; - DMA IT/CAPTURE end of block T0_CAP: spp tm jxz
#T0D_PG T_FLAGR,#ccp0 RESET_START
; Timer 0 data register page ; mask successful capture ; this is not an IT CAPTURE ; == Pb ; overrun on Capture 0 ? ; yes == RESET ; reset successful capture flags ; reset overrun on capture 0 flag ; return from interrupt
tm T_FLAGR,#ocp0 jxnz RESET_START and T_FLAGR,#~cp0 and T_FLAGR,#~ocp0 iret
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INITIALIZATION OF THE ST9
APPENDIX C. EXAMPLES OF TIMER 0 CONFIGURATIONS (Continued) ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * *** ;Timer 0 COMPARE interrupt subroutine: ; - IT / COMPARE T0_COMP: spp tm jxz #T0D_PG T_FLAGR,#cm0 RESET_START ; Timer 0 data register page ; mask successful compare ; RESET if it is not ; an IT COMPARE ; overrun on Compare 0 ? ; yes == RESET ; reset successful compare bit ; reset overrun compare 0 bit ; return from interrupt
tm T_FLAGR,#ocm0 jxnz RESET_START and and iret T_FLAGR,#~cm0 T_FLAGR,#~ocm0
;* * **** END OF TIMER 0 CONFIGURATION EXAMPLES * * ** * ***
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INITIALIZATION OF THE ST9
APPENDIX D. EXAMPLES OF A/D CONVERTOR CONFIGURATIONS ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** proc SG_CONV{ ; A/D Converter is configured as follows: ; - one shot conversion ; - power up mode ; - IT upon End of Conversion ; - Start mode ; - Autoscan from channel number AD_CONV ; - No INT upon Analog Compare spp ld #AD0_PG AD_CLR,#0 0 0100b ; A/D converter register page ; ; ; ; ; ; ; ; ; ; ; Control logic register power up Stop Single mode Channel 0 Compare result register Interrupt control register mask analog watchdog enable end of conversion Priority level = 6 Interrupt vector register
ld ld
AD_CRR,#00h AD_ICR,#0010 0 0b
or ld ld swap rcf rlc or
AD_ICR,#IT_CAD_LEVEL AD_IVR,#ADC_IT_VECT r0,ad_conv r0 r0 AD_CLR,r0
; AD_CONV = channel number
; mask for channel number ; start conversion address
ld R10, #40 loop [R10] { nop } or } AD_CLR,#st
; wait 60s before start the first ; conversion
; start conversion
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INITIALIZATION OF THE ST9
APPENDIX D. EXAMPLES OF A/D CONVERTOR CONFIGURATIONS (Continued) ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** ; A/D END OF CONVERSION INTERRUPT SUBROUTINE ADC_EOC: spp
#AD0_PG
; A/D converter register page ; converter flags ; ; ; ; end of conversion pending flag analog watch_dog pending flag stop converter power down mode
and and iret
AD_ICR,#~(ecv | awd) AD_CLR,#~(st | pow )
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APPENDIX E. EXAMPLES OF SCI CONFIGURATIONS ;* * ** * ** * ** * **** ; SCI ;constant declarations. ;* * ** * ** * ** * **** PRIORITY_SCI = 4 DIV_9600 = 78 DIV_4800 DIV_2400 DIV_1200 VC_9600 Return = LNG_DMA_SCI DEPART_DMA_SCI = = = := 00dh := := 156 312 614 4 0Fh 0A0h
; ; ; ; ; ;
SCI priority level BRG divisor for a 9600 baud clock with a 12 MHz system clock. To generate a 4800 bds clock. To generate a 2400 bds clock. To generate a 1200 bds clock.
; Character for 9600 bauds. ; DMA length. ; Start DMA address . ; BK_DMA_SCI reserved for this. ; Contains DMA transmit address pointer value. ; Contains DMA transmit address counter value. ; data hold register
NUM_TDAP NUM_TDCP data rec_ptr rec_cpt
:= := := := :=
6 7 r2 rr6 rr8
;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; function: ; - I/O ports initialization. ; - Speed and frame initialization. ; - Compare register initialization. ; - Interrupt and DMA configuration. ; ; Interrupt request: ; - Receive error. ; - Receiver data. ; - end of DMA transmit. ; ; inputs: none ; ; outputs:none ;
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APPENDIX E. EXAMPLES OF SCI CONFIGURATIONS (Continued) ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** proc INIT_SCI { ;--- Communication format configuration. ; ; Communication format is configured as follows: ; ; - 8 data bit transmitted or received character. ; - 1 stop bit included in data format. ; - Parity even. ; - 9600 Baud communication rate. ;--- SCI configuration. ; ; - No address bit included between the parity bit and the stop bit. ; - Address mode: Address interrupt if character match. ; - DMA permits transmission from EEPROM memory to serial line. ; - Receiver data interrupt unmask (to detect a received data item). ; - Transmitter data interrupt unmask (to detect DMA end of block). ; - Receiver error interrupt unmask (to detect overrun, parity or framing error). spp srp ld ld #SCI1_PG ; SCI register page. #BK_F ; To address SCI registers with r. s_brglr,#00 ; Reset SCI s_chcr,#( wl8 | sb10 ; ; ; ; ; ; s_ccr,#txclk | pen | ep | am ) 8 data bit. 1 stop bit. Parity even. No address bit. AME = 0, AM = 1. = IT if character match.
ld
; Xmit clock source = BRG. ; Receiver clock source = BRG. ; 16x asynchronous mode. ; End Of Command acquisition.
ld
s_acr,#RETURN
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INITIALIZATION OF THE ST9
APPENDIX E. EXAMPLES OF SCI CONFIGURATIONS (Continued) ;--- Interrupt and DMA configuration. ld ld ld s_ivr,#SCI_IT ; Interrupt vector register. s_tdcpr,#NUM_TDCP ; Tx DMA counter in register file. s_imr,#( rxdi | rxa | rxe ) ; Mask Transmitter data interrupt. ; Unmask Receiver data interrupt. ; Unmask Receiver data error interrupt. ; Unmask Receiver address interrupt. ; Reset of the pending bits. s_idpr,#PRIORITY_SCI s_brglr,#DIV_9600 ; ; ; ; ; Mask transmitter DMA request. SCI exeptions priority level. BRG divisor for 9600 bauds, start SCI !!! with a 24 Mhz external clock, !!! or 4800 Bds (12 MHz external clock.)
ld ld
} ;--- end of proc. ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** ; SYNC_COM: proc SYNC_COM { spp #SCI1_PG srp #BK_F ld R#NUM_TDAP,#(DEPART_DMA_SCI) ld R#NUM_TDCP,#(LNG_DMA_SCI) or s_idpr,#txd
; DMA pointer initialisation. ; DMA counter initialisation. ; Unmask transmitter DMA request. ; unmask transmitter data interrupt.
ld s_imr,#txdi ; Unmask Transmitter data interrupt. ; Mask Receiver data interrupt. ; Mask Receiver data error interrupt. } ;--- End of proc.
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APPENDIX E. EXAMPLES OF SCI CONFIGURATIONS (Continued) * * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** ; REC_DATA: Receive interrupt. REC_DATA: pushu PPR ; save page pointer. pushuw RPP ; save register pointer pair. spp srp ld and #SCI1_PG #BK_SCI data,S_RXBR data,#07Fh ; SCI register page. ; 16 registers reserved for SCI. ; Read the data received. ; Mask the parity bit. ; Storage of the received data. ; End of the table. ; Reset receiver data pending flag. ; restore register pointer pair ; restore page pointer
ld rec_ptr(rec_cpt),data incw rec_cpt cpw rec_cpt,#7 and S_ISR,#~rxdp RPP PPR
popuw popu iret
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APPENDIX E. EXAMPLES OF SCI CONFIGURATIONS (Continued) ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * **** ; TRA_HOLD: End of DMA transmitter Interrupt ; Function: ; - Check Interrupt source. ; - Disable DMA mask . ; - Enable Receiver interrupt mask. TRA_HOLD: pushu pushuw spp srp tm if PPR RPP ; save page pointer. ; save register pointer pair. ; SCI register page. ; To address SCI registers with r. ; If a Transmitter End Of Block interrupt. ; Dis. Transmit end of block pending bit. ; Reset transmit holding reg. empty . rxe) ; Unmask Receiver data interrupt. ; Unmask Receiver data error interrupt. ; Mask Transmitter data interrupt. ; If not a normal interrupt source.
#SCI1_PG #BK_F s_imr,#txeob [SETZ] { bres S_txeob bres S_txhem ld s_imr,#~( rxdi |
} else { jx RESET_START } ;--- end of if. popuw popu iret RPP PPR
; restore register pointer pair ; restore page pointer
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APPENDIX F. EXAMPLES OF WATCHDOG TIMER CONFIGURATIONS ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** ;INIT_WDT: This procedure initializes and starts Watchdog Timer. ; ; Watchdog mode is disabled. ; Timer will down count in continuous mode. ; It will generate an interrupt on channel A0 at each End Of Count. ; --- See the external interrupt parameters initialization. ;* * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ** * ***** proc INIT_WDT { spp ld clr ldw or #WDT_PG wcr,#wden wdtpr WDTR,#3003 wdtcr,#stsp ; ; ; ; ; ; ; ; ; ; ; ; To access in paged registers with r. watch dog mode dis., no wait states. 333 ns(sys.clock=12 MHz) min. count, prescaler = 0. (3003 X 333) ns = 1 ms. Timer starts down counting. Continuous mode. Watch Dog disabled. Input section disabled. Output disabled. Interrupt A0 on Timer EOC. Top Level Interrupt on SW TRAP.
};--- End of proc. ;* * ** * ** * ** * ** * ** * ** * ** * * ;*Interrupt on channel A0 initialization* ;* * ** * ** * ** * ** * ** * ** * ** * * spp #WDT_PG srp #BK_F ; page 0 reg. direct addressing mode. clr nop ld eipr eivr,#EXT_IT_VECT ; ; ; ; ; Dis. all external int. pending bits. See WARNING (Tech. manual-Chap. 8). External interrupt vector. IAOS - TLIS = 00 = ... ... A0 int. will be on WDT End Of Count.
ld ld
eiplr,#0FEh eimr,#ia0sm ; Priority level: group INTA0,INTA1 = 4,5. ; Unmask Interrupt A0 channel ; (WDT End Of Count).
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