M48T08 M48T08Y, M48T18
5 V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM
Features
Integrated ultra low power SRAM, real-time clock, power-fail control circuit, and battery BYTEWIDETM RAM-like clock access BCD coded year, month, day, date, hours, minutes, and seconds Typical clock accuracy of 1 minute a month, at 25C Automatic power-fail chip deselect and write protection Write protect VPFD = Power-fail deselect voltage): M48T08: VCC = 4.75 to 5.5 V 4.5 V VPFD 4.75 V M48T18/T08Y: VCC = 4.5 to 5.5 V 4.2 V VPFD 4.5 V
SNAPHAT (SH) battery/crystal
28 1
PCDIP28 (PC) battery/crystal CAPHATTM
Software controlled clock calibration for high accuracy applications Self-contained battery and crystal in the CAPHATTM DIP package Packaging includes a 28-lead SOIC and SNAPHAT top (to be ordered separately) SOIC package provides direct connection for a snaphat top which contains the battery and crystal Pin and function compatible with DS1643 and JEDEC standard 8 K x 8 SRAMs RoHS compliant Lead-free second level interconnect
SOH28 (MH)
28 1
February 2009
Rev 9
1/31
www.st.com 1
Contents
M48T08, M48T08Y, M48T18
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-fail interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 3.2 3.3 3.4 3.5 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 5 6 7 8 9
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
M48T08, M48T08Y, M48T18
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PCDIP28 28-pin plastic DIP, battery CAPHATTM, package mech. data . . . . . . . . . . . . . 23 SOH28 28-lead plastic SO, 4-socket battery SNAPHAT, package mech. data. . . . . . . 24 SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package mech. data . . . . . 25 SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, package mech. data . . . . 26 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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List of figures
M48T08, M48T08Y, M48T18
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write enable controlled, write AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip enable controlled, write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PCDIP28 28-pin plastic DIP, battery CAPHATTM, package outline . . . . . . . . . . . . . . . . . 23 SOH28 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline . . . 24 SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline. . . . . . . . . 25 SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, package outline. . . . . . . . 26 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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M48T08, M48T08Y, M48T18
Description
1
Description
The M48T08/18/08Y TIMEKEEPER RAM is an 8 K x 8 non-volatile static RAM and real time clock which is pin and functional compatible with the DS1643. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard 8 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28-pin, 600 mil DIP CAPHATTM houses the M48T08/18/08Y silicon with a quartz crystal and a long-life lithium button cell in a single package. The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4T28-BR12SH" or "M4T32-BR12SH" (see Table 17 on page 28). Figure 1. Logic diagram
VCC
13 A0-A12
8 DQ0-DQ7
W E1 E2 G
M48T08 M48T08Y M48T18
INT
VSS
AI01020
5/31
Description Table 1.
A0-A12 DQ0-DQ7 INT E1 E2 G W VCC VSS
M48T08, M48T08Y, M48T18 Signal names
Address inputs Data inputs / outputs Power fail interrupt (open drain) Chip enable 1 Chip enable 2 Output enable WRITE enable Supply voltage Ground
Figure 2.
DIP connections
INT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48T08 8 M48T18 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
AI01182
6/31
M48T08, M48T08Y, M48T18 Figure 3. SOIC connections
INT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48T08Y 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
Description
AI01021B
Figure 4.
Block diagram
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
8 x 8 BiPORT SRAM ARRAY
A0-A12
8184 x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
DQ0-DQ7
E1 E2 W G
VCC
INT
VSS
AI01333
7/31
Operation modes
M48T08, M48T08Y, M48T18
2
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM READ/WRITE memory cells. The M48T08/18/08Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the battery backup switchover voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2.
Mode Deselect Deselect WRITE READ READ Deselect Deselect VSO to VPFD(min)(1) VSO(1) 4.75 to 5.5 V or 4.5 to 5.5 V
Operating modes
VCC E1 VIH X VIL VIL VIL X X E2 X VIL VIH VIH VIH X X G X X X VIL VIH X X W X X VIL VIH VIH X X DQ0-DQ7 High Z High Z DIN DOUT High Z High Z High Z Power Standby Standby Active Active Active CMOS standby Battery backup mode
1. See Table 11 on page 22 for details.
Note:
X = VIH or VIL ; VSO = Battery backup switchover voltage.
2.1
Read mode
The M48T08/18/08Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripplethrough access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1, E2 and G access times are not met, valid data will
8/31
M48T08, M48T08Y, M48T18
Operation modes
be available after the latter of the chip enable access times (tE1LQV or tE2HQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E1, E2 and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E1, E2 and G remain active, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access. Figure 5. Read mode AC waveforms
tAVAV A0-A12 tAVQV tE1LQV E1 tE1LQX tE2HQV E2 tE2HQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00962
VALID tAXQX tE1HQZ
tE2LQZ
tGHQZ
Note:
WRITE enable (W) = high.
9/31
Operation modes Table 3. Read mode AC characteristics
M48T08, M48T08Y, M48T18
M48T08/M48T18/T08Y Symbol Parameter(1) 100/10 (T08Y) Min tAVAV tAVQV tE1LQV tE2HQV tGLQV tE1LQX tE2HQX tGLQX tE1HQZ tE2LQZ tGHQZ tAXQX READ cycle time Address valid to output valid Chip enable 1 low to output valid Chip enable 2 high to output valid Output enable low to output valid Chip enable 1 low to output transition Chip enable 2 high to output transition Output enable low to output transition Chip enable 1 high to output Hi-Z Chip enable 2 low to output Hi-Z Output enable high to output Hi-Z Address transition to output transition 5 10 10 5 50 50 40 5 100 100 100 100 50 10 10 5 75 75 60 Max 150/15 (T08Y) Min 150 150 150 150 75 Max ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note:
Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2.2
Write mode
The M48T08/18/08Y is in the WRITE mode whenever W, E1, and E2 are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of tE1HAX or tE2LAX from chip enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; however, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs tWLQZ after W falls.
10/31
M48T08, M48T08Y, M48T18 Figure 6. Write enable controlled, write AC waveform
tAVAV A0-A12 VALID tAVWH tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH tWHQX
Operation modes
tWHAX
AI00963
Figure 7.
Chip enable controlled, write AC waveforms
tAVAV A0-A12 VALID tAVE1H tAVE1L E1 tE1LE1H tE1HAX
tAVE2L tAVE2H E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L tE2HE2L tE2LAX
AI00964B
11/31
Operation modes Table 4. Write mode AC characteristics
M48T08, M48T08Y, M48T18
M48T08/M48T18/T08Y Symbol Parameter(1) 100/10 (T08Y) Min tAVAV tAVWL tAVE1L tAVE2H tWLWH tE1LE1H t E2HE2L tWHAX tE1HAX tE2LAX tDVWH tDVE1H tDVE2L tWHDX tE1HDX tE2LDX tWLQZ tAVWH tAVE1H tAVE2L tWHQX WRITE cycle time Address valid to WRITE enable low Address valid to chip enable 1 low Address valid to chip enable 2 high WRITE enable pulse width Chip enable 1 low to chip enable 1 high Chip enable 2 high to chip enable 2 low WRITE enable high to address transition Chip enable 1 high to address transition Chip enable 2 low to address transition Input valid to WRITE enable high Input valid to chip enable 1 high Input valid to chip enable 2 low WRITE enable high to input transition Chip enable 1 high to input transition Chip enable 2 low to input transition WRITE enable low to output Hi-Z Address valid to WRITE enable high Address valid to chip enable 1 high Address valid to chip enable 2 low WRITE enable high to output transition 80 80 80 10 100 0 0 0 80 80 80 10 10 10 50 50 50 5 5 5 50 130 130 130 10 Max 150/15 (T08Y) Min 150 0 0 0 100 130 130 10 10 10 70 70 70 5 5 5 70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2.3
Data retention mode
With valid VCC applied, the M48T08/18/08Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "Don't care."
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T08/18/08Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended.
12/31
M48T08, M48T08Y, M48T18
Operation modes
When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T08/18/08Y for an accumulated period of at least 10 years when VCC is less than VSO. Note: Requires use of M4T32-BR12SH SNAPHAT top when using the SOH28 package. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max). For more information on battery storage life refer to the application note AN1012.
2.4
Power-fail interrupt pin
The M48T08/18/08Y continuously monitors VCC. When VCC falls to the power-fail detect trip point, an interrupt is immediately generated. An internal clock provides a delay of between 10 s and 40 s before automatically deselecting the M48T08/18/08Y. The INT pin is an open drain output and requires an external pull-up resistor, even if the interrupt output function is not being used.
13/31
Clock operations
M48T08, M48T08Y, M48T18
3
3.1
Clock operations
Reading the clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, the seventh bit in the control register. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'
3.2
Setting the clock
The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (on Table 5). Resetting the WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. See the application note AN923, "TIMEKEEPER rolling Into the 21st century" for information on century rollover.
14/31
M48T08, M48T08Y, M48T18 Table 5.
Address D7 1FFFh 1FFEh 1FFDh 1FFCh 1FFBh 1FFAh 1FF9h 1FF8h 0 0 0 0 0 ST W R D6 D5 D4 D3 D2 D1 Year 10 M Month Date 0 Day Hours Minutes Seconds Calibration D0 10 years 0 0 FT 0 0
Clock operations
Register map
Data Function/range BCD format Year Month Date Day Hours Minutes Seconds Control 00-99 01-12 01-31 01-07 00-23 00-59 00-59
10 date 0 0
10 hours 10 minutes 10 seconds S
Note:
S = SIGN bit FT = FREQUENCY TEST bit (set to '0' for normal clock operation) R = READ bit W = WRITE bit ST = STOP bit 0 = Must be set to '0'
3.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit (ST) is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T08/18/08Y (in the PCDIP28 package) is shipped from STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T08/18/08Y oscillator starts within one second.
Note:
To guarantee oscillator startup after initial power-up, first write the STOP bit (ST) to '1,' then reset to '0.'
3.4
Calibrating the clock
The M48T08/18/08Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. A typical M48T08/18/08Y is accurate within 1 minute per month at 25C without calibration. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T08/18/08Y improves to better than +1/2 ppm at 25C. The oscillation rate of any crystal changes with temperature. Figure 8 on page 17 shows the frequency error that can be expected at various temperatures. Most clock chips compensate for crystal frequency and temperature shift error with cumbersome "trim" capacitors. The M48T08/18/08Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9 on page 17. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into
15/31
Clock operations
M48T08, M48T08Y, M48T18
the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration byte occupies the five lower order bits in the control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or 2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T08/18/08Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of standard test equipment. When the frequency test (FT) bit, the seventh-most significant bit in the day register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the seconds register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a 10 (WR001010) to be loaded into the calibration byte for correction. Note: Setting or changing the calibration byte does not affect the frequency test output frequency. The device must be selected and addresses must be stable at address 1FF9h when reading the 512 Hz on DQ0. The LSB of the seconds register is monitored by holding the M48T08/18/08Y in an extended READ of the seconds register, but without having the READ bit set. The FT bit MUST be reset to '0' for normal clock operations to resume. For more information on calibration, see the application note AN934, "TIMEKEEPER calibration."
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M48T08, M48T08Y, M48T18 Figure 8. Crystal accuracy across temperature
ppm 20
Clock operations
0
-20
-40 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C -80
-60
-100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 C
AI02124
Figure 9.
Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
3.5
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 F (as shown in Figure 10) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
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Clock operations
M48T08, M48T08Y, M48T18
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 10. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48T08, M48T08Y, M48T18
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Symbol TA TSTG TSLD(1)(2)(3) VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltages Supply voltage Output current Power dissipation Value 0 to 70 40 to 85 260 0.3 to 7 0.3 to 7 20 1 Unit C C C V V mA W
1. For DIP package: soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). 2. For SO package, standard (SnPb) lead finish: reflow at peak temperature of 225C (the time above 220C must not exceed 20 seconds). 3. For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260C (the time above 255C must not exceed 30 seconds).
Caution: Caution:
Negative undershoots below 0.3 V are not allowed on any pin while in the battery backup mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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DC and AC parameters
M48T08, M48T08Y, M48T18
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M48T08 4.75 to 5.5 0 to 70 100 5 0 to 3 1.5 M48T18/T08Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 Unit V C pF ns V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 11. AC testing load circuit
5V
1.8k DEVICE UNDER TEST 1k
OUT
CL = 100pF
CL includes JIG capacitance
AI01019
Table 8.
Symbol CIN CIO(3)
Capacitance
Parameter(1)(2) Input capacitance Input / output capacitance Min M ax 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. At 25C, f = 1 MHz. 3. Outputs deselected.
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M48T08, M48T08Y, M48T18 Table 9.
Symbol ILI ILO(2) ICC ICC1
(3)
DC and AC parameters
DC characteristics
Parameter Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output low voltage (INT)(4) IOL = 2.1 mA IOL = 0.5 mA IOH = 1 mA 2.4 Test condition(1) 0V VIN VCC 0V VOUT VCC Outputs open E1 = VIH, E2 = VIL E1 = VCC 0.2V, E2 = VSS + 0.2V 0.3 2.2 M48T08/M48T18/T08Y Unit Min Max 1 1 80 3 3 0.8 VCC + 0.3 0.4 0.4 A A mA mA mA V V V V V
ICC2(3) VIL VIH VOL VOH
Output high voltage
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. Outputs deselected. 3. Measured with control bits set as follows: R = '1'; W, ST, FT = '0.' 4. The INT pin is open drain.
Figure 12. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD tFB tPFX INT trec INPUTS
RECOGNIZED
tDR tRB
tR
tPFH
DON'T CARE
NOTE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00566
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
21/31
DC and AC parameters Table 10.
Symbol tPD tF
(2)
M48T08, M48T08Y, M48T18 Power down/up AC characteristics
Parameter(1) E1 or W at VIH or E2 at VIL before power-down VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time E1 or W at VIH or E2 at VIL before power-up INT low to auto deselect VPFD (max) to INT high Min 0 300 10 0 1 1 10 40 120 Max Unit s s s s s ms s s
tFB(3) tR tRB trec tPFX tPFH
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11.
Symbol VPFD VSO tDR
Power down/up trip points DC characteristics
Parameter(1)(2) Power-fail deselect voltage M48T08 M48T18/T08Y Min 4.5 4.2 10(3) Typ 4.6 4.3 3.0 Max 4.75 4.5 Unit V V V Years
Battery backup switchover voltage Expected data retention time
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 3. At 55C, VCC = 0 V; tDR = 8.5 years (typ) at 70C. Requires use of M4T32-BR12SH SNAPHAT top when using the SOH28 package.
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M48T08, M48T08Y, M48T18
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 13. PCDIP28 28-pin plastic DIP, battery CAPHATTM, package outline
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Note:
Drawing is not to scale. Table 12.
Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150
PCDIP28 28-pin plastic DIP, battery CAPHATTM, package mech. data
mm inches
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Package mechanical data
M48T08, M48T08Y, M48T18
Figure 14. SOH28 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note:
Drawing is not to scale. Table 13. SOH28 28-lead plastic SO, 4-socket battery SNAPHAT, package mech. data
mm Symb Typ A A1 A2 B C D E e eB H L a N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 0.142 0.500 0.050 8 inches
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M48T08, M48T08Y, M48T18
Package mechanical data
Figure 15. SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 14. SH 4-pin SNAPHAT housing for 48 mAh battery & crystal, package mech. data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
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Package mechanical data
M48T08, M48T08Y, M48T18
Figure 16. SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 15. SH 4-pin SNAPHAT housing for 120 mAh battery & crystal, package mech. data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 .0335 0.315 0.015 0.022 0.860 .0710 0.628 0.142 0.090 inches
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M48T08, M48T08Y, M48T18
Part numbering
7
Part numbering
Table 16.
Example:
Ordering information scheme
M48T 18 100 PC 1 E
Device type M48T Supply voltage and write protect voltage 08(1) = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V 18/08Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V Speed 100 = 100 ns 150 = 150 ns 10 = 100 ns (M48T08Y) Package PC(1) = PCDIP28 MH(2) = SOH28 Temperature range 1 = 0 to 70C Shipping method For SOH28: blank = Tubes (not for new design - use E) E = ECOPACK package, tubes F = ECOPACK package, tape & reel TR = Tape & reel (not for new design - use F) For PCDIP28: blank = ECOPACK package, tubes
1. The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHATTM) package only. 2. The SOIC package (SOH28) requires the SNAPHAT battery/crystal package which is ordered separately under the part number "M4TXX-BR12SH" in plastic tube or "M4TXX-BR12SHTR" in tape & reel form (see Table 17). The M48T08Y part is offered in the SOH28 (SNAPHAT) package only.
Caution:
Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Part numbering Table 17. SNAPHAT battery table
Description Lithium battery (48 mAh) SNAPHAT Lithium battery (120 mAh) SNAPHAT
M48T08, M48T08Y, M48T18
Part number M4T28-BR12SH M4T32-BR12SH
Package SH SH
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M48T08, M48T08Y, M48T18
Environmental information
8
Environmental information
Figure 17. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Please refer to the following web site address for additional information regarding compliance statements and waste recycling. Go to www.st.com/rtc, then select "Lithium Battery Recycling" from "Related Topics".
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Revision history
M48T08, M48T08Y, M48T18
9
Revision history
Table 18.
Date Dec-1999 07-Feb-2000 11-Jul-2000 16-Jul-2001 01-Aug-2001 21-Dec-2001 06-Mar-2002 20-May-2002 29-Aug-2002 28-Mar-2003 10-Dec-2003 30-Mar-2004 13-Dec-2005 04-Jul-2007 10-Feb-2009
Document revision history
Revision 1 2 2.1 3 3.1 3.2 3.3 3.4 3.5 4 5 6 7 8 9 First Issue From Preliminary Data to Datasheet; Battery Low Flag paragraph changed; 100ns speed class identifier changed (Table 3, 4) tFB changed (Table 10); Watchdog Timer paragraph changed Reformatted; SNAPHAT battery table added (Table 17); added temp./voltage info. to tables (Table 8, 9, 3, 4, 10, 11). Reference to App. Note corrected in "Calibrating the Clock" section Changes to text in document to reflect addition of M48T08Y option Fix Ordering Information table and add to footnote (Table 16) Modify reflow time and temperature footnotes (Table 6) tDR specification temperature updated (Table 11) v2.2 template applied; updated test conditions (Table 10) Reformatted Reformatted; Lead-free (Pb-free) information package update (Table 6, 16) Updated template, Lead-free information, removed footnote (Table 9, 16) Reformatted; added lead-free second level interconnect information to cover page and Section 6: Package mechanical data. Updated Table 6, text in Section 6: Package mechanical data; added Section 8: Environmental information; minor formatting changes. Changes
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M48T08, M48T08Y, M48T18
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