ST20-GP6
GPS PROCESSOR
FEATURES
Figure 1. Package
Application specific features · 12 channel GPS correlation DSP hardware, ST20 CPU (for control and position calculations) and memory on one chip · no TCXO required · RTCA-SC159 / WAAS / EGNOS supported GPS performance · accuracy - stand alone with SA on <100m, SA off <30m - differential <1m - surveying <1cm · time to first fix - autonomous start 90s - cold start 45s - warm start 7s - obscuration 1s Enhanced 32-bit VL-RISC CPU - C2 core · 16/33/50 MHz processor clock · 25 MIPS at 33 MHz · fast integer/bit operations 64 Kbytes on-chip SRAM 128 Kbytes on-chip ROM Programmable memory interface · 4 separately configurable regions · 8/16-bits wide · support for mixed memory · 2 cycle external access Programmable UART (ASC) Parallel I/O Vectored interrupt subsystem Diagnostic control unit Power management · low power operation · power down modes Professional toolset support · ANSI C compiler/link driver and libraries · Debugging/profiling and simulation tools Technology · Static clocked 50 MHz design · 3.3 V, sub micron technology 100 pin PQFP package JTAG Test Access Port
PQFP100
Table 1. Order Codes
Part Number ST20GP6X33S Package PQFP100
Figure 2. Block Diagram
GPS radio
bs O
let o
Pr e
du o
(s) ct
Ob -
so
te le
ro P
uc d
ST20 CPU
s) t(
ST20-GP6
12 channel GPS hardware DSP
Low power controller Real time clock/calendar
Interrupt controller
Serial communications 2 UART (ASC)
Programmable memory interface
Parallel input/output Diagnostic control unit
. 16 . .
64K SRAM
128K optional mask ROM
Test access port
APPLICATIONS
Global Positioning System (GPS) receivers Car navigation systems Fleet management systems Time reference for telecom systems
Rev. 2 1/123
October 2004
ST20-GP6
Contents
1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST20-GP6 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
5 7 11
DSP module registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 13
4
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 4.2 4.3 4.4 4.5 4.6 Registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... Processes and concurrency . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... Priority . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... Process communications . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... Timers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... Traps and exceptions . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....
19
19 20 22 23 23 24
5
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 5.2 5.3 5.4 5.5 5.6 Interrupt vector table . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . Interrupt handlers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . Interrupt latency . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... Preemption and interrupt priority . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. Restrictions on interrupt handlers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . Interrupt configuration registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....
6
Interrupt level controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 6.2
Interrupt assignments . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 37 Interrupt level controller registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 37
7
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 7.2 7.3
8
bs O
8.1 8.2 8.3 9.1 9.2
Instruction cycles . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 40 Instruction characteristics . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 41 Instruction set tables . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 42
let o
ro P e
uc d
(s) t
so Ob -
eP let
ro
uc d
s) t(
30
31 31 32 32 33 33
37
40
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
System memory use . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 51 Boot ROM . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 52 Internal peripheral space . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 52
9
Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
SRAM . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 55 ROM . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 55
2/123
ST20-GP6 10 Programmable memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1 10.2 10.3 10.4 10.5 10.6 EMI signal descriptions . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. External accesses . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... MemWait . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... EMI configuration registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . Boot source . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... Default configuration . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .
56
58 59 60 62 65 65
11 Low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 11.2
66
Low power control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 66 Low power configuration registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 67
12 Real time clock and watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 12.2 12.3 12.4 Power supplies . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... Real time clock . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... Watchdog timer . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... RTC/WDT configuration registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .
70
70 70 70 71
13 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1 13.2 13.3
Reset, initialization and debug . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 73 Bootstrap . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 73 Clocks . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 73
14 Diagnostic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.1 14.2 14.3 14.4 14.5 14.6 Diagnostic hardware . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . Access features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... Software debugging features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... Controlling the diagnostic controller . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... Peeking and poking the host from the target . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... Abortable instructions . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....
15 UART interface (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bs O
16.1
15.1 15.2 15.3 15.4 15.5
Functionality . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... Timeout mechanism . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . Baud rate generation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... Interrupt control . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... ASC configuration registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
73
75
75 76 77 79 80 80
82
82 85 85 86 88
16 Parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
PIO Ports0-1 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ... 94
17 Configuration register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
3/123
ST20-GP6 18 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19 GPS Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
19.1 19.2 Accuracy . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... 106 Time to first fix . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... 107
20 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
20.1 20.2 20.3 20.4 20.5 EMI timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... Reset timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. PIO timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..... ClockIn timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .... JTAG IEEE 1149.1 timings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 108 110 111 112 113
21 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 22 Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
22.1 22.2 ST20-GP6 package pinout . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . 116 100 pin PQFP package dimensions . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. 119
23 Test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 24 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 25 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
4/123
ST20-GP6
1
Introduction
The ST20-GP6 is an application-specific single chip micro using the ST20 CPU with microprocessor style peripherals added on-chip. It incor porates DSP hardware for processing the signals from GPS (Global Positioning System) satellites. The twelve channel GPS correlation DSP hardware is designed to handle twelve satellites, two of which can be initialized to suppor t the RTCA-SC159 specification for WAAS (Wide Area Augmentation Ser vice) and EGNOS (European Geostationar y Navigation Overlay System) services. The ST20-GP6 has been designed to minimize system costs and reduce the complexity of GPS systems. It offers all hardware DSP and microprocessor functions on one chip and provides sufficient on-chip RAM and ROM. The entire analogue section, RF and clock generation are available on a companion chip. Thus, a complete GPS system is possible using just two chips, see Figure 1.1.
Antenna ST20-GP6 STB5600 Radio Single chip DSP ASIC
Low cost cr ystal No TCXO
bs O
let o
Pr e
du o
(s) ct
so Ob CPU Watchdog timer RAM
te le
UART Parallel I/O Real time clock
ro P
uc d
s) t(
Driver (optional)
Parallel I/O
optional mask ROM
Figure 1.1 GPS system
The ST20-GP6 suppor ts large values of frequency offset, allowing the use of a very low cost oscillator, thus saving the cost of a Temperature Controlled Crystal Oscillator (TCXO). The CPU and software have access to the par t-processed signal to enable accelerated acquisition time.
5/123
ST20-GP6 The ST20-GP6 can implement the GPS digital signal processing algorithms using less than 50% of the available CPU processing power. This leaves the rest available for integrating OEM application functions such as route-finding, map display and telemetr y. A hardware microkernel in the ST20 CPU suppor ts the sharing of CPU time between tasks without an operating system or executive overhead. The architecture is based on the ST20 CPU core and suppor ting macrocells developed by STMicroelectronics. The ST20 micro-core family provides the tools and building blocks to enable the development of highly integrated application specific 32-bit devices at the lowest cost and fastest time to market. The ST20 macrocell librar y includes the ST20Cx family of 32-bit VL-RISC (variable length reduced instruction set computer) micro-cores, embedded memories, standard peripherals, I/O, controllers and ASICs. The ST20-GP6 uses the ST20 macrocell librar y to provide the hardware modules required in a GPS system. These include: · · · · · · · · DSP hardware Dual channel UART for serial communications Two parallel I/O modules providing 16 bits of parallel I/O Interrupt controller Real time clock/calendar and watchdog timer 128 Kbytes of on-chip ROM for application code
64 Kbytes of on-chip RAM, of which 16 Kbytes is battery backed
Diagnostic control unit and test access port for development support
The ST20-GP6 is suppor ted by a range of software and hardware development tools for PC and UNIX hosts including an ANSI-C ST20 software toolset and the ST20 INQUEST window based debugging toolkit.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
6/123
ST20-GP6
2
ST20-GP6 architecture overview
The ST20-GP6 consists of an ST20 CPU plus application specific DSP hardware for handling GPS signals, plus a dual channel UART, ROM and RAM memor y, parallel IO, real time clock and watchdog functions. Figure 2.1 shows the subsystem modules that comprise the ST20-GP6. These modules are outlined below and more detailed information is given in the following chapters. DSP The ST20-GP6 includes DSP hardware for processing signals from the GPS satellites. The DSP module generates the pseudo-random noise (prn) signals, and de-spreads the incoming signal. It consists of a down conversion stage that takes the 4 MHz input signal down to nominally zero frequency both in-phase and quadrature (I & Q). This is followed by 12 parallel hardware channels for satellite tracking, whose output is passed to the CPU for fur ther software processing at a programmable interval, nominally every millisecond. CPU The Central Processing Unit (CPU) on the ST20-GP6 is the ST20 32-bit processor core. It contains instruction processing logic, instruction and data pointers, and an operand register. It directly accesses the high speed on-chip memor y, which can store data or programs. The processor can access up to 4 Mbytes of memory via the programmable memory interface.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
7/123
ST20-GP6
GPS radio ST20-GP6
12 channel GPS hardware DSP
ST20 CPU
Interrupts
Interrupt controller Low power controller Real time clock
Serial communications 2 UART
Parallel input/output
Programmable memor y interface
bs O
let o
128K ROM
Pr e
du o
64K SRAM
(s) ct
so Ob -
eP let
od r
. . . 16
uc
s) t(
User position output in ASCII
Diagnostic control unit
Test access por t
System ser vices
Reset Clock
Figure 2.1 ST20-GP6 architectural block diagram Memory subsystem The ST20-GP6 on-chip memor y system provides 60 Mbytes/s internal data bandwidth, suppor ting pipelined 2-cycle internal memor y access at 30 ns cycle times. The ST20-GP6 memor y system consists of SRAM, ROM and a programmable external memory interface (EMI).
8/123
ST20-GP6 The ST20-GP6 can use 8 or 16-bit external RAM, 8 or 16-bit external ROM, and has a 20-bit address bus. The ST20-GP6 product has 64 Kbytes of on-chip SRAM. This is in 4 banks of 16 Kbytes. One of these banks is powered from the back-up batter y supply. The ST20-GP6 has 128 Kbytes of ROM for application code. The ST20-GP6 memor y interface controls the movement of data between the ST20-GP6 and offchip memory. It is designed to suppor t memor y subsystems without any external suppor t logic and is programmable to suppor t a wide range of memor y types. Memor y is divided into 4 banks which can each have different memor y characteristics and each bank can access up to 1 Mbyte of external memory. The normal memor y provision in a simple GPS receiver is a single 64K x 16-bit ROM or Flash ROM (70, 90 or 100 ns access time). The internal 64 Kbyte RAM is sufficient for application use, however for development pur poses external RAM may be added. The ST20-GP6 can suppor t up to 1 Mbyte of SRAM plus 1 Mbyte of ROM, enabling additional functions to be added if required. Low power controller, real time clock and watchdog timer The ST20-GP6 has power-down capabilities configurable in software. When powered down, a timer can be used as an alarm, re-activating the CPU after a programmed delay. This is suitable for ultra low power or solar powered applications such as container tracking, railway truck tracking, or marine navigation buoys that must check they are on station at intervals. There is also a watchdog timer (WDT), resetting the system if it times out. The watchdog timer function is enabled by an external pin (WdEnable). The WDT has a counter, clocked to give a nominal 2 second delay. A status flag (notWdReset) is set by a watchdog reset. This can be used to indicate to application code that the system was reset by the watchdog timer. The real time clock (RTC) provides a set of continuously running counters to provide a clockcalendar function. The counter values can be written to set the current time/data. The RTC is clocked by a 32,768 Hz crystal oscillator and has a separate power supply so that it can continue to run when the rest of the chip is powered down. The RTC contains two counters: a 30-bit `milliseconds' counter and a 16-bit `weeks' counter. This allows large time values to be represented to high accuracy. Note that the milliseconds counter is actually clocked at 1.024 KHz and this must be handled by software. The ST20-GP6 is designed for 0.35 micron, 3.3 V CMOS technology and runs at speeds of up to 50 MHz. 3.3 V operation provides reduced power consumption internally and allows the use of low power peripherals. In addition, a power-down mode is available on the ST20-GP6. The different power levels of the ST20-GP6 are listed below.
bs O
· · ·
Operating power -- power consumed during functional operation. Stand-by power -- power consumed during little or no activity. The CPU is idle but ready to immediately respond to an interrupt/reschedule. Power-down -- clocks are stopped and power consumption is significantly reduced. Functional operation is stalled. Normal functional operation can be resumed from previous state as soon as the clocks are stable. No information is lost during power down as all internal logic is static.
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
9/123
ST20-GP6 · Power to most of the chip removed -- only the real time clock supply (RTCVDD) power on.
In power-down mode the processor and all peripherals are stopped, including the external memor y controller and optionally the PLL. Effectively the internal clock is stopped and functional operation is stalled. On restart the clock is restarted and the chip resumes normal functional operation. Serial communications The ST20-GP6 has two UARTs (Asynchronous Serial Controllers (ASCs)) for serial communication. The UARTs provide an asynchronous serial interface and can be programmed to suppor t a range of baud rates and data formats, for example, data size, stop bits and parity. Interrupt subsystem The ST20-GP6 interrupt subsystem suppor ts eight prioritized interrupts. Four interrupts are connected to on-chip peripherals (2 for the UARTs, 2 for the programmable IO), two are available as external interrupt pins and two are spare. Each interrupt level has a higher priority than the previous and each level suppor ts only one software handler process. Note that interrupt handlers must not prevent the GPS DSP data traffic from being handled. During continuous operation this has 1 ms latency and is not a problem, but during initial acquisition it has a 32 s rate and thus all interrupts must be disabled except if used to stop GPS operation. Parallel IO module Sixteen bits of parallel IO are provided. Each bit is programmable as an output or an input. Edge detection logic is provided which can generate an interrupt on any change of an input bit. JTAG Test Access Port Diagnostic controller The Test Access Port (TAP) supports the IEEE 1149.1 JTAG test standard. The diagnostic controller is a programmable module which connects directly into the CPU. It can be accessed by the TAP. This allows debugging systems to be used which do not affect CPU performance or intrude into application code. Debugging support includes: · · · hardware breakpoint and watchpoint real time trace external LSA triggering support
It is also used to provide system services, including booting the CPU. System services module The ST20-GP6 system services module includes: · · reset and initialization port. phase locked loop (PLL) -- accepts 16.368 MHz input and generates all the internal high frequency clocks needed for the CPU.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
10/123
ST20-GP6
3
Digital signal processing module
The ST20-GP6 chip includes 12 channel GPS correlation DSP hardware. It is designed to handle twelve satellites, two of which can be initialized to support the RTCA-SC159 specification. The digital signal processing (DSP) module extracts GPS data from the incoming IF (Intermediate Frequency) data. There are a number of stages of processing involved; these are summarized below and in Figure 3.1. After the 12 pairs of hardware correlators, the data for all channels are time division multiplexed onto the appropriate internal buses (i.e. values for each channel are passed in sequence, for example: I1, Q1, I2, Q2 ... I12, Q12, I1, Q1).
4 MHz IF input data sampler
frequency conver ter A
I correlator (x 12) Q correlator (x 12)
frequency conver ter B
accumulator
DMA interface
Pseudo random noise sequence generator (x 12)
Numerically controlled oscillator
ST20 CPU accessible registers
The main stages of processing are as follows: Data sampling This stage removes any meta-stability caused by the asynchronous input data coming from an analogue source (the radio receiver). The data at this point consists of a carrier of nominally 4.092 MHz with a bandwidth of approximately 1 MHz. This stage is common to all 12 channels.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Figure 3.1 DSP module block diagram
11/123
ST20-GP6 Frequency conversion (A) The first frequency conver ter mixes the sampled IF data with the (nominal) 4.092 MHz signal. This is done twice with a quar ter cycle offset to produce I and Q (In-phase and Quadrature) versions of the data at nominal zero centre frequency (this can actually be up to 132 KHz due to errors such as doppler shift, crystal accuracy, etc.). The sum frequency (~8 MHz) is removed by low-pass filtering in the correlator. This stage is common to all 12 channels. Correlation against pseudo-random sequence The GPS data is transmitted as a spread-spectrum signal (with a bandwidth of about 2 MHz). In order to recover the data it is necessar y to correlate against the same Pseudo-Random Noise (PRN) signal that was used to transmit the data. The output of the correlator accumulator is sampled at 264 KHz. The PRN sequences come from the PRN generator. There is a correlator for the I and Q signals for each of the 12 channels. The output signal is now narrowband. Frequency conversion (B) The second stage of frequency conversion mixes the data with the local oscillator signal generated by the Numerically Controlled Oscillator (NCO). This signal is locked, under software control, to the Space Vehicle (SV) frequency and phase to remove the errors and take the frequency and bandwidth of the data down to 0 and 50 Hz respectively. Filtering to 500 Hz is achieved in hardware, to 50 Hz in software. This stage is shared by time division multiplexing between all 12 channels. This is loss-free as the stage supports 12 channels x 264 KHz, approximately 3 MHz, well within its 16 MHz clock rate. Result integration The final stage sums the I and Q values for each channel over a user defined period. In normal operation, the sampling period is slightly less than the 1ms length of the PRN sequence. This ensures that no data is lost, although it may mean that some data samples are seen twice -- this is handled (mainly) in software. The sampling period can also be programmed to be much shor ter (i.e. a higher cut-off frequency for the filter) when the system is trying to find new satellites (`acquisition mode'). There are two fur ther stages of buffering for the accumulated 16-bit I and Q values for each channel. These allow for the slightly different time domains involved1. The results after hardware processing of the signal, using the parameters set in the DSP registers, refer to Section 3.1, are delivered to the CPU via a DMA engine in packet format. The CPU should perform an in (input) instruction on the appropriate channel (see address map, Figure 8.1 on page 53) in order to read a packet. The format of the 62-byte packets is given in Figure 3.2. These represent a two byte header, followed by the 16-bit I-values for 12 channels, then the 16-bit Q-values for 12 channels, then the 8-bit timestamp values for the 12 channels. The I and Q values are sent least significant byte first. The 2
1. Data sampled in SV time, data transmitted to the CPU at fixed intervals.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
12/123
ST20-GP6 byte header contains: a `sync' byte with the value #1B, and a `sample rate' byte which contains the two SampleRate bits from the DSPControl register, see Table 3.1. Packets are delivered at the rate selected by the DSPControl register, even if new data is not available. In this case, the data value for the field is set to #8000. This guarantees that synchronism is maintained between the satellite one-millisecond epochs and the receiver, despite time-of-reception variations due to the varying path length from the satellite.
62 byte packet every 840/970/31/62 s 12 x 16-bit I values 16-bit header 12 x 16-bit Q values 12 x 8-bit time values
Absent 16-bit values padded with #8000
sync
sample rate
Tracking mode T[7:6] = 10 T[5:0] = time[5:0]
Acquisition mode
3.1
1 2 3
DSP module registers
DSPControl register
The GPS hardware channels of the ST20-GP6 are controlled by three sets of registers:
bs O
let o
Pr e
du o
Figure 3.2 DSP packet format
(s) ct
so Ob -
te le
ro P
First packet (in SV ms) T[7:6] = 10 T[5:0] = time[5:0] Remaining packets T[7:6] = 00 T[5:0] = sequence number (sequence numbers are 2 to 16 or 32)
uc d
s) t(
PRNcode0-11 and PRNphase0-11 registers NCOfrequency0-11 and NCOphase0-11 registers
The base addresses for the DSP registers are given in the Memory Map chapter. DSPControl register The DSPControl register determines whether the PRN generators are on (normal use) or disabled (for built-in-self-test of a system), whether the system is in tracking mode (840/970 s output rate) or initial acquisition mode (31/62 s), and selects which of the two rates for each mode. It also
13/123
ST20-GP6 determines whether the accumulated carrier phase in the NCO are reset to zero automatically or continue from their existing value. The bit allocations are given in Table 3.1.
DSPControl Bit 1:0 Bit field SampleRate
DSP base address + #140 Function
Write only
These bits control the sampling rate (the rate at which data is sent to the DMA controller). The encoding of these bits is as follows: SampleRate[1:0] 00 01 10 11 Transfer period 840 s 970 s 31 s 62 s No. of samples accumulated 256 256 8 16 Acquisition Mode Tracking
2 3
NCOResetEnable PRNDisable
When set to 1, the accumulated NCO phase for a channel is reset when the corresponding PRN code register is written. When set to 1, all PRN generators are disabled.
Table 3.1 DSPControl register format PRNcode0-11 registers
The PRNcode0-11 registers choose the code for the par ticular satellite, and writing these causes a reset to the accumulated carrier phase in the NCO for the corresponding channel, if enabled by the DSPControl register.
PRNcode0-11 Bit 6:0 Bit field PRNcode DSP base address + #00 to #2C
The bit-fields for selecting particular GPS satellites are given in Table 3.3.
bs O
let o
Pr e
du o
Function
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Write only
Satellite code as a 7-bit value.
Table 3.2 PRNcode0-11 register format
14/123
ST20-GP6 PRNcode0-11
register value #62 #73 #04 #15 #11 #22 #01 #12 #23 #32 #43 #65 #76 #07 #18 #29 #41 #52 #63 #74 #05 #16 #31 #64 #75 #06 #17 #28 #61 #72 #03 #14 #25 #24 #71 #02 #24 #20 Taps selected from G2 shift registera by bits 6 to 4 6 7 8 9 9 10 8 9 10 3 4 6 7 8 9 10 4 5 6 7 8 9 3 6 7 8 9 10 6 7 8 9 10 10 7 8 10 10 by bits 3 to 0 2 3 4 5 1 2 1 2 3 2 3 5 6 7 8 9 1 2 3 4 5 6 1 4 5 6 7 8 1 2 3 4 5 4 1 2 4 0
Satellite ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 -
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
WAASb
Table 3.3 PRNcode0-11 register value
a. Refer to the US DoD document ICD-GPS-200. b. It is the responsibility of the software to ensure that when this value is selected, a suitable value has been written into the PRNinitialVal0-1 register. If this channel is later used for a standard GPS satellite, the PRNinitialVal0-1 must be set to all ones (#3FF).
For channels 0 and 1, RTCA-SC159 satellite codes can also be selected. This is achieved by setting the PRNcode0-11 register appropriately and also writing the initial value for the satellite to the
15/123
ST20-GP6 PRNinitialVal0-1 register, see Table 3.8. If uninitialized by the software, the PRNinitialVal register defaults to 11 1111 1111 (#3FF) as required for GPS satellites. The PRNcode0-11 and PRNinitialVal0-1 registers are normally written only when the satellite is first chosen. PRNphase0-11 registers The PRN0-11phase registers determine the relative delay between the receiver master clock, and the star t of the one millisecond repetitive code sequence. The code sequence star ts when the receiver clock counter (invisible to the software except through message timestamps) reaches the value written to the PRNphase0-11 register. The PRNphase0-11 register must only be written once per satellite milliseconds-epoch, which varies from the receiver epoch dynamically due to satellite motion. Synchronism with the software is achieved by reading the register, when a write enable flag is returned. If not enabled, the write operation is abandoned by the software. The 19-bit value comprises three fields. The 3 least significant bits represent the fractional-delay in eighths of a code-chip. The middle 10 bits represent the integer delay in code-chips, 0-1022, with the value 1023 illegal. The upper 6 most significant bits represent the delay in integer milliseconds.
PRNphase0-11 Bit 2:0 12:3 18:13 Bit field FractionalDelay IntegerDelay Delay DSP base address + #40 to #6C Function Fractional delay in eighths of a code-chip.
Integer delay in code-chips. Value 0-1022. Note, the value 1023 is illegal. Delay in integer milliseconds.
Table 3.4 PRNphase0-11 register format Note also that the eighth-chip resolution of the code generator is not sufficient for positioning. At 125 ns it represents approximately 40 m of range, over 100 m of position. The software must maintain the range measurements around the 1 ns resolution level in a 32-bit field, and send an appropriate 19-bit sub-field to the register. Note, care must be taken when calculating this field from a computed delay, or vice versa, to allow for the missing value 1023. The overall register bit-field cannot be used mathematically as a single binary number. PRNphase0-11WrEn registers The PRNphase0-11WrEn flags are active low flags that record when the PRNphase0-11 register can be updated. The PRNphaseWrEn flag for a channel is set high when the corresponding PRNphase register is written. The flag is reset again when the value written is loaded into the PRN gen-
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Write only
16/123
ST20-GP6 erator. Note, the PRNphase0-11 register should only be updated when the PRNphase0-11WrEn register has been cleared by the hardware.
PRNphase0-11WrEn Bit 0 Bit field PRNphaseWrEn DSP base address + #40 to #6C Function Set when the corresponding PRNphase0-11 register is set. Read only
Table 3.5 PRNphase0-11WrEn register format NCOfrequency0-11 registers The NCOfrequency0-11 registers hold a signed 18-bit value that is added repetitively, ignoring overflows, to the accumulated NCO phase from which the NCO sine and cosine waveforms are generated. The addition is performed at a 264 KHz rate (16.368MHz/62). The accumulated NCO phase is not accessible to the software, but can be cleared when initialising the channel if enabled by the DSPControl register. Each unit value in 1.007080078125 Hz. the NCOfrequency0-11 register represents 264KHz/(218),
If the extreme values are written, #1FFFF and #20000, the sine wave generated will be at approximately +132 KHz, and precisely -132 KHz respectively.
NCOfrequency0-11 Bit 17:0 Bit field NCOfrequency DSP base address + #80 to #AC Function
NCO frequency as a signed 18-bit value.
Table 3.6 NCOfrequency0-11 register format NCOphase0-11 registers
The NCOphase0-11 registers contents are added to the accumulated phase to correct the carrier for the final 1 Hz that cannot be resolved by the NCO frequency. This addition is not cumulative, and the value must be updated regularly by the software as a result of carrier phase errors measured on the satellite signal. The register holds a signed 7-bit field representing +/-180 degrees total in steps of 2.8125 degrees (360/128).
NCOphase0-11 Bit
6:0
O
bs
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
i.e.
Write only
DSP base address + #C4 to #EC Function
Write only
Bit field NCOphase
NCO phase as a signed 7-bit value representing +/-180 degrees total in steps of 2.8125 degrees (360/128).
Table 3.7 NCOphase0-11 register format
17/123
ST20-GP6 PRNinitialVal0-1 registers The initial value for the two RTCA-SC159 capable satellites channels should be written to the PRNinitialVal0-1 registers. The value can be found in the RTCA-SC159 Specification. Note: The value written to the register is the Initial Value defined by RTCA-SC159 for the PRN required. The conversion from `big-endian' as used in the specification to `little-endian' as conventionally used in ST20 architectures has been implemented in the hardware. If uninitialized by the software, this register defaults to 11 1111 1111 (#3FF) as required for GPS satellites.
PRNinitialVal0-1 Bit 9:0 Bit field InitialValue DSP base address + #100, #104 Function Initial value of the RTCA-SC159 satellite channel. Write only
Table 3.8 PRNinitialVal0-1 register format
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
18/123
ST20-GP6
4
Central processing unit
The Central Processing Unit (CPU) is the ST20 32-bit processor core. It contains instruction processing logic, instruction and data pointers, and an operand register. It can directly access the high speed on-chip memor y, which can store data or programs. Where larger amounts of memor y are required, the processor can access memory via the External Memory Interface (EMI). The processor provides high performance: · · · · · Fast integer multiply - 4 cycle multiply Fast bit shift - single cycle barrel shifter Byte and part-word handling Scheduling and interrupt support 64-bit integer arithmetic support.
The scheduler provides a single level of pre-emption. In addition, multi-level pre-emption is provided by the interrupt subsystem, see Chapter 5 for details. Additionally, there is a per-priority trap handler to improve the support for arithmetic errors and illegal instructions, refer to section 4.6.
4.1
Registers
The CPU contains six registers which are used in the execution of a sequential integer process. The six registers are: · · · · The workspace pointer (Wptr) which points to an area of store where local data is kept. The instruction pointer (Iptr) which points to the next instruction to be executed. The status register (Status). The Areg, Breg and Creg registers which form an evaluation stack.
The Areg, Breg and Creg registers are the sources and destinations for most arithmetic and logical operations. Loading a value into the stack pushes Breg into Creg, and Areg into Breg, before loading Areg. Storing a value from Areg, pops Breg into Areg and Creg into Breg. Creg is left undefined.
O
bs
let o
Pr e
Areg Breg Creg Wptr Iptr
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Registers
Local data
Program
Figure 4.1 Registers used in sequential integer processes
19/123
ST20-GP6 Expressions are evaluated on the evaluation stack, and instructions refer to the stack implicitly. For example, the add instruction adds the top two values in the stack and places the result on the top of the stack. The use of a stack removes the need for instructions to explicitly specify the location of their operands. No hardware mechanism is provided to detect that more than three values have been loaded onto the stack; it is easy for the compiler to ensure that this never happens. Note that a location in memor y can be accessed relative to the workspace pointer, enabling the workspace to be of any size. The use of shadow registers provides fast, simple and clean context switching.
4.2
Processes and concurrency
The following section describes `default' behavior of the CPU and it should be noted that the user can alter this behavior, for example, by disabling timeslicing, installing a user scheduler, etc. A process star ts, performs a number of actions, and then either stops without completing or terminates complete. Typically, a process is a sequence of instructions. The CPU can run several processes in parallel (concurrently). Processes may be assigned either high or low priority, and there may be any number of each. The processor has a microcoded scheduler which enables any number of concurrent processes to be executed together, sharing the processor time. This removes the need for a software kernel, although kernels can still be written if desired. At any time, a process may be
active
-
being executed, interrupted by a higher priority process, on a list waiting to be executed. waiting to input, waiting to output, waiting until a specified time.
inactive
The scheduler operates in such a way that inactive processes do not consume any processor time. Each active high priority process executes until it becomes inactive. The scheduler allocates a portion of the processor's time to each active low priority process in turn (see section 4.3). Active processes waiting to be executed are held in two linked lists of process work spaces, one of high priority processes and one of low priority processes. Each list is implemented using two registers, one of which points to the first process in the list, the other to the last. In the linked process list shown in Figure 4.2, process S is executing and P, Q and R are active, awaiting execution. Only the low priority process queue registers are shown; the high priority process ones behave in a similar manner.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
20/123
ST20-GP6
Registers FptrReg1 BptrReg1 Areg Breg Creg Wptr Iptr
Local data P Q R S Iptr.s Link.s Iptr.s Link.s Iptr.s
Program
Figure 4.2 Linked process list
Function Pointer to front of active process list Pointer to back of active process list High priority FptrReg0 BptrReg0 Low priority
Table 4.1 Priority queue control registers
Each process runs until it has completed its action or is descheduled. In order for several processes to operate in parallel, a low priority process is only permitted to execute for a maximum of two timeslice periods. After this, the machine deschedules the current process at the next timeslicing point, adds it to the end of the low priority scheduling list and instead executes the next active process. The timeslice period is 1ms. There are only cer tain instructions at which a process may be descheduled. These are known as descheduling points. A process may only be timesliced at cer tain descheduling points. These are known as timeslicing points and are defined in such a way that the operand stack is always empty. This removes the need for saving the operand stack when timeslicing. As a result, an expression evaluation can be guaranteed to execute without the process being timesliced part way through. Whenever a process is unable to proceed, its instruction pointer is saved in the process workspace and the next process taken from the list. The processor core provides a number of special instructions to suppor t the process model, including star tp (star t process) and endp (end process). When a main process executes a parallel construct, star tp is used to create the necessar y additional concurrent processes. A star tp instruction creates a new process by adding a new workspace to the end of the scheduling list, enabling the new concurrent process to be executed together with the ones already being executed. When a process is made active it is always added to the end of the list, and thus cannot pre-empt processes already on the same list. The correct termination of a parallel construct is assured by use of the endp instruction. This uses a data structure that includes a counter of the parallel construct components which have still to ter-
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
FptrReg1
BptrReg1
uc d
s) t(
21/123
ST20-GP6 minate. The counter is initialized to the number of components before the processes are star ted. Each component ends with an endp instruction which decrements and tests the counter. For all but the last component, the counter is non zero and the component is descheduled. For the last component, the counter is zero and the main process continues.
4.3
Priority
The following section describes `default' behavior of the CPU and it should be noted that the user can alter this behavior, for example, by disabling timeslicing and priority interrupts. The processor can execute processes at one of two priority levels, one level for urgent (high priority) processes, one for less urgent (low priority) processes. A high priority process will always execute in preference to a low priority process if both are able to do so. High priority processes are expected to execute for a shor t time. If one or more high priority processes are active, then the first on the queue is selected and executes until it has to wait for a communication, a timer input, or until it completes processing. If no process at high priority is active, but one or more processes at low priority are active, then one is selected. Low priority processes are periodically timesliced to provide an even distribution of processor time between tasks which use a lot of computation. If there are n low priority processes, then the maximum latency from the time at which a low priority process becomes active to the time when it star ts processing is the order of 2n timeslice periods. It is then able to execute for between one and two timeslice periods, less any time taken by high priority processes. This assumes that no process monopolizes the time of the CPU; i.e. it has frequent timeslicing points. The specific condition for a high priority process to star t execution is that the CPU is idle or running at low priority and the high priority queue is non-empty. If a high priority process becomes able to run while a low priority process is executing, the low priority process is temporarily stopped and the high priority process is executed. The state of the low priority process is saved into `shadow' registers and the high priority process is executed. When no fur ther high priority processes are able to run, the state of the interrupted low priority process is reloaded from the shadow registers and the interrupted low priority process continues executing. Instructions are provided on the processor core to allow a high priority process to store the shadow registers to memor y and to load them from memor y. Instructions are also provided to allow a process to exchange an alternative process queue for either priority process queue (see Table 7.21 on page 49). These instructions allow extensions to be made to the scheduler for custom run-time kernels. A low priority process may be interrupted after it has completed execution of any instruction. In addition, to minimize the time taken for an interrupting high priority process to star t executing, the potentially time consuming instructions are interruptible. Also some instructions may be abor ted, and are restarted when the process next becomes active (refer to the Instruction Set chapter).
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
22/123
ST20-GP6
4.4
Process communications
Communication between processes takes place over channels, and is implemented in hardware. Communication is point-to-point, synchronized and unbuffered. As a result, a channel needs no process queue, no message queue and no message buffer. A channel between two processes executing on the same CPU is implemented by a single word in memory; a channel between processes executing on different processors is implemented by pointto-point links. The processor provides a number of operations to suppor t message passing, the most important being in (input message) and out (output message). The in and out instructions use the address of the channel to determine whether the channel is internal or external. This means that the same instruction sequence can be used for both hard and soft channels, allowing a process to be written and compiled without knowledge of where its channels are implemented. Communication takes place when both the inputting and outputting processes are ready. Consequently, the process which first becomes ready must wait until the second one is also ready. The inputting and outputting processes only become active when the communication has completed. A process performs an input or output by loading the evaluation stack with, a pointer to a message, the address of a channel, and a count of the number of bytes to be transferred, and then executing an in or out instruction.
4.5
Timers
There are two 32-bit hardware timer clocks which `tick' periodically. These are independent of any on-chip peripheral real time clock. The timers provide accurate process timing, allowing processes to deschedule themselves until a specific time. One timer is accessible only to high priority processes and is incremented approximately ever y microsecond, cycling completely in approximately 4295 seconds. The other is accessible only to low priority processes and is incremented approximately ever y 64 microseconds, giving 15625 ticks per second. It has a full period of approximately 76 hours. Timer frequencies are approximate.
Register
ClockReg0
bs O
let o
ClockReg1 TnextReg0 TnextReg1 TptrReg0 TptrReg1
Pr e
Function
Current value of high priority (level 0) process clock. Current value of low priority (level 1) process clock. Indicates time of earliest event on high priority (level 0) timer queue. Indicates time of earliest event on low priority (level 1) timer queue. High priority timer queue. Low priority timer queue.
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Table 4.2 Timer registers The current value of the processor clock can be read by executing a ldtimer (load timer) instruction. A process can arrange to perform a tin (timer input), in which case it will become ready to execute after a specified time has been reached. The tin instruction requires a time to be specified. If this time is in the `past' then the instruction has no effect. If the time is in the `future' then the process is descheduled. When the specified time is reached the process becomes active. In addition, the
23/123
ST20-GP6
ldclock (load clock), stclock (store clock) instructions allow total control over the clock value and the clockenb (clock enable), clockdis (clock disable) instructions allow each clock to be individually stopped and re-started.
Figure 4.3 shows two processes waiting on the timer queue, one waiting for time 21, the other for time 31.
Work spaces ClockReg0 5 Comparator TnextReg0 21 Alarm 21 Program
TptrReg0
Empty
Figure 4.3 Timer registers
4.6
Traps and exceptions
A software error, such as arithmetic overflow or array bounds violation, can cause an error flag to be set in the CPU. The flag is directly connected to the ErrorOut pin. Both the flag and the pin can be ignored, or the CPU stopped. Stopping the CPU on an error means that the error cannot cause fur ther corruption. As well as containing the error in this way it is possible to determine the state of the CPU and its memor y at the time the error occurred. This is par ticularly useful for postmor tem debugging where the debugger can be used to examine the state and histor y of the processor leading up to and causing the error condition. In addition, if a trap handler process is installed, a variety of traps/exceptions can be trapped and handled by software. A user supplied trap handler routine can be provided for each high/low process priority level. The handler is star ted when a trap occurs and is given the reason for the trap. The trap handler is not re-entrant and must not cause a trap itself within the same group. All traps can be individually masked. 4.6.1 Trap groups The trap mechanism is arranged on a per priority basis. For each priority there is a handler for each group of traps, as shown in Figure 4.4.
bs O
let o
Pr e
du o
(s) ct
so Ob -
31
te le
ro P
uc d
s) t(
24/123
ST20-GP6
Low priority traps
High priority traps
CPU Error trap handler Breakpoint trap handler
Scheduler trap handler
CPU Error trap handler Breakpoint trap handler
Scheduler trap handler
System operations trap handler
System operations trap handler
Figure 4.4 Trap arrangement There are four groups of traps, as detailed below. · Breakpoint This group consists of the Breakpoint trap. The breakpoint instruction (j0) calls the breakpoint routine via the trap mechanism. · Errors The traps in this group are IntegerError and Overflow. Overflow represents arithmetic overflow, such as arithmetic results which do not fit in the result word. IntegerError represents errors caused when data is erroneous, for example when a range checking instruction finds that data is out of range. · System operations , and traps. The IllegalOpcode This group consists of the trap is signalled when an attempt is made to execute an illegal instruction. The LoadTrap and StoreTrap traps allow a kernel to intercept attempts by a monitored process to change or examine trap handlers or trapped process information. It enables a user program to signal to a kernel that it wishes to install a new trap handler. · Scheduler The scheduler trap group consists of the ExternalChannel, InternalChannel, Timer, TimeSlice, Run, Signal, ProcessInterrupt and QueueEmpty traps. The ProcessInterrupt trap signals that the machine has performed a priority interrupt from low to high. The QueueEmpty trap indicates that there is no fur ther executable work to perform. The other traps in this group indicate that the hardware scheduler wants to schedule a process on a process queue, with the different traps enabling the different sources of this to be monitored.
bs O
let o
od Pr e
soIllegalOpcode LoadTrap StoreTrap Ob )t(s uc
te le
ro P
uc d
s) t(
The scheduler traps enable a software scheduler kernel to use the hardware scheduler to implement a multi-priority software scheduler. Note that scheduler traps are different from other traps as they are caused by the microscheduler rather than by an executing process.
Trap groups encoding is shown in Table 4.3 below. These codes are used to identify trap groups to various instructions.
25/123
ST20-GP6
Trap group Breakpoint CPU errors System operations Scheduler
Code 0 1 2 3
Table 4.3 Trap group codes In addition to the trap groups mentioned above, the CauseError flag in the Status register is used to signal when a trap condition has been activated by the causeerror instruction. It can be used to indicate when trap conditions have occurred due to the user setting them, rather than by the system. 4.6.2 Events that can cause traps Table 4.4 summarizes the events that can cause traps and gives the encoding of bits in the trap Status and Enable words.
Trap cause Status/Enable codes 0 1 2 3 4 5 Trap group 0 1 1 2 2 2 Comments
Breakpoint IntegerError Overflow IllegalOpcode LoadTrap StoreTrap
When a process executes the breakpoint instruction (j0) then it traps to its trap handler. Integer error other than integer overflow - e.g. explicitly checked or explicitly set error. Integer overflow or integer division by zero. Attempt to execute an illegal instruction. This is signalled when opr is executed with an invalid operand. When the trap descriptor is read with the ldtraph instruction or when the trapped process status is read with the ldtrapped instruction. When the trap descriptor is written with the sttraph instruction or when the trapped process status is written with the sttrapped instruction. Scheduler trap from internal channel. Scheduler trap from external channel. Scheduler trap from timer alarm. Scheduler trap from timeslice. Scheduler trap from runp (run process) or star tp (start process). Scheduler trap from signal. Star t executing a process at a new priority level. Caused by no process active at a priority level.
InternalChannel ExternalChannel Timer Timeslice Run Signal
ProcessInterrupt QueueEmpty CauseError
bs O
let o
Pr e
6 7 8 9 10 11 12 13
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
3 3 3 3 3 3 3 3
15 (Status only)
Signals that the causeerror instruction set the trap flag. Any, encoded 0-3
Table 4.4 Trap causes and Status/Enable codes
26/123
ST20-GP6 4.6.3 Trap handlers
For each trap handler there is a trap handler structure and a trapped process structure. Both the trap handler structure and the trapped process structure are in memor y and can be accessed via instructions, see section 4.6.4. The trap handler structure specifies what should happen when a trap condition is present, see Table 4.5. The trapped process structure saves some of the state of the process that was running when the trap was taken, see Table 4.6. In addition, for each priority, there is an Enables register and a Status register. The Enables register contains flags to enable each cause of trap. The Status register contains flags to indicate which trap conditions have been detected. The Enables and Status register bit encodings are given in Table 4.4.
Comments Iptr Wptr Status Enables Iptr of trap handler process. Contains the Status register that the trap handler starts with. Location
Wptr of trap handler process. A null Wptr indicates that a trap handler has not been installed. Base + 2 A word which encodes the trap enable and global interrupt masks, which will be ANDed with the existing masks to allow the trap handler to disable various events while it runs.
Table 4.5 Trap handler structure
Comments Iptr Wptr Status Enables
Points to the instruction after the one that caused the trap condition. Wptr of the process that was running when the trap was taken. The relevant trap bit is set, see Table 4.3 for trap codes. Interrupt enables.
A trap will be taken at an interruptible point if a trap is set and the corresponding trap enable bit is set in the Enables register. If the trap is not enabled then nothing is done with the trap condition. If the trap is enabled then the corresponding bit is set in the Status register to indicate the trap condition has occurred. When a process takes a trap the processor saves the existing Iptr, Wptr, Status and Enables in the trapped process structure. It then loads Iptr, Wptr and Status from the equivalent trap handler structure and ANDs the value in Enables with the value in the structure. This allows the user to disable various events while in the handler, in par ticular a trap handler must disable all the traps of its trap group to avoid the possibility of a handler trapping to itself.
bs O
let o
Pr e
du o
Table 4.6 Trapped process structure
(s) ct
so Ob -
Pr te le
od
uc
s) t(
Base + 3
Base + 1 Base + 0
Location Base + 3 Base + 2 Base + 1 Base + 0
The trap handler then executes. The values in the trapped process structure can be examined using the ldtrapped instruction (see section 4.6.4). When the trap handler has completed its opera-
27/123
ST20-GP6 tion it returns to the trapped process via the tret (trap return) instruction. This reloads the values saved in the trapped process structure and clears the trap flag in Status. Note that when a trap handler is star ted, Areg, Breg and Creg are not saved. The trap handler must save the Areg, Breg, Creg registers using stl (store local). 4.6.4 Trap instructions Trap handlers and trapped processes can be set up and examined via the ldtraph, sttraph, ldtrapped and sttrapped instructions. Table 4.7 describes the instructions that may be used when dealing with traps.
Instruction Meaning load trap handler store trap handler load trapped store trapped trap enable trap disable trap return cause error Use Load the trap handler from memory to the trap handler descriptor. Store an existing trap handler descriptor to memory. Load replacement trapped process status from memory. Store trapped process status to memory. Enable traps. Disable traps. Used to return from a trap handler.
ldtraph sttraph ldtrapped sttrapped trapenb trapdis tret causeerror
Program can simulate the occurrence of an error.
Table 4.7 Instructions which may be used when dealing with traps The first four instructions transfer data to/from the trap handler structures or trapped process structures from/to an area in memor y. In these instructions Areg contains the trap group code (see Table 4.3) and Breg points to the 4 word area of memor y used as the source or destination of the transfer. In addition Creg contains the priority of the handler to be installed/examined in the case of ldtraph or sttraph. ldtrapped and sttrapped apply only to the current priority. If the LoadTrap trap is enabled then ldtraph and ldtrapped do not perform the transfer but set the LoadTrap trap flag. If the StoreTrap trap is enabled then sttraph and sttrapped do not perform the transfer but set the StoreTrap trap flag. The trap enable masks are encoded by an array of bits (see Table 4.4) which are set to indicate which traps are enabled. This array of bits is stored in the lower half-word of the Enables register. There is an Enables register for each priority. Traps are enabled or disabled by loading a mask into Areg with bits set to indicate which traps are to be affected and the priority to affect in Breg. Executing trapenb ORs the mask supplied in Areg with the trap enables mask in the Enables register for the priority in Breg. Executing trapdis negates the mask supplied in Areg and ANDs it with the trap enables mask in the Enables register for the priority in Breg. Both instructions return the previous value of the trap enables mask in Areg.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
28/123
ST20-GP6 4.6.5 Restrictions on trap handlers
There are various restrictions that must be placed on trap handlers to ensure that they work correctly. 1 2 3 Trap handlers must not deschedule or timeslice. Trap handlers alter the Enables masks, therefore they must not allow other processes to execute until they have completed. Trap handlers must have their Enable masks set to mask all traps in their trap group to avoid the possibility of a trap handler trapping to itself. Trap handlers must terminate via the tret (trap return) instruction. The only exception to this is that a scheduler kernel may use restar t to return to a previously shadowed process.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
29/123
ST20-GP6
5
Interrupt controller
The ST20-GP6 suppor ts external interrupts, enabling an on-chip subsystem or external interrupt pin to interrupt the currently running process in order to run an interrupt handling process The ST20-GP6 interrupt subsystem suppor ts eight prioritized interrupts. This allows nested preemptive interrupts for real-time system design. In addition, there is an interrupt level controller (refer to Chapter 6) which multiplexes incoming interrupts onto the eight programmable interrupt levels. This multiplexing is controllable by software. There are 6 sources of interrupts. Four of these are internal (2 for the UARTs, 2 for the programmable IO) and two are external. All interrupts are a higher priority than the low priority process queue. Each interrupt can be programmed to be at a lower priority or a higher priority than the high priority process queue, this is determined by the Priority bit in the HandlerWptr0-7 registers, see Table 5.1 on page 33. Note: Interrupts (Interrupt0-7) which are specified as higher priority must be contiguous from the highest numbered interrupt downwards, i.e. if 4 interrupts are programmed as higher priority and 4 as lower priority the higher priority interrupts must be Interrupt7:4 and the lower priority interrupts Interrupt3:0. Note that interrupt handlers must not prevent the GPS DSP data traffic from being handled. During continuous operation this has 1 ms latency and is not a problem, but during initial acquisition it has a 32 s rate and thus care must be taken with interrupt priorities unless used to stop GPS operation.
Interrupt 7 when Priority bit set to 0
bs O
let o
Increasing pre-emption
Pr e
du o
Interrupt 0 when Priority bit set to 0
(s) ct
so Ob . . .
te le
ro P
uc d
s) t(
High priority process
Interrupt 7 when Priority bit set to 1 . . . Interrupt 0 when Priority bit set to 1 Low priority process
Figure 5.1 Interrupt priority
30/123
ST20-GP6 Interrupts on the ST20-GP6 are implemented via an on-chip interrupt controller peripheral. An interrupt can be signalled to the controller by one of the following: · · · a signal on an external Interrupt pin a signal from an internal peripheral or subsystem software asserting an interrupt in the Pending register
5.1
Interrupt vector table
The interrupt controller contains a table of pointers to interrupt handlers. Each interrupt handler is represented by its workspace pointer (Wptr). The table contains a workspace pointer for each level of interrupt. The Wptr gives access to the code, data and interrupt save space of the interrupt handler. The position of the Wptr in the interrupt table implies the priority of the interrupt. Run-time library support is provided for setting and programming the vector table.
5.2
Interrupt handlers
At any interruptible point in its execution the CPU can receive an interrupt request from the interrupt controller. The CPU immediately acknowledges the request. In response to receiving an interrupt the CPU performs a procedure call to the process in the vector table. The state of the interrupted process is stored in the workspace of the interrupt handler as shown in Figure 5.2. Each interrupt level has its own workspace.
Before interrupt Interrupting high priority process
Wptr Handler Iptr
O
bs
let o
Handler Status
ro P e
du
Wptr
(s) ct
so Ob Handler Iptr
te le
ro P
uc d
s) t(
Interrupting low priority process or CPU idle
Wptr Handler Iptr Handler Status
Handler Status Creg Breg Areg Iptr Wptr Status
Null Status
Figure 5.2 State of interrupted process
31/123
ST20-GP6 The interrupt routine is initialized with space below Wptr. The Iptr and Status word for the routine are stored there permanently. This should be programmed before the Wptr is written into the vector table. The behavior of the interrupt differs depending on the priority of the CPU when the interrupt occurs. When an interrupt occurs when the CPU was running at high priority, and the interrupt is set at a higher priority than the high priority process queue, the CPU saves the current process state (Areg, Breg, Creg, Wptr, Iptr and Status) into the workspace of the interrupt handler. The value HandlerWptr, which is stored in the interrupt controller, points to the top of this workspace. The values of Iptr and Status to be used by the interrupt handler are loaded from this workspace and star ts executing the handler. The value of Wptr is then set to the bottom of this save area. When an interrupt occurs when the CPU was running at high priority, and the interrupt is set at a lower priority than the high priority process queue, no action is taken and the interrupt waits in a queue until all higher priority interrupts have been serviced (see section 5.4). Interrupts always take priority over low priority processes. When an interrupt occurs when the CPU was idle or running at low priority, the Status is saved. This indicates that no valid process is running (Null Status). The interrupted processes (low priority process) state is stored in shadow registers. This state can be accessed via the ldshadow (load shadow registers) and stshadow (store shadow registers) instructions. The interrupt handler is then run at high priority. When the interrupt routine has completed it must adjust Wptr to the value at the star t of the handler code and then execute the iret (interrupt return) instruction. This restores the interrupted state from the interrupt handler structure and signals to the interrupt controller that the interrupt has completed. The processor will then continue from where it was before being interrupted.
5.3
Interrupt latency
The interrupt latency is dependent on the data being accessed and the position of the interrupt handler and the interrupted process. This allows systems to be designed with the best trade-off use of fast internal memory and interrupt latency.
Each interrupt channel has an implied priority fixed by its place in the interrupt vector table. All interrupts will cause scheduled processes of lower priority to be suspended and the interrupt handler star ted. Once an interrupt has been sent from the controller to the CPU the controller keeps a record of the current executing interrupt priority. This is only cleared when the interrupt handler executes a return from interrupt ( ) instruction. Interrupts of a lower priority arriving will be blocked by the interrupt controller until the interrupt priority has descended to such a level that the routine will execute. An interrupt of a higher priority than the currently executing handler will be passed to the CPU and cause the current handler to be suspended until the higher priority interrupt is serviced. In this way interrupts can be nested and a higher priority interrupt will always pre-empt a lower priority one. Deep nesting and placing frequent interrupts at high priority can result in a system where low priority interrupts are never ser viced or the controller and CPU time are consumed in nesting interrupt priorities and not executing the interrupt handlers.
s) (priority ct 5.4 Preemption and interrupt du ro P ete iret ol bs O
so Ob -
te le
ro P
uc d
s) t(
32/123
ST20-GP6
5.5
Restrictions on interrupt handlers
There are various restrictions that must be placed on interrupt handlers to ensure that they interact correctly with the rest of the process model implemented in the CPU. 1 2 Interrupt handlers must not deschedule. Interrupt handlers must not execute communication instructions. However they may communicate with other processes through shared variables using the semaphore signal to synchronize. Interrupt handlers must not perform 2d block move instructions. Interrupt handlers must not cause program traps. However they may be trapped by a scheduler trap.
3 4
5.6
Interrupt configuration registers
The interrupt controller is allocated a 4k block of memor y in the internal peripheral address space. Information on interrupts is stored in registers as detailed in the following section. The registers can be examined and set by the devlw (device load word) and devsw (device store word) instructions. Note, they can not be accessed using memory instructions. HandlerWptr register The HandlerWptr registers (1 per interrupt) contain a pointer to the workspace of the interrupt handler. It also contains the Priority bit which determines whether the interrupt is at a higher or lower priority than the high priority process queue. Note, before the interrupt is enabled, by writing a 1 in the Mask register, the user (or toolset) must ensure that there is a valid Wptr in the register.
HandlerWptr Bit 0 Bit field Priority Interrupt controller base address + #00 to #1C Function
31:2 1
HandlerWptr
O
bs
let o
Pr e
du o
Sets the priority of the interrupt. If this bit is set to 0, the interrupt is a higher priority than the high priority process queue, if this bit is 1, the interrupt is a lower priority than the high priority process queue. 0 high priority 1 low priority Pointer to the workspace of the interrupt handler. Reser ved, write 0.
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Read/Write
Table 5.1 HandlerWptr register format - one register per interrupt
33/123
ST20-GP6 TriggerMode register Each interrupt channel can be programmed to trigger on rising/falling edges or high/low levels on the external Interrupt.
TriggerMode Bit 2:0 Bit field Trigger Interrupt controller base address + #40 to #5C Function Control the triggering condition of the Interrupt, as follows: Trigger2:0 Interrupt triggers on 000 No trigger mode 001 High level - triggered while input high 010 Low level - triggered while input low 011 Rising edge - low to high transition 100 Falling edge - high to low transition 101 Any edge - triggered on rising and falling edges 110 No trigger mode 111 No trigger mode Read/Write
Table 5.2 TriggerMode register format - one register per interrupt
Note, level triggering is different to edge triggering in that if the input is held at the triggering level, a continuous stream of interrupts is generated. Mask register An interrupt mask register is provided in the interrupt controller to selectively enable or disable external interrupts. This mask register also includes a global interrupt disable bit to disable all external interrupts whatever the state of the individual interrupt mask bits. To complement this the interrupt controller also includes an interrupt pending register which contains a pending flag for each interrupt channel. The Mask register performs a masking function on the Pending register to give control over what is allowed to interrupt the CPU while retaining the ability to continually monitor external interrupts. On star t-up, the Mask register is initialized to zeros, thus all interrupts are disabled, both globally and individually. When a 1 is written to the GlobalEnable bit, the individual interrupt bits are still disabled and must also have a 1 individually written to the InterruptEnable bit to enable the respective interrupt.
Mask Bit 7:0 16 Bit field
15:8
O
bs
Interrupt7:0Enable GlobalEnable
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Interrupt controller base address + #C0 Function When set to 1, interrupt is enabled. When 0, interrupt is disabled. When set to 1, the setting of the interrupt is determined by the specific InterruptEnable bit. When 0, all interrupts are disabled. Reser ved, write 0.
Read/Write
Table 5.3 Mask register format The Mask register is mapped onto two additional addresses so that bits can be set or cleared individually.
34/123
ST20-GP6 Set_Mask (address `interrupt base address + #C4') allows bits to be set individually. Writing a `1' in this register sets the corresponding bit in the Mask register, a `0' leaves the bit unchanged. Clear_Mask (address `interrupt base address + #C8') allows bits to be cleared individually. Writing a `1' in this register resets the corresponding bit in the Mask register, a `0' leaves the bit unchanged. Pending register The Pending register contains a bit per interrupt with each bit controlled by the corresponding interrupt. A read can be used to examine the state of the interrupt controller while a write can be used to explicitly trigger an interrupt. A bit is set when the triggering condition for an interrupt is met. All bits are independent so that several bits can be set in the same cycle. Once a bit is set, a fur ther triggering condition will have no effect. The triggering condition is independent of the Mask register. The highest priority interrupt bit is reset once the interrupt controller has made an interrupt request to the CPU. The interrupt controller receives external interrupt requests and makes an interrupt request to the CPU when it has a pending interrupt request of higher priority than the currently executing interrupt handler.
Pending Bit 7:0 Bit field PendingInt7:0 Interrupt controller base address + #80 Function Interrupt pending bit.
Table 5.4 Bit fields in the Pending register The Pending register is mapped onto two additional addresses so that bits can be set or cleared individually. Set_Pending (address `interrupt base address + #84') allows bits to be set individually. Writing a `1' in this register sets the corresponding bit in the Pending register, a `0' leaves the bit unchanged. Clear_Pending (address `interrupt base address + #88') allows bits to be cleared individually. Writing a `1' in this register resets the corresponding bit in the Pending register, a `0' leaves the bit unchanged. Note, if the CPU wants to write or clear some bits of the Pending register, the interrupts should be masked (by writing or clearing the Mask register) before writing or clearing the Pending register. The interrupts can then be unmasked. Exec register The Exec register keeps track of the currently executing and pre-empted interrupts. A bit is set when the CPU star ts running code for that interrupt. The highest priority interrupt bit is reset once the interrupt handler executes a return from interrupt (iret).
Exec Bit 7:0 Bit field Interrupt7:0Exec Interrupt controller base address + #100 Function Set to 1 when the CPU starts running code for interrupt. Read/Write
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Read/Write
Table 5.5 Bit fields in the Exec register
35/123
ST20-GP6 The Exec register is mapped onto two additional addresses so that bits can be set or cleared individually. Set_Exec (address `interrupt base address + #104') allows bits to be set individually. Writing a `1' in this register sets the corresponding bit in the Exec register, a `0' leaves the bit unchanged. Clear_Exec (address `interrupt base address + #108') allows bits to be cleared individually. Writing a `1' in this register resets the corresponding bit in the Exec register, a `0' leaves the bit unchanged.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
36/123
ST20-GP6
6
Interrupt level controller
There are 6 interrupts (of which 2 are external) generated in the ST20-GP6 system and each of these is assigned to one of the interrupt controller's 8 inputs. Thus each of the interrupt controller's inputs responds to zero or more of the 8 system interrupts. An interrupt handler routine is able to ascer tain the source of an interrupt where two or more system interrupts are assigned to one handler by doing a device read from the InputInterrupts register (see Table 6.3) and examining the bits that correspond to the system interrupts assigned to that handler. The interrupt level controller has additional functionality to suppor t the low power controller. The external interrupts are monitored and a signal is generated for the low power controller which tells it when any of them goes to a pre-determined level. This level is programmable for each external interrupt, and in addition each interrupt can be selectively masked.
6.1
Interrupt assignments
Interrupt 0 1 2 3 15:4 16 17 Peripheral PIO A PIO B ASC0 ASC1 UNUSED Interrupt0 pin Interrupt1 pin Signals ORed together to generate interrupt signal Compare function Compare function
The interrupts from the peripherals on the ST20-GP6 are assigned as follows:
ASC0TxBufEmpty, ASC0TxEmpty, ASC0RxBufFull, ASC0ErrorInterrupt ASC1TxBufEmpty, ASC1TxEmpty, ASC1RxBufFull, ASC1ErrorInterrupt UNUSED
Table 6.1 Interrupt assignments These interrupts are inputs to the interrupt level controller. This allows these interrupts to be assigned to any of eight interrupt priority levels and for multiple interrupts to share a priority level.
6.2
Interrupt level controller registers
The interrupt level controller is programmable via configuration registers. These registers can be examined and set by the devlw (device load word) and devsw (device store word) instructions. IntPriority registers The priority assigned to each of the input interrupts is programmable via the IntPriority registers. The interrupt level controller asser ts interrupt output N when one or more of the input interrupts with programmed priority equal to N are high. It is level sensitive and re-timed at the input, thus incurring one cycle of latency.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
37/123
ST20-GP6
IntPriority Bit 2:0 Bit field IntPriority
Interrupt level controller base address + #00 to #1C Function Determines the priority of each interrupt input. IntPriority2:0 Asserts output interrupt 000 0 (lowest priority) 001 1 010 2 011 3 100 4 101 5 110 6 111 7 (highest priority)
Read/Write
Table 6.2 IntPriority register format - 1 register per interrupt InputInterrupts register The InputInterrupts register is a read only register. It contains a vector which shows all of the input interrupts, so bit 0 of the read data corresponds to InterruptIn0, bit 1 corresponds to InterruptIn1.
Inputinterrupts Bit 1:0 Bit field InterruptIn-0 Interrupt level controller base address + #48 Function Input interrupt levels.
Table 6.3 InputInterrupts register format Low power controller support registers The interrupt level controller has 2 additional registers to suppor t the low power controller (see Chapter 11 on page 66). The external interrupts can be used to provide a wake-up from powerdown mode. The IntLPEnable register can be programmed for each interrupt to cause the interrupt to wake-up the ST20-GP6 from power-down mode. The wake-up occurs when the interrupt goes either high or low, depending on the setting of the respective bit in the IntActiveHigh register. IntLPEnable The IntLPEnable register can be set to enable a wake-up from power-down mode when the interrupt occurs.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Read only
38/123
ST20-GP6
IntLPEnable Bit 0 Bit field Int0LPEnable
Interrupt level controller base address + #50 Function
Read/Write
Enable external Interrupt0 for low power controller. 0 Interrupt0 masked from the low power controller 1 Interrupt0 enabled to cause a wake-up from power down mode Enable external Interrupt1 for low power controller. 0 Interrupt1 masked from the low power controller 1 Interrupt1 enabled to cause a wake-up from power down mode
1
Int1LPEnable
Table 6.4 IntLPEnable register format IntActiveHigh The setting of the IntActiveHigh register determines whether the wake-up occurs when the interrupt goes high or low, assuming the interrupt has been enabled to cause a wake-up in the IntLPEnable register.
IntActiveHigh Bit 0 Bit field Int0ActiveHigh Interrupt level controller base address + #4C Function
Interrupt0 set to be active high or low 0 Interrupt0 goes low the ST20-GP6 wakes up from power down mode. 1 Interrupt0 goes high the ST20-GP6 wakes up from power down mode. Interrupt1 set to be active high or low 0 Interrupt1 goes low the ST20-GP6 wakes up from power down mode. 1 Interrupt1 goes high the ST20-GP6 wakes up from power down mode.
1
Int1ActiveHigh
Table 6.5 IntActiveHigh register format
bs O
let o
Pr e
du o
(s) ct
so Ob -
eP let
ro
uc d
s) t(
Read/Write
39/123
ST20-GP6
7
Instruction set
This chapter provides information on the ST20-C2 instruction set. It contains tables listing all the instructions, and where applicable provides details of the number of processor cycles taken by an instruction. The instruction set has been designed for simple and efficient compilation of high-level languages. All instructions have the same format, designed to give a compact representation of the operations occurring most frequently in programs. Each instruction consists of a single byte divided into two 4-bit par ts. The four most significant bits (MSB) of the byte are a function code and the four least significant bits (LSB) are a data value, as shown in Figure 7.1.
Function 7 43
Data 0
Figure 7.1 Instruction format For fur ther information on the instruction set refer to the ment number 72-TRN-273).
7.1
Instruction cycles
Timing information is available for some instructions. However, it should be noted that many instructions have ranges of timings which are data dependent. Where included, timing information is based on the number of clock cycles assuming any memor y accesses are to 2 cycle internal memor y and no other subsystem is using memor y. Actual time will be dependent on the speed of external memory and memory bus availability. Note that the actual time can be increased by: 1 2 the instruction requiring a value on the register stack from the final memor y read in the previous instruction the current instruction will stall until the value becomes available. the first memor y operation in the current instruction can be delayed while a preceding memory operation completes - any two memor y operations can be in progress at any time, any further operation will stall until the first completes. memory operations in current instructions can be delayed by access by instruction fetch or subsystems to the memory interface. there can be a delay between instructions while the instruction fetch unit fetches and partially decodes the next instruction this will be the case whenever an instruction causes the instruction flow to jump.
bs O
3 4
let o
Pr e
du o
(s) ct
Ob -
uSct Manual ST20C2/C4 Instructdn e ro io eP let so
s) t(
(docu-
Note that the instruction timings given refer to `standard' behavior and may be different if, for example, traps are set by the instruction.
40/123
ST20-GP6
7.2
Instruction characteristics
Table 7.3 gives the basic function code of each of the primar y instructions. Where the operand is less than 16, a single byte encodes the complete instruction. If the operand is greater than 15, one prefix instruction (pfix) is required for each additional four bits of the operand. If the operand is negative the first prefix instruction will be nfix. Examples of pfix and nfix coding are given in Table 7.1.
Mnemonic Function code #4 Memory code #43
ldc ldc
is coded as
#3 #35
pfix ldc ldc
is coded as
#3 #5 #987
#2 #4
#23 #45
pfix pfix ldc ldc
is coded as
#9 #8 #7 -31 (ldc #FFFFFFE1)
#2 #2 #4
#29 #28 #47
nfix ldc
#1 #1
Table 7.1 Prefix coding Any instruction which is not in the instruction set tables is an invalid instruction and is flagged illegal, returning an error code to the trap handler, if loaded and enabled. The Notes column of the tables indicates the features of an instruction as described in Table 7.2.
Ident E L
O
bs
let o
Pr e
S O I A D T
du o
Feature
(s) ct
so Ob #4
#6
te le
ro P
uc d
s) t(
#61 #41
Instruction can set an IntegerError trap Instruction can cause a LoadTrap trap
Instruction can cause a StoreTrap trap Instruction can cause an Overflow trap Interruptible instruction Instruction can be aborted and later restarted. Instruction can deschedule Instruction can timeslice
Table 7.2 Instruction features
41/123
ST20-GP6
7.3
Instruction set tables
Function code 0 1 2 3 4 5 6 7 8 9 A B C D E F Memory code 0X 1X 2X 3X 4X 5X 6X 7X 8X 9X AX BX CX DX EX FX Mnemonic j ldlp pfix ldnl ldc ldnlp nfix ldl adc call cj ajw eqc stl stnl opr Processor cycles 5 1 0 to 1 2 1 1 0 to 1 1 1 8 1 or 5 2 1 1 2 0 Name jump load local pointer prefix load non-local load constant load non-local pointer negative prefix load local add constant call conditional jump adjust workspace equals constant store local store non-local operate O Notes D, T
Table 7.3 Primary functions
Memory code 22FA 23FE 23FD 21F8 25F0 Mnemonic testpranal saveh savel sthf stlf stlb sttimer lddevid ldmemstar tval sthb Processor cycles 2 3 3 1 1 1 1 2 1 1
bs O
21FC 21F7 25F4
let o
Pr e
od
ct u
(s)
so Ob Name
te le
ro P
uc d
s) t(
Notes
test processor analyzing save high priority queue registers save low priority queue registers store high priority front pointer store high priority back pointer store low priority front pointer store low priority back pointer store timer load device identity load value of MemStart address
2127FC 27FE
Table 7.4 Processor initialization operation codes
42/123
ST20-GP6
Memory code 24F6 24FB 23F3 23F2 24F1 24F0 F5 FC 25F3 27F2 22FC 21FF F9 25FF F4 25F2 F8 26F8 26F9 26FA
Mnemonic and or xor not shl shr add sub mul fmul div rem gt gtu diff sum prod satadd satsub satmul
Processor cycles 1 1 1 1 1 1 1 1 4 6 5 to 37 5 to 40 1 1 1 1 4 2 2 5
Name and or exclusive or bitwise not shift left shift right add subtract multiply fractional multiply divide remainder greater than greater than unsigned difference sum product
Notes
A, O A, O A, O
saturating add
Table 7.5 Arithmetic/logical operation codes
bs O
let o
od Pr e
ct u
(s)
saturating subtract saturating multiply
Ob -
so
te le
Pr
od
uc
s) t(
A, O A A A, O
A, O
A A A A
43/123
ST20-GP6
Memory code 21F6 23F8 23F7 24FF 23F1 21FA 23F6 23F5 21F9 26F4 26F5
Mnemonic ladd lsub lsum ldiff lmul ldiv lshl lshr norm slmul sulmul
Processor cycles 2 2 2 2 5 to 6 5 to 39 2 2 2 to 5 5 5
Name long add long subtract long sum long diff long multiply long divide long shift left long shift right normalize signed long multiply signed times unsigned long multiply
Notes A, O A, O
A A, O A A A A, O
Table 7.6 Long arithmetic operation codes
Memory code F0 23FA 25F6 21FD 24FC 24F2 25FA 27F9 68FD Mnemonic rev xword cword xdble csngl mint dup pop Processor cycles 1 4 3 2 3 Name reverse extend to word check word
reboot
bs O
let o
ro P e
uc d
1 1 1
1
(s) t
extend to double check single
so Ob -
eP let
ro
uc d
s) t(
Notes
A, O
A A, E A, E
minimum integer duplicate top of stack pop processor stack reboot
Table 7.7 General operation codes
44/123
ST20-GP6
Memory code F2 FA 28F1 23F4 23FF F1 23FB 24FA
Mnemonic bsub wsub wsubdb bcnt wcnt lb sb move
Processor cycles 1 1 1 1 1 1 2
Name byte subscript word subscript form double word subscript byte count word count load byte store byte move message
Notes
I
Table 7.8 Indexing/array operation codes
Memory code 22F2 22FB 24FE 25F1 24F7 22FE Mnemonic ldtimer tin talt taltwt enbt dist 2 to 8 3 Processor cycles 1 Name load timer timer input timer alt start timer alt wait enable timer
disable timer
Table 7.9 Timer handling operation codes
bs O
let o
Pr e
du o
(s) ct
so Ob -
eP let
od r
uc
s) t(
I D, I I
Notes
45/123
ST20-GP6
Memory code F7 FB FF FE 24F3 24F4 24F5 24F9 23F0 21F2 24F8 22FF
Mnemonic in out outword outbyte alt altwt altend enbs diss resetch enbc disc
Processor cycles
Name input message output message output word output byte
Notes D D D D
2 4 to 7 9 1 to 2 1 3 2 to 5 2 to 7
alt start alt wait alt end enable skip disable skip reset channel enable channel disable channel D
Table 7.10 Input and output operation codes
Memory code 22F0 21FB 23FC F6 22F1 Mnemonic ret ldpi gajw gcall lend Processor cycles 3 1 Name return
O
bs
Memory code FD F3 23F9 21F5 21FE
let o
ro P e
uc d
6
3
(s) t
load pointer to instruction general adjust workspace general call loop end T
so Ob -
te le
ro P
uc d
s) t(
Notes
5 to 8
Table 7.11 Control operation codes
Processor cycles 5 4 to 6 3 2 1 Name star t process end process run process stop process load current priority D Notes
Mnemonic star tp endp runp stopp ldpri
Table 7.12 Scheduling operation codes
46/123
ST20-GP6
Memory code 21F3 24FD 22F9 21F0 25F5 25F7 25F8 25F9
Mnemonic csub0 ccnt1 testerr seterr stoperr clrhalterr sethalterr testhalterr
Processor cycles 2 3 2 2 2 to 3 1 1 2
Name check subscript from 0 check count from 1 test error false and clear set error stop on error (no error) clear halt-on-error set halt-on-error test halt-on-error
Notes A, E A, E
D
Table 7.13 Error handling operation codes
Memory code 25FB 25FC 25FD 25FE Mnemonic move2dinit move2dall move2dnonzero move2dzero Processor cycles 3 Name initialize data for 2D block move 2D block copy 2D block copy non-zero bytes 2D block copy zero bytes Notes
Table 7.14 2D block move operation codes
Memory code 27F4 27F5 27F6 27F7 27F8 Mnemonic crcword crcbyte bitcnt Processor cycles 36 12 Name
bitrevword bitrevnbits
bs O
let o
ro P e
uc d
3 2 2
(s) t
calculate crc on word calculate crc on byte count bits set in word reverse bits in word reverse bottom n bits in word
so Ob -
te le
Pr
od
uc
s) t(
I I I
Notes A A A A
Table 7.15 CRC and bit operation codes
47/123
ST20-GP6
Memory code 27F3 29FC 26F3 26FD 26FC
Mnemonic cflerr fptesterr unpacksn roundsn postnormsn
Processor cycles 3 1 10 7 9
Name check floating point error load value true (FPU not present) unpack single length floating point number round single length floating point number post-normalize correction of single length floating point number load single length infinity
Notes E A A A
27F1
ldinf
1
Table 7.16 Floating point support operation codes
Memory code 2CF7 2CFC 2BFA 2BFB 2FFA 2FFB 2FF8 2BF8 Mnemonic cir ciru cb cbu cs csu xsword xbword Processor cycles 3 3 3 2 3 2 3 3 Name check in range check in range unsigned check byte check byte unsigned check sixteen
check sixteen unsigned
sign extend sixteen to word sign extend byte to word
Table 7.17 Range checking and conversion instructions
Memory code 2CF1 Mnemonic ssub
2CFA
O
bs
2CF8 2BF9 2FF9
let o
ls
Pr e
du o
(s) ct
1 1 2 1 1
so Ob -
te le
Pr
od
uc
s) t(
A, E A, E A, E A, E A, E A, E A A
Notes
Processor cycles
Name sixteen subscript load sixteen store sixteen load byte and sign extend load sixteen and sign extend
Notes
ss
lbx lsx
Table 7.18 Indexing/array instructions
48/123
ST20-GP6
Memory code 2FF0 2FF2 2FF4 62F4 2FF1 2FF3 2FF5
Mnemonic devlb devls devlw devmove devsb devss devsw
Processor cycles 3 3 3
Name device load byte device load sixteen device load word device move
Notes A A A I A A A
3 3 3
device store byte device store sixteen device store word
Table 7.19 Device access instructions
Memory code 60F5 60F4 Mnemonic wait signal Processor cycles 5 to 11 7 to 12 Name wait signal
Table 7.20 Semaphore instructions
Memory code 60F0 60F1 60F2 60F3 60FC 60FD 62FE 62FF Mnemonic swapqueue swaptimer inser tqueue timeslice ldshadow stshadow restar t Processor cycles 4 5 Name
swap scheduler queue swap timer queue
3 to 4
bs O
61FF
2BF0
let o
causeerror iret
Pr e
od
uc
3 to 4
(s) t
inser t at front of scheduler queue timeslice load shadow registers store shadow registers restar t A A
so Ob -
eP let
od r
uc
s) t(
D
Notes
Notes
6 to 31 6 to 17 20 7 to 8 3 to 11 2 2 2 5 5
cause error interrupt return set timeslicing status interrupt disable interrupt enable global interrupt disable global interrupt enable
settimeslice intdis intenb gintdis gintenb
2CF4 2CF5
2CFD 2CFE
Table 7.21 Scheduling support instructions
49/123
ST20-GP6
Memory code 26FE 2CF6 2CFB 26FF 60F7 60F6 60FB
Mnemonic ldtraph ldtrapped sttrapped sttraph trapenb trapdis tret
Processor cycles 12 12 12 12 4 4 8 to 10
Name load trap handler load trapped process status store trapped process status store trap handler trap enable trap disable trap return
Notes L L S S
Table 7.22 Trap handler instructions
Memory code 68FC 63F0 Mnemonic ldprodid nop Processor cycles 1 1 Name load product identity no operation
Table 7.23 Processor initialization and no operation instructions
Memory code 64FF 64FE 64FD 64FC Mnemonic clockenb clockdis ldclock stclock Processor cycles 2 2 2 Name
clock enable
bs O
let o
Pr e
od
uc
2
(s) t
clock disable load clock
so Ob -
te le
ro P
uc d
s) t(
Notes
Notes
store clock
Table 7.24 Clock instructions
50/123
ST20-GP6
8
Memory map
The ST20-GP6 processor memor y has a 32-bit signed address range. Words are addressed by 30-bit word addresses and a 2-bit byte-selector identifies the bytes in the word. Memor y is divided into 4 banks which can each have different memor y characteristics and can be used for different purposes. In addition, on-chip peripherals can be accessed via the device access instructions (see Table 7.19). The bottom 16 Kbytes of the internal SRAM are powered from the batter y backup supply. Various memory locations at the bottom and top of memor y are reser ved for special system purposes. There is also a default allocation of memory banks to different uses. Note that the ST20-GP6 uses 30 bits of addressing internally, but addresses A20-A29 are not brought out to external pins. Address bits A30 and A31 are decoded internally for use as bank selects.
8.1
System memory use
The ST20-GP6 has a signed address space where the address ranges from MinInt (#80 0 000) at the bottom to MaxInt (#7FFFFFFF) at the top. The ST20-GP6 has an area of 64 Kbytes of SRAM at the bottom of the address space provided by on chip memor y. The bottom of this area is used to store various items of system state. These addresses should not be accessed directly but via the appropriate instructions. Near the bottom of the address space there is a special address MemStart. Memor y above this address is for use by user programs while addresses below it are for private use by the processor and used for subsystem channels and trap handlers. The address of MemStart can be obtained via the ldmemstar tval instruction. 8.1.1 Subsystem channels memory
Each DMA channel between the processor and a subsystem is allocated a word of storage below MemStart. This is used by the processor to store information about the state of the channel. This information should not normally be examined directly, although debugging kernels may need to do so. 8.1.2 Trap handlers memory
The area of memor y reserved for trap handlers is broken down hierarchically. Full details on trap handlers is given in see Section 4.6 on page 23.
bs O
· · · ·
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Each high/low process priority has a set of trap handlers. Each set of trap handlers has a handler for each of the four trap groups (refer to Section 4.6.1). Each trap group handler has a trap handler structure and a trapped process structure. Each of the structures contains four words, as detailed in Section 4.6.3.
51/123
ST20-GP6 The contents of these addresses can be accessed via ldtraph, sttraph, ldtrapped and sttrapped instructions.
8.2
Boot ROM
There is 128K bytes of mask ROM on-chip. This is mapped to the upper 128K of bank 3 (addresses #7FFE0000 to #7FFFFFFF). If mask ROM is not programmed, internal ROM is disabled and external ROM is used. When the processor boots from ROM, it jumps to a boot program held in ROM with an entr y point 2 bytes from the top of memor y at #7FFFFFFE. These 2 bytes are used to encode a negative jump of up to 256 bytes down in the ROM program. For large ROM programs it may then be necessary to encode a longer negative jump to reach the start of the routine.
8.3
Internal peripheral space
On-chip peripherals are mapped to addresses in the address range #0 0 0000 to #3FFFFFFF). They can only be accessed by the device access instructions (see Table 7.19). When used with addresses in this range, the device instructions access the on-chip peripherals rather than external memory. For all other addresses the device instructions access memor y. Standard load/store instructions to these addresses will access external memory. Each on-chip peripheral occupies a 4K block, see the following memory map.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
52/123
ST20-GP6
MEMORY BANK
ADDRESS
USE
MaxInt #7FFFFFFF BootEntry #7FFFFFFE #40 0 000 #2000E000 #2000C000 #2000A000 #20008000 #20006000 #20004000 #20002000 #20001000 #20 0 000 #00004000 #00003000 #00002000 #0 0 0000 #C0 0 000 Start of external memory #810 0 00 MemStart #80000140 #80000130 #80000120 #80000110 #80000100 #80 0 0F0 #80 0 0E0 #80 0 0D0 #80 0 0C0 #80 0 0B0 #80 0 0A0
Bank 3 User code and boot ROM RESERVED DSP controller peripheral (registers accessed via CPU device accesses) PIO B controller peripheral (registers accessed via CPU device accesses) PIO A controller peripheral (registers accessed via CPU device accesses) ASC1 controller peripheral (registers accessed via CPU device accesses) ASC0 controller peripheral (registers accessed via CPU device accesses) Real-time clock/watchdog timer peripheral (registers accessed via CPU device accesses) Interrupt level controller peripheral (registers accessed via CPU device accesses) Interrupt and low power controller peripheral (registers accessed via CPU device accesses) RESERVED
Diagnostic controller(registers accessed via CPU device accesses) External memory interface(registers accessed via CPU device accesses) RESERVED
O
bs
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Bank 2
Bank 1
User code/Data/Stack
Low priority Scheduler trapped process Low priority Scheduler trap handler Low priority SystemOperations trapped process Low priority SystemOperations trap handler Low priority Error trapped process Low priority Error trap handler Low priority Breakpoint trapped process Low priority Breakpoint trap handler High priority Scheduler trapped process High priority Scheduler trap handler
Bank 0
Figure 8.1 ST20-GP6 internal peripheral map
53/123
ST20-GP6
MEMORY BANK
ADDRESS
USE
TrapBase
MinInt
#80 0 090 #80 0 080 #80 0 070 #80 0 060 #80 0 050 #80 0 040 #80 0 03C #80 0 01C #80 0 018 #80 0 014 #80 0 010 #80 0 00C #80 0 008 #80 0 004 #80 0 000
High priority SystemOperations trapped process High priority SystemOperations trap handler High priority Error trapped process High priority Error trap handler High priority Breakpoint trapped process High priority Breakpoint trap handler RESERVED DSP module DMA channel Bank 0
RESERVED
Figure 8.1 ST20-GP6 internal peripheral map
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
54/123
ST20-GP6
9
Memory subsystem
The memory system consists of SRAM and a programmable memor y interface. The specific details on the operation of the memory interface are described separately in Chapter 10.
9.1
SRAM
There is an internal memor y module of 64 Kbytes of SRAM. The internal SRAM is mapped into the base of the memory space from MinInt (#80 0 000) extending upwards. This memory can be used to store on-chip data, stack or code for time critical routines. Optional external RAM, if fitted, is addressed from #810 0 00.
9.2
ROM
There is 128 Kbytes of on-chip ROM for application code.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
55/123
ST20-GP6
10 Programmable memory interface
The ST20-GP6 programmable memor y interface has a 16 bit data bus and provides glueless suppor t for up to four banks of SRAM memor y. Sufficient configuration options are provided to enable the interface to be used with a wide variety of SRAM speeds, permitting systems to be built with optimum price/performance trade-offs. The programmable memor y interface is also referred to as the external memor y interface (EMI). The EMI provides configuration information for four independent banks of external memor y devices. The addresses of these bank boundaries are hard wired to give each bank one quar ter of the address space of the machine. Bank 0 occupies the lowest quar ter of the [signed] address space, bank 3 is the highest, see Figure 10.1. The configuration is held in memor y mapped registers within the EMI. Each bank has 64 bits to hold configuration data. This data is accessed as four 16-bit accesses. The EMI configuration software ensures that the configuration of a bank is consistent and works with all devices in the bank before any access to that bank. Default configurations on star t-up (see "Default configuration" on page 65) allow the slowest memory to be accessed. Four configuration control registers (one for each bank) are provided which allow the configuration data registers to be locked. This prevents an accidental overwrite from destroying the emi configuration. A configuration status register is also provided to show which banks have been locked and which banks have been configured. The memory map for the configuration registers within the EMI contains 16 x 16-bit data registers each located at word boundar y, plus four lock control registers and a global register for status information.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
56/123
ST20-GP6
7FFFFFFF 7FFE0000 7F0 0 00
128k internal ROM RESERVED Bank 3 Bank 2 On-chip peripheral registers are mapped into this bank.
40 0 000
20 0 000 00010000 00003000 00003FFF 00002000 0 0 0000
On-chip peripherals RESERVED Diagnostic controller EMI configuration
external memory
external memory
C0 0 000
810 0 00
bs O
let o
Pr e
RESERVED 64k internal SRAM
Bank 0
du o
(s) ct
so Ob -
Bank 1
te le
ro P
uc d
s) t(
8000FFFF
Internal SRAM
80003FFF MemStart Batter y backed RAM Traps/ exceptions Subsystem channels
80 0 000
80 0 000
Addresses shown are physical addresses.
Figure 10.1 Memory allocation
57/123
ST20-GP6
10.1 EMI signal descriptions
The following section describes the functions of the EMI pins. Note that a signal name prefixed by not indicates active low. MemAddr1-19 External address bus. The ST20-GP6 uses 30 bits of addressing internally but only the bottom 18 bits are brought out to external pins (MemAddr2-19); MemAddr1 is generated by the EMI. MemAddr1-19 is valid and constant for the whole duration of an external access. The memor y locations in each bank can be accessed at multiple addresses, as bits 20-29 are ignored when making external accesses. MemData0-15 External data bus. The data bus may be configured to be either 8 or 16 bits wide on a per bank basis. MemData0 is always the least significant bit. MemData7 is the most significant bit in 8-bit mode and MemData15 is the most significant bit in 16-bit mode. When performing a write access to a bank configured to be 8-bits wide, MemData8-15 are held in a high-impedance state for the duration of the access; MemData0-7 behave according to the configuration parameters as specified in Section 10.4. When making a write to a bank configured to be 16-bits wide, MemData0-15 behave according to the configuration parameters. notMemCE0-3 Chip enable strobes, one per bank. The notMemCE0-3 strobe corresponding to the bank being accessed will be active on both reads and writes to that bank. notMemOE0 Output enable strobe. This strobe is shared between all four banks. The notMemOE0 strobe will be active only on reads to the bank. notMemBE0-1 Byte enable strobes to select bytes within a 16-bit half-word. These strobes are shared between all four banks. notMemBE0 always corresponds to data on MemData0-7 whether the bus is currently 8 or 16 bits wide. When the EMI is accessing a bank configured to be 16 bits wide, notMemBE1 corresponds to MemData8-15. When the EMI is accessing a bank configured to be 8 bits wide, notMemBE1 becomes address bit 0 and follows the timing of MemAddr1-19 for that bank. MemWait Halt external access. The EMI samples MemWait at or just after the midpoint of an access. If MemWait is sampled high, the access is stalled. MemWait will then continue to be sampled and the access proceeds when MemWait is sampled low. The action of MemWait may be disabled by software, see Section 10.3. No mechanism is provided to abor t an access; if MemWait is held high too long the EMI will become a contentious resource and may stall the ST20-GP6.
bs O
let o
Pr e
|
