STE10/100A
PCI 10/100 Ethernet controller with integrated PHY (3.3V)
Features
IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant Support for IEEE802.3x flow control IEEE802.3u auto-negotiation support for 10BASE-T and 100BASE-TX PCI bus interface rev. 2.2 compliant ACPI and PCI power management standard compliant Support for PC99 wake on LAN Provides 32-bit PCI bus master data transfer at PCI clocks of 20-33 MHz Provides writable EEPROM/Boot rom interface Provides independent transmission and receiving FIFOs, each 2k bytes long Supports big endian or little endian byte ordering ACPI and PCI compliant power management functions offer significant power-savings performance Provides general purpose timers 128-pin QFP package
PQFP128 (14mm x 20mm x 2.7mm)
Description
The STE10/100A is a high performing PCI fast ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide glueless 32-bit bus master interface for PCI bus, boot ROM interface, CSMA/CD protocol for fast ethernet, as well as the physical media interface for 100BASE-TX of IEEE802.3u and 10BASE-T of IEEE802.3. The auto-negotiation function is also supported for speed and duplex detection.
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The STE10/100A provides both half-duplex and full-duplex operation, as well as support for fullduplex flow control. It provides long FIFO buffers for transmission and receiving, and early interrupt mechanism to enhance performance. The STE10/100A also supports ACPI and PCI compliant power management function
February 2007
Rev 8
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www.st.com
82
Contents
STE10/100A
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1. 1 1. 2 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Detailed features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. 1 3.2 Initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Network packet buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 3.2.2 Descriptor structure types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Descriptor management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Transmit scheme and transmit early interrupt . . . . . . . . . . . . . . . . . . . . . 16
3.3.1 3.3.2 3.3.3 Transmit scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transmit pre-fetch data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transmit early interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 3.5
Receive scheme and receive early interrupt scheme . . . . . . . . . . . . . . . . 18 Network operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.1 3.5.2 3.5.3 MAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transceiver operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Flow control in full duplex application . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3. 6 3.7
LED display operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7.1 3.7.2
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Reset whole chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reset transceiver only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Wake on LAN function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ACPI power management function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Registers and descriptors description . . . . . . . . . . . . . . . . . . . . . . . . . 29
STE10/100A configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.1 STE10/100A configuration registers description . . . . . . . . . . . . . . . . . . 31
PCI control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Transceiver(XCVR) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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STE10/100A
Contents
4.4
Descriptors and buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4.1 4.4.2 Receive descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5 6
General EEPROM format description . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Electrical specifications and timings . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6. 1 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7 8 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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Overview
STE10/100A
1
1.1
Overview
Block diagrams
Figure 1. STE10/100A block diagram
MI controller Manchester encoder 10 TX filter
Flow control
DMA
4B/5B
Scrambler
Transmitter 125MHz
PCI controller
Auto-negociation Tx FiFo
25MHz
TX freq. synth. 20MHz
5B/4B Rx FiFo MAC sublayer MI controller 100 clock recovery
Descrambler
Base line restore
Adaptive equalization
EMI
10 clock recovery Manchester decoder Link polarity
Figure 2.
STE10/100A system diagram
Serial EEPROM
Boot ROM
PCI interface
STE10/100A
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PC00347
Xfmr
Medium
PC00348
4/82
STE10/100A
Overview
1.2
Detailed features
FIFO
Provides independent transmission and receiving FIFOs, each 2k bytes long Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us Retransmits collided packet without reload from host memory within 64 bytes. Automatically retransmits FIFO under-run packet with maximum drain threshold until 3rd time retry failure threshold of next packet.
PCI interface
Provides 32-bit PCI bus master data transfer Suppor ts PCI clock with frequency from 0Hz to 33MHz Suppor ts network operation with PCI system clock from 20MHz to 33MHz Provides performance meter and PCI bus master latency timer for tuning the threshold to enhance the performance Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization As bus master, supports memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate command Suppor ts big or little endian byte ordering
EEPROM/Boot ROM interface
Provides writable flash ROM and EPROM as boot ROM, up to 128Kbit Provides PCI to access boot ROM by byte, word, or double word Re-writes flash boot ROM through I/O port by programming register Provides serial interface for read/write 93C46 EEPROM Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, maximum-latency, and minimum-grand from the 64 byte contents of 93C46 after PCI reset de-asserted
MAC/physical
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Integrates the complete set of physical layer 100BASE-TX and 10BASE-T functions Provides full-duplex operation in both 100Mbps and 10Mbps modes Provides auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbps Provides MLT-3 transceiver with DC restoration for base-line wander compensation Provides transmit wave-shaper, receive filters, and adaptive equalizer Provides MAC and transceiver (TXCVR) loop-back modes for diagnostic Built-in stream cipher scrambler/ de-scrambler and 4B/5B encoder/decoder Suppor ts external transmit and receive transformer with 1:1 turn ratio
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Overview
STE10/100A
LED display
Provides 2 LED display modes: 3 LED displays for 100Mbps (on) or 10Mbps (off) link (remains on when link ok) or activity (Blinks at 10Hz when receiving or transmitting collision-free) FD (Remains on when in full duplex mode) or when collision detected (Blinks at 20Hz) 4 LED displays for: 100 link (On when 100M link ok) 10 link (On when 10M link ok) Activity (Blinks at 10Hz when receiving or transmitting) FD (Remains on when in full duplex mode) or when collision detected (Blinks at 20Hz)
If no LED is used, then: Pull the pins 90, 91, 92 of U4 to high with 4.7K resistor (see STE10/100A evaluation board schematics for details)
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STE10/100A
Pin description
2
Pin description
Figure 3. Pin connection
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Pin description Table 1.
Pin no.
STE10/100A Pin description
Name Type Description
PCI bus interface 113 INTA# O/D PCI interrupt request. STE10/100A asserts this signal when one of the interrupt event is set. PCI reset signal to initialize the STE10/100A. The RST signal should be asserted for at least 100s to ensure that the STE10/100A completes initialization. During the reset period, all the output pins of STE10/100A will be placed in a highimpedance state and all the O/D pins are floated. PCI clock input to STE10/100A for PCI bus functions. The Bus signals are synchronized relative to the rising edge of PCI-CLK PCI-CLK must operate at a frequency in the range between 20MHz and 33MHz to ensure proper network operation. PCI bus granted. This signal indicates that the STE10/100A has been granted ownership of the PCI bus as a result of a bus request. PCI bus request. STE10/100A asserts this line when it needs access to the PCI Bus. The power management event signal is an open drain, active low signal. The STE10/100A will assert PME# to indicate that a power management event has occurred. When WOL (bit 18 of CSR18) is set, the STE10/100A is placed in wake on LAN mode. While in this mode, the STE10/100A will activate the PME# signal upon receipt of a magic packet frame from the network. In the wake on LAN mode, when LWS (bit 17 of CSR18) is set, the LAN-wake signal follows HP's protocol; otherwise, it is IBM protocol.
114
RST#
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116
PCI-CLK
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117
GNT#
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118
REQ#
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119
PM E#
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120,121 123,124 126,127 1,2 6,7 9,10 12,13 15,16 29,30 32~35 37 41 43,44 46,47 49,50 52,53
Pr e
AD-31,30 AD-29,28 AD-27,26 AD-25,24 AD-23,22 AD-21,20 AD-19,18 AD-17,16 AD-15,14 AD-13~10 AD-9 AD-8 AD-7, 6 AD-5,4 AD-3,2 AD-1,0
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Multiplexed PCI bus address/data pins
8/82
STE10/100A Table 1.
Pin no. 3 17 28 42 4 18 20 21 22 23 24 25 26
Pin description Pin description (continued)
Name C-BEB3 C-BEB2 C-BEB1 C-BEB0 IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR Type Description
I/O
Bus command and byte enable
I I/O I/O I/O I/O I/O I/O O/D I/O
Initialization device select. This signal is asserted when the host issues configuration cycles to the STE10/100A. Asser ted by PCI bus master during bus tenure Master device is ready to begin data transaction Target device is ready to begin data transaction Device select. Indicates that a PCI target device address has been decoded PCI target device request to the PCI master to stop the current transaction
Data parity error detected, driven by the device receiving data Address parity error
Parity. Even parity computed for AD[31:0] and C/BE[3:0]; master drives PAR for address and write data phase, target drives PAR for read data phase.
Boot ROM/EEPROM interface BrA0~3 BrA4~9 BrA10~15 BrA16/ LED M2 Fd/Col
56~59 61~66 80~86 87
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67~71 72 73 74
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76 77 78 79
BrD0~4 BrD5/EDO BrD6/EDI BrD7/ECK
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ROM data bus Provides up to 128Kbit EPROM or flash-ROM application space. This pin can be programmed as mode 2 LED display for full duplex or collision status. It will be driven (LED on) continually when a full duplex configuration is detected, or it will be driven at a 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. BootROM data bus (0~7) EDO: Data output of serial EEPROM, data input to STE10/100A EDI: Data input to serial EEPROM, data output from STE10/100A ECK: Clock input to serial EEPROM, sourced by STE10/100A Chip select of serial EEPROM BootROM chip select BootROM read output enable for flash ROM application BootROM write enable for flash ROM application.
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Pin description Table 1.
Pin no.
STE10/100A Pin description (continued)
Name Type Description
Physical interface 25MHz reference clock input for physical portion. When an external 25MHz crystal is used, this pin will be connected to one of its terminals, and X2 will be connected to the other terminal. If an external 25 MHz oscillator is used, then this pin will be connected to the oscillator's output pin. 25MHz reference clock output for physical portion. When an external 25MHz crystal is used, this pin will be connected to one of the crystal terminals (see X1, above). If an external clock source is used, then this pin should be left open. The differential transmit outputs of 100BASE-TX or 10BASET, these pins connect directly to magnetic. The differential receive inputs of 100BASE-TX or 10BASE-T, these pins connect directly from magnetic. Reference resistor connecting pin for reference current, directly connects a 5KOhm 1% resistor to Vss.
98
X1
I
97
X2
O
107,109 105,104 101
TX+, TXRX+, RXIref
O I O
LED display & miscellaneous
90
LED M1LK/Act or LED M2Act
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92
LED M1Speed or LED M2100 link
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This pin can be programmed as mode 1 or mode 2: For mode 1: LED display for link and activity status. This pin will be driven on continually when a good Link test is detected. This pin will be driven at a 10Hz blinking frequency when either effective receiving or transmitting is detected. For mode 2: LED display for activity status. This pin will be driven at a 10Hz blinking frequency when either effective receiving or transmitting is detected.
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This pin can be programmed as mode 1 or mode 2: For mode 1: LED display for 100M b/s or 10M b/s speed. This pin will be driven on continually when the 100M b/s network operating speed is detected. For mode 2: LED display for 100Ms/s link status. This pin will be driven on continually when 100Mb/s network operating speed is detected.
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STE10/100A Table 1.
Pin no.
Pin description Pin description (continued)
Name Type Description This pin can be programmed as mode 1 or mode 2: For mode 1: LED display for full duplex or collision status. This pin will be driven on continually when a full duplex configuration is detected. This pin will be driven at a 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. For mode 2: LED display for 10Ms/s link status. This pin will be driven on continually when 10Mb/s network operating speed is detected. When this pin is asserted, it indicates an auxiliary power source is supported from the system. When this pin is asserted, it indicates a PCI power source is supported.
91
LED M1Fd/Col or LED M210 link
O
89 88
Vaux-detect Vcc-detect
I I
Pin no. Digital power pins 5,11,19,31,36,39,45,51,55,75,93,112,115,125 8,14,27,38,40,48,60,85,111,122,128 Analog power pins 94,96,102,106,110 95,99,100,103,108 Vss Vdd
Name
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11/82
Functional description
STE10/100A
3
3.1
Functional description
Initialization flow
Figure 4. STE10/100A initialization flow
Search NIC
Get base IO address Get IRQ value
Reset MAC (CSR0) Reset PHY (XR0)
Need set No
Yes
(Force media) Program the media type to XR0
Read EEPROM from CSR9 Set physical address (CSR25, 26)
Need set No
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Prepare transmit descriptor and buffer Prepare receive descriptor and buffer
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Set multimedia address table (CSR27, 28)
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Install NIC ISR function
Open NIC interrupt Enable Tx & Rx functions
END PC00349
12/82
STE10/100A
Functional description
3.2
3.2.1
Network packet buffer management
Descriptor structure types
During normal network transmit operations, the STE10/100A transfers the data packets from transmit buffers in the host's memory to the STE10/100A's transmit FIFO. For receive operations, the STE10/100A transfers the data packet from its receive FIFO to receive buffers in the host's memory. The STE10/100A makes use of descriptors, data structures which are built in host memory and contain pointers to the transmit and receive buffers and maintain packet and frame parameters, status, and other information vital to controlling network operation. There are two types of structures employed to group descriptors, the Ring and the Chain, both supported by the STE10/100A and shown below. The selection of structure type is controlled by RCH (RDES1 bit 24) and TCH (TDES1 bit 24). The transmit and receive buffers reside in the host's memory. Any buffer can contain either a complete or partial packet. A buffer may not contain more than one packet.
Ring structure
There are two buffers per descriptor in the ring structure. Support receive early interrupt. Figure 5. Frame buffer ring structure
Descriptor CSR3 or CSR4 Descriptor pointer own
Length 2 Length 1
Buffer1 pointer
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Buffer2 pointer . . . . . . .
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Data buffer Length 1
Data
Length 2
End of ring
PC00350
13/82
Functional description
STE10/100A
Chain structure
There is only one buffer per descriptor in chain structure. Figure 6. Frame buffer chain structure
Descriptor own --Length 1
CSR3 or CSR4 Descriptor pointer
Data buffer Data Length 1
Buffer1 pointer Next pointer
own --Length 2
Buffer1 pointer Next pointer
Data
Length 2
own --Length 3
Buffer1 pointer Next pointer . . .
Data
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Length 3
PC00351
14/82
STE10/100A
Functional description
3.2.2
Descriptor management
OWN bit = 1, ready for network side access OWN bit = 0, ready for host side access
Transmit descriptors
Figure 7. Transmit descriptor management
Descriptor ring
0
Length 2 Length1
Ext packet to be transmitted Own bit=1, packet 1 and packet 2 are ready to transmit
Buffer Buffer 1 pointer Buffer 2 pointer 1 Packet1 Data buffer
1 Packet1
Data
Data 1 Packet2
Empty descriptor pointer
0
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End of ring
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PC00352
15/82
Functional description
STE10/100A
Receive descriptors
Figure 8. Receive descriptor management
0 Own bit = 1 Next descriptor ready for incoming packet Paacket22 P cket 1 Data b u ffer
1
1
Filled descriptor pointer
0
Packett 1 Packe 1
· · ·
End of ring
0
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PC00353
16/82
STE10/100A
Functional description
3.3
3.3.1
Transmit scheme and transmit early interrupt
Transmit scheme
Figure 9. Transmit scheme
Initialize descriptor Place data in host memory Set own bit to 1 Write Tx demand poll command
Ex it
Own = 0
STE10/100 checks descriptor Own = 1 Transfer data to Tx FIFO
Deferring OR data less than Tx threshold?
Transmit data across line
Back-off
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Collision occured?
Write descriptor Generate interrupt
PC00354
17/82
Functional description
STE10/100A
3.3.2
Transmit pre-fetch data flow
Transmit FIFO size=2K-byte Two packets in the FIFO at the same time Meet the transmit min. back-to-back
Figure 10. Transmit pre-fetch data flow
Place the 1st packet data into host memory Issue transmit demand FIFO-to-host memory operation (1st packet) Transmit enable Place the 2nd packet data into host memory Check point FIFO-to-host memory operation (2nd packet) Place the 3rd packet data into host memory Check point FIFO-to-host memory operation (3rd packet) 1st packet is transmitted, check the 3rd packet 1st packet Check the next packet 2nd packet Transmit threshold IFG
Time : handled by driver
3.3.3
Transmit early interrupt scheme
Figure 11. Transmit normal interrupt and early interrupt comparison
Host to TX-FIFO memory operation Transmit data from FIFO to media Normal interrupt after transmit completed
Driver return buffer to upper layer
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Early interrupt after host to TXFIFO operation completed
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PC00355
Driver return buffer to upper layer
Time
The saved time when transmit early interrupt is implemented : handled by driver : handled by STE10/100A
PC00356
18/82
STE10/100A
Functional description
3.4
Receive scheme and receive early interrupt scheme
The following figure shows the difference of timing without early interrupt and with early interrupt. Figure 12. Receive data flow (without early interrupt and with early interrupt)
Incoming packet Receive FIFO operation FIFO-to-host memory operation Interrupt Driver read header Higher layer process Driver read the rest data Finish time Receive early interrupt Driver read header (early) Higher layer process (early) Driver read the rest data Finish time
Time : without early interrupt
Figure 13. Detailed receive early interrupt flow
FIFO-to-host memory operation
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PC00357
: with early interrupt
The size of 1st descriptor is programmed as the header size in advance
1s t descriptor full
descriptor
Issue 2 interrupt at end of packet
Receive early interrupt
Driver read header (early)
Higher layer process (early) Driver read the rest data Time Finish
PC00358
19/82
Functional description
STE10/100A
3.5
3.5.1
Network operation
MAC operation
The MAC (Media access control) portion of STE10/100A incorporates the essential protocol requirements for operating as an IEEE802.3 and ethernet compliant node.
Format
Table 2. Format
Field Preamble Start frame diameter Destination address Source address Description A 7-byte field of (10101010b) A 1-byte field of (10101011b) A 6-byte field A 6-byte field A 2-byte field indicated the frame is in IEEE802.3 format or ethernet format. IEEE802.3 format: 0000H ~ 05DCH for length field Ethernet format: 05DD ~ FFFFH for type field 46(1) ~ 1500 bytes of data information
Length/type
Data CRC
A 32-bit cyclic redundancy code for error detection
1. If padding is disabled (TDES1 bit 23), the data field may be shorter than 46 bytes
Transmit data encapsulation
The differences between transmit data encapsulation and a MAC frame while operating in 100BASE-TX mode are listed as follows: The first byte of the preamble is replaced by the JK code according to IEE802.3u, clause 24. After the CRC field of the MAC frame, the STE10/100A will insert the TR code according to IEE802.3u, clause 24.
Receive data decapsulation
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When operating in 100BASE-TX mode the STE10/100A detects a JK code in a preamble as well as a TR code at the packet end. If a JK code is not detected, the STE10/100A will abort the reception of the frame and wait for a new JK code detection. If a TR code is not detected, the STE10/100A will report a CRC error.
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Deferring
The inter-frame gap (IFG) time is divided into two parts: FG1 time (64-bit time): If a carrier is detected on the medium during this time, the STE10/100A will reset the IFG1 time counter and restart to monitor the channel for an idle again. IFG2 time (32-bit time): After counting the IFG2 time the STE10/100A will access the channel even though a carrier has been sensed on the network.
20/82
STE10/100A
Functional description
Collision handling
The scheduling of re-transmissions are determined by a controlled randomization process called "truncated binary exponential back-off". At the end of enforcing a collision (jamming), the STE10/100A delays before attempting to re-transmit the packet. The delay is an integer multiple of slot time. The number of slot times to delay before the nth re-transmission attempt is chosen as a uniformly distributed integer r in the range: 0 · r < 2k where k = min(n, 10)
3.5.2
Transceiver operation
The transceiver portion of the ste10/100a integrates the ieee802.3u compliant functions of PCS (physical coding sub-layer), PMA (physical medium attachment) sub-layer, and PMD (physical medium dependent) sub-layer for 100base-tx, and the ieee802.3 compliant functions of manchester encoding/decoding and transceiver for 10base-t. All the functions and operating schemes are described in the following sections.
100BASE-TX transmit operation
For 100BASE-TX transmissions, the STE10/100A transceiver provides the transmission functions of PCS, PMA, and PMD for encoding of MII data nibbles into five-bit code-groups (4B/5B), scrambling, serialization of scrambled code-groups, converting the serial NRZ code into NRZI code, converting the NRZI code into MLT3 code, and then driving the MLT3 code into the category 5 unshielded twisted pair cable through an isolation transformer with the turns ratio of 1: 1.
Recommended transformers
HB626-1 from transpower technologies, 9410 prototype drive, suite #1, Reno, NV 89511. Tel: (775) 852-0140 and H1102 from pulse engineering Inc., 12220 World Trade Drive, San Diego, CA92128. Tel: (619) 674-8100.
Data code-groups encoder
In normal MII mode applications, the transceiver receives nibble type 4B data via the TxD0~3 inputs of the MII. These inputs are sampled by the transceiver on the rising edge of Tx-clk and passed to the 4B/5B encoder to generate the 5B code-group used by 100BASETX.
Idle code-groups
bs O
let o
In order to establish and maintain the clock synchronization, the transceiver must keep transmitting signals to medium. The transceiver will generate Idle code-groups for transmission when there is no actual data to be sent by MAC.
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Start-of-stream delimiter-SSD (/J/K/)
In a transmission stream, the first 16 nibbles comprise the MAC preamble. In order to let a network partner delineate the boundary of a data transmission sequence and to authenticate carrier events, the transceiver will replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups.
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Functional description
STE10/100A
End-of-stream delimiter-ESD (/T/R/)
In order to indicate the termination of normal data transmissions, the transceiver will insert 2 nibbles of /T/R/ code-group after the last nibble of the FCS.
Scrambling
All the encoded data (including the idle, SSD, and ESD code-groups) is passed to the data scrambler to reduce EMI by spreading the power spectrum using a 10-bit scrambler seed loaded at the beginning.
Data conversion of parallel to serial, NRZ to NRZI, NRZI to MLT3
After being scrambled, the 5B type transmission data at 25MHz will be converted to a 125HMz serial bit stream by the parallel-to-serial function. The bit stream will be further converted from NRZ to NRZI format, unless the conversion function is bypassed by clearing ENRZI (bit 7 of XR10) to 0. After NRZI conversion, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3 code. By using MLT3 code, the frequency and energy content of the transmission signal is reduced in the UTP, making the system more easily compliant to FCC EMI specifications.
Wave-shaper and media signal driver
In order to reduce the energy of the harmonic frequency of transmission signals, the transceiver provides a wave-shaper prior the line driver to smooth the rising/falling edge of transmission signals while maintaining the waveforms' symmetry. The 100BASE-TX and 10BASE-T wave-shaped signals are both passed to the same media signal driver. This can simplify system design by employing a single external magnetic connection.
100BASE-TX receiving operation
For 100BASE-TX receiving operation, the transceiver provides the receiving functions of PMD, PMA, and PCS for incoming data signals through category 5 UTP cable and an isolation transformer with a 1:1 turns ratio. The receive transceiver portion includes the adaptive equalizer and baseline wander, MLT3 to NRZI data conversion, NRZI to NRZ conversion, serial to parallel conversion, a PLL for clock and data recovery, de-scrambler, and the 5B/4B decoder.
Adaptive equalizer and baseline wander
High speed signals over unshielded (or shielded) twisted pair cable will experience attenuation and phase shift. These effects depend on the signal frequency, cable type, cable length and the cable connectors. Robust circuits in the transceiver provide reliable adaptive equalizer and baseline wander compensation for amplitude attenuation and phase shift due to transmission line parasites.
bs O
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MLT3 to NRZI decoder and PLL for data recovery
Following adaptive equalizer, baseline wander, the transceiver converts the resulting MLT3 to NRZI code, which is passed to the Phase Lock Loop circuits in order to extract the synchronous clock and the original data.
22/82
STE10/100A
Functional description
Data conversions of NRZI to NRZ and serial to parallel
After the data is recovered, it will be passed to the NRZI-to-NRZ converter to produce a 125MHz serial bit stream. This serial bit stream will be packed to parallel 5B type for further processing. The NRZI to NRZ conversion may be bypassed by clearing ENRZI (bit 7 of XR10) to 0.
De-scrambling and decoding of 5B/4B
The parallel 5B type data is passed to the de-scrambler and 5B/4B decoder to restore it to its original MII nibble representation.
Carrier sensing
The carrier sense (CRS) signal is asserted when the transceiver detects any 2 noncontiguous zeros within any 10-bit boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected. In half duplex mode, CRS is asserted during packet transmission or receive; in full duplex mode, CRS is asserted only during packet reception.
10BASE-T transmission operation
The parallel-to-serial converter, Manchester Encoder, Link test, Jabber and the transmit wave-shaper and line driver functions described in the section of "Wave-Shaper and Media Signal Driver" of "100BASE-T Transmission Operation" are also provided for 10BASE-T transmission. Additionally, Collision detection and SQE test for half duplex application are provided.
10BASE-T receive operation
Carrier sense function, receiving filter, PLL for clock and data recovery, Manchester decoder, and serial to parallel converter functions are provided to support 10BASE-T reception.
Loop-back operation of transceiver
bs O
let o
Pr e
The transceiver provides internal loop-back (also called transceiver loop-back) operation for both 100BASE-TX and 10BASE-T operation. The loop-back function can be enabled by setting XLBEN (bit 14 of XR0) to 1. In loop-back mode, the TX and RX lines are isolated from the media. The transceiver also provides remote loop-back operation for 100BASE-TX operation. The remote loop-back operation can be enabled by setting ENRLB (bit 9 of XR10) to 1.
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In 100BASE-TX internal loop-back operation, the data is routed from the transmit output of NRZ-to-NRZI converter and looped back to the receive input of NRZI-to-NRZ converter. In 100BASE-TX remote loop-back operation, data is received from RX pins and passed through the receive path to the output of the data and clock recovery section, and then looped back to the input of the NRZI-to-MLT3 converter and out to the medium via the transmit line drivers. In 10BASE-T loop-back operation, the data is passed through the transmit path to the output of the Manchester encoder and then looped back into the input of the phase lock loop circuit in the receive path.
23/82
Functional description
STE10/100A
Full duplex and half duplex operation of transceiver
The transceiver can operate in either full duplex or half duplex network applications. In full duplex, both transmission and reception can take place simultaneously. In full duplex mode, collision (COL) signal is ignored and carrier sense (CRS) signal is asserted only when the transceiver is receiving. In half duplex mode, transmission and reception can not take place simultaneously. In half duplex mode, the collision signal is asserted when transmitted and received signals collide, and carrier sense is asserted during both transmission and reception.
Auto-negotiation operation
The auto-negotiation function provides the means to exchange information between the transceiver and the network partner to automatically configure both to take maximum advantage of their abilities. The auto-negotiation function is controlled by ANEN (bit 12 of XR0). During auto-negotiation information is exchanged with the network partner using fast link pulses (FLPs) - a burst of link pulses. There are 16 bits of signaling information contained in the link pulses which advertise to the remote partner the capabilities which are represented by the contents of ANA (register XR4). According to this information the partners find out their highest common capabilities by following the priority sequence listed below: 100BASE-TX full duplex 100BASE-TX half duplex 10BASE-T full duplex 10BASE-T half duplex
During power-up or reset, if auto-negotiation is enabled, the FLPs will be transmitted and the auto-negotiation function will proceed. Otherwise, auto-negotiation will not occur until ANEN (bit 12 of XR0) is set to 1. When the auto-negotiation is disabled, then network speed and duplex mode are selected by programming the XR0 register.
Power down operation
The transceiver is designed with a power-down feature which can reduce power consumption significantly. Since the power supply of the 100BASE-TX and 10BASE-T circuits are separate, the transceiver can turn off the circuit of either the 100BASE-TX or 10BASE-T when the other is active.
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24/82
STE10/100A
Functional description
3.5.3
Flow control in full duplex application
The PAUSE function is used to inhibit transmission of data frames for a specified period of time. The STE10/100A supports the full duplex protocol of IEEE802.3x. To support the PAUSE function, the STE10/100A implements the MAC Control Sub-layer functions to decode the MAC Control frames received from MAC control clients and to execute the relative requests accordingly. When full duplex mode and the PAUSE function are selected after Auto-Negotiation completes (refer to the configuration of XR8), the STE10/100A will enable the PAUSE function for flow control in a full duplex application. In this section we will describe how the STE10/100A implements the PAUSE function.
MAC control frame and PAUSE frame
Figure 14. MAC control frame format
6 octets 6 octets 2 octets 2 octets Destination address Source address Lenght/Type = 88-08h MAC control Opcode
MAC control parameter (min frame size 160) / 8 octets
Reserved (pads with zeroes)
The MAC control frame is distinguished from other MAC frames only by its length/type field identifier. The MAC control opcode defined in MAC control frame format for the PAUSE function is 0001h, and the PAUSE time is specified in the MAC control parameters field with 2 octets, representing an unsigned integer, in units of slot-times. The range of possible PAUSE times is 0 to 65535 slot-times. A valid PAUSE frame issued by a MAC control client (for example, a switch or a bridge) would contain:
O
bs
let o
Pr e
The destination address, set to the globally assigned 48 bit mulitcast address 0180-C2-00-00-01, or to the unicast address to which the MAC control client requests to inhibit its transmission of data frames. The MAC control opcode field set to 0001h.
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2 octets of PAUSE time specified in the MAC control parameter field to indicate the length of time for which the destination is requested to inhibit data frame transmission.
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Functional description
STE10/100A
Receive operation for PAUSE function
Upon reception of a valid MAC Control frame, the STE10/100A will start a timer for the length of time specified by the MAC control parameters field. When the timer value reaches zero, the STE10/100A exits the PAUSE state. However, a PAUSE frame will not affect the transmission of a frame that has been submitted to the MAC (i.e., once a transmit out of the MAC is begun, it can't be interrupted). Conversely, the STE10/100A will not begin to transmit a frame more than one slot-time after valid PAUSE frame is received a with a non-zero PAUSE time. If the STE10/100A receives a PAUSE frame with a zero PAUSE time value, the STE10/100A exits the PAUSE state immediately. Figure 15. Pause operation receive state diagram
Opcode = PAUSE function
Wait for transmission completed
Transmission_in_progress = false * DA = (01-80-C2-00-00-01 + Phys-address)
DA (01-80-C2-00-00-01 + Phys-address)
PAUSE function
n_slots_rx = data [17:32] Start pause_timer (n_slots_rx * slot_time)
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UCT
END PAUSE
PC00359
26/82
STE10/100A
Functional description
3.6
LED display operation
The STE10/100A provides 2 LED display modes; the detailed descriptions of their operation are described in the pin description section.
First mode 3 LED displays
100Mbps (on) or 10Mbps (off) Link (Remains on when link ok) or activity (Blinks at 10Hz when receiving or transmitting collision-free) FD (Remains on when in full duplex mode) or collision (Blinks at 20Hz when collisions detected)
Second mode 4 LED displays
100 Link (On when 100M link ok) 10 Link (On when 10M link ok) Activity (Blinks at 10Hz when receiving or transmitting) FD (Remains on when in full duplex mode) or collision (Blinks at 20Hz when collisions detected)
3.7
3.7.1
Reset operation
Reset whole chip
There are two ways to reset the STE10/100A:
Hardware reset Via RST# pin (to ensure proper reset operation, the RST# signal should be asserted at least 100ms) Software reset Via SWR (bit 0 of CSR0) being set to 1 (the STE10/100A will reset all circuits except the transceivers and configuration registers, set registers to their default values, and will clear SWR) and set XRST(XR0, bit 15) to reset the transceivers.
3.7.2
Reset transceiver only
bs O
let o
When XRST (bit 15 of XR0) is set to 1, the transceiver will reset its circuits, will initialize its registers to their default values, and clear XRST.
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27/82
Functional description
STE10/100A
3.8
Wake on LAN function
The STE10/100A can assert a signal to wake up the system when it has received a Magic Packet from the network. The wake on LAN operation is described as follow.
The Magic Packet format
Valid destination address that can pass the address filter of the STE10/100A Payload of the frame including at least 6 contiguous `FF' followed immediately by 16 repetitions of IEEE address The frame can contain multiple `six FF + sixteen IEEE address' pattern Valid CRC
The wake on LAN operation
The wake on LAN enable function is controlled by WOL (bit 18 of CSR18), which is loaded from EEPROM after reset or programmed by driver software. If WOL is set and the STE10/100A receives a Magic Packet, it will assert the PME# signal (active low) to indicate reception of a wake up frame and will set the PME status bit (bit 15 of CSR20).
3.9
ACPI power management function
The STE10/100A has a built-in capability for power management (PM) which is controlled by the host system. The STE10/100A will provide: Compatibility with device class power management reference specification Network device class, draft proposal v0.9, october 1996 Compatibility with ACPI, Rev 1.0, december 22, 1996 Compatibility with PCI bus power management interface specification, Rev 1.0, january 6, 1997 Compatibility with AMD Magic PacketTM Technology.
3.9.1
Power states
DO (Fully on)
O
bs
let o
In this state the STE10/100A operates with full functionality and consumes normal power. While in the D0 state, if the PCI clock is lower than 16MHz, the STE10/100A may not receive or transmit frames properly.
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D1, D2, and D3hot
In these states, the STE10/100A doesn't respond to any accesses except configuration space and full function context in place. The only network operation the STE10/100A can initiate is a wake-up event.
D3cold (Power removed)
In this state all function context is lost. When power is restored, a PCI reset must be asserted and the function will return to D0.
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STE10/100A
Functional description
D3hot (Software visible D3)
When the STE10/100A is brought back to D0 from D3hot the software must perform a full initialization. The STE10/100A in the D3hot state responds to configuration cycles as long as power and clock are supplied. This requires the device to perform an internal reset and return to a power-up reset condition without the RST# pin asserted. Table 3. Power stage
Function context Supported Clock Power actions to function Full speed Full power Any PCI transaction PCI configuration access PCI configuration access(B0, B1) Supported actions from function Any PCI transaction or interrupt Only wake-up events
Device PCI bus state state
D0
B0
Full function context in place
D1
B0, B1
Configuration maintained. No Tx Stopped to and Rx except wake- full speed up events Stopped to full speed
D2
Configuration B0, B1, maintained. No Tx B2 and Rx
D3hot
Configuration lost, B0, B1, full initialization Stopped to B2 required upon return full speed to D0 All configuration lost. Power-on defaults in No clock place on return to D0
D3cold
B3
bs O
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No power
PCI configuration access(B0, B1)
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Power-on reset
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Registers and descriptors description
STE10/100A
4
Note:
Registers and descriptors description
There are three kinds of registers within the STE10/100A: STE10/100A configuration registers, PCI control/status registers, and transceiver control/status registers.
The STE10/100A configuration registers are used to initialize and configure the STE10/100A and for identifying and querying the STE10/100A. The PCI control/status registers are used to communicate between the host and STE10/100A. The host can initialize, control, and read the status of the STE10/100A through mapped I/O or memory address space. The STE10/100A contains 11 16-bit registers to supported transceiver control and status. They include 7 basic registers which are defined according to clause 22 "Reconciliation Sub-layer and Media Independent Interface" and clause 28 "Physical Layer link signaling for 10 Mb/s and 100 Mb/s auto-negotiation on twisted pair" of the IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status. The STE10/100A also provides receive and transmit descriptors for packet buffering and management.
4.1
STE10/100A configuration registers
An STE10/100A software driver can initialize and configure the chip by writing its configuration registers. The contents of configuration registers are set to their default values upon power-up or whenever a hardware reset occurs, but their settings remain unchanged whenever a software reset occurs. The configuration registers are byte, word, and double word accessible. Table 4.
Offset 00h 04h 08h 0ch
STE10/100A configuration registers list
Index CR0 CR1 CR2
O
bs
let o
ro P e
10h 14h 2ch 30h 34h 3ch 40h 80h c0h c4h
CR3
uc d
(s) t
LID CSC CC LT IOBA MBA SID BRBA CP CINT DS SIG PMR0 PMR1
Name
so Ob Latency timer IO base address
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Description
Loaded device ID and vendor ID Configuration status and command Class code and revision number
CR4 CR5
Memor y base address Subsystem ID and vendor ID Boot ROM base address (ROM size = 128Kbit) Capability pointer Configuration interrupt Driver space for special purpose Signature of STE10/100A Power management register 0 Power management register 1
CR11 CR12 CR13
CR15 CR16 CR32 CR48 CR49
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STE10/100A Table 5.
offset 00h 04h 08h 0ch 10h 14h 18h~28h 2ch 30h 34h 38h 3ch 40h 80h c0h c4h PMC Reserved Max_Lat(1) Reser ved Min-Gnt(1) Reserved Subsystem ID(1) Base class code ------
Registers and descriptors description STE10/100A configuration registers table
b31 ----------Device ID* Status Subclass ----------Latency timer Base I/O address Base memory address Reserved Subsystem vendor ID(1) Boot ROM base address Cap_Ptr Reserved Interrupt pin Driver space Signature of STE10/100A b16 b15 ---------Vendor ID
(1)
b0
Command Revision # Step #
Cache line size
Interrupt line
Next_Item_Ptr
1. Automatically recalled from EEPROM when PCI reset is deserted DS(40h), bit15-8, is read/write able register SIG(80h) is hard wired register, read only
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Reserved
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Cap_ID
31/82
Registers and descriptors description
STE10/100A
4.1.1
STE10/100A configuration registers description
Table 6.
Bit #
Configuration registers description
Name Description Default RW type
CR0 (offset = 00h), LID - Loaded identification number of device and vendor 31~16 15~0 LDID LVID Loaded device ID, the device ID number loaded from serial EEPROM Loaded vendor ID, the vendor ID number loaded from serial EEPROM From EEPROM From EEPROM R/O R/O
From EEPROM: Loaded from EEPROM CR1 (offset = 04h), CSC - Configuration command and status Status parity error. 1: means that STE10/100A detected a parity error. This bit will be set even if the parity error response (bit 6 of CR1) is disabled. Status system error. 1: means that STE10/100A asserted the system error pin.
31
SPE
0
30
SES
29
SMA
Status master abort. 1: means that STE10/100A received a master abort and has terminated a master transaction. Status target abort. 1: means that STE10/100A received a target abort and has terminated a master transaction. Reserved
28 27 26, 25
STA --SDST
Status device select timing. Indicates the timing of the chip's assertion of device select. 01: indicates a medium assertion of DEVSEL#. Status data parity report. 1: when three conditions are met: a. STE10/100A asserted parity error (PERR#) or it detected parity error asserted by another device. b. STE10/100A is operating as a bus master. c. STE10/100A's parity error response bit (bit 6 of CR1) is enabled.
bs O
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24 23 ---
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0 0 0
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R/W R/W
R/W
R/W
01
R/O
SDPR
0
R/W
SFBB
Status fast back-to-back. Always 1, since STE10/100A has the ability to accept fast back to back transactions. Reserved
1
R/O
22~21
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STE10/100A Table 6.
Bit #
Registers and descriptors description Configuration registers description (continued)
Name Description New capabilities. Indicates whether the STE10/100A provides a list of extended capabilities, such as PCI power management. 1: the STE10/100A provides the PCI management function. 0: the STE10/100A doesn't provide new capabilities. Reserved Command system error response. 1: enable system error response. The STE10/100A will assert SERR# when it finds a parity error during the address phase. Reserved Command parity error response. 0: disable parity error response. STE10/100A will ignore any detected parity error and keep on operating. Default value is 0. 1: enable parity error response. STE10/100A will assert system error (bit 13 of CSR5) when a parity error is detected. Reserved Default RW type
20
NC
Same as bit 19 of CSR18
RO
19~ 9
---
8
CSE
1
R/W
7
---
6
CPE
5~ 3
---
2
CMO
Command master operation ability. 0: disable the STE10/100A bus master ability. 1: enable the PCI bus master ability. Default value is 1 for normal operation. Command memory space access. 0: disable the memory space access ability. 1: enable the memory space access ability. Command I/O space access. 0: enable the I/O space access ability. 1: disable the I/O space access ability.
1
CMSA
0
CIOSA
R/W: Read and write able. RO: Read able only.
bs O
let o
CR2 (offset = 08h), CC - Class code and revision number 31~24 23~16 15~ 8 7~4 3~0 BCC SC --RN SN Base class code. It means STE10/100A is a network controller. Subclass code. It means STE10/100A is a fast ethernet controller. Reserved Revision number, identifies the revision number of STE10/100A Step number, identifies the STE10/100A steps within the current revision Ah 1h RO RO 02h 00h RO RO
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R/W R/W
1
R/W
1
R/W
RO: Read only
33/82
Registers and descriptors description Table 6.
Bit #
STE10/100A
Configuration registers description (continued)
Name Description Default RW type
CR3 (offset = 0ch), LT - Latency timer 31~16 --Reserved Latency timer. This value specifies the latency timer of the STE10/100A in units of PCI bus clock cycles. Once the STE10/100A asserts FRAME#, the latency timer starts to count. If the latency timer expires and the STE10/100A is still asserting FRAME#, the STE10/100A will terminate the data transaction as soon as its GNT# is removed. Cache line size. This value specifies the system cache line size in units of 32-bit double words (DW). The STE10/100A supports cache line sizes of 8, 16, or 32 DW. CLS is used by the STE10/100A driver to program the cache alignment bits (bit 14 and 15 of CSR0) which are used for cache oriented PCI commands, for example, memory-read-line, memory-read-multiple, and memory-write-andinvalidate.
15~ 8
LT
40h
R/W
7~0
CLS
08h
CR4 (offset = 10h), IOBA - I/O base address 31~ 7 6~1 0 IOBA --IOSI
I/O base address. This value indicate the base address of PCI control and status register (CSR0~28), and transceiver registers (XR0~10). Reserved
I/O space indicator. 1: means that the configuration registers map into I/O space.
CR5 (offset = 14h), MBA - Memory base address
31~ 7
MBA
6~1
bs O
let o
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--0
du
Memory base address. This value indicate the base address of PCI control and status register(CSR0~28), and transceiver registers(XR0~10). Reserved
(s) ct
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0 1
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R/W
R/W
RO
0
R/W
IOSI
Memory space indicator. 1: means that the configuration registers map into I/O space.
0
RO
CR11 (offset = 2ch), SID - Subsystem ID 31~16 15~ 0 SID SVID Subsystem ID. This value is loaded from EEPROM as a result of power-on or hardware reset. Subsystem vendor ID. This value is loaded from EEPROM as a result power-on or hardware reset. From EEPROM From EEPROM RO RO
CR12 (offset = 30h), BRBA - Boot ROM base address. This register should be initialized before accessing the boot ROM space.
34/82
STE10/100A Table 6.
Bit #
Registers and descriptors description Configuration registers description (continued)
Name Description Boot ROM base address. This value indicates the address mapping of the boot ROM field as well as defining the boot ROM size. The values of bit 16~10 are set to 0 indicating that the STE10/100A supports up to 128Kbit of boot ROM. Reserved Boot ROM enable. The STE10/100A will only enable its boot ROM access if both the memory space access bit (bit 1 of CR1) and this bit are set to 1. 1: enable boot ROM. (If bit 1 of CR1 is also set). Default RW type
31~10
BRBA
X: b31~17 0: b16~10
R/W RO
9~1
---
RO R/W R/W
0
BRE
0
R/W
CR13 (offset = 34h), CP - Capabilities pointer 31~8 7~0 --CP Reserved Capabilities pointer C0h
CR15 (offset = 3ch), CI - Configuration interrupt Max_Lat register. This value indicates how often the STE10/100A needs to access to the PCI bus in units of 250ns. This value is loaded from serial EEPROM as a result of power-on or hardware reset.
31~24
ML
23~16
MG
Min_Gnt register. This value indicates how long the STE10/100A needs to retain the PCI bus ownership whenever it initiates a transaction, in units of 250ns. This value is loaded from serial EEPROM as a result power-on or hardware reset. Interrupt Pin. This value indicates one of four interrupt request pins to which the STE10/100A is connected. 01h: means the STE10/100A always connects to INTA#.
15~ 8
IP
7~0
O
bs
let o
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IL ---
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Ob -
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From EEPROM
uc d
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RO RO RO
From EEPROM
01h
RO
Interrupt Line. This value indicates the system interrupt request lines to which the INTA# of STE10/100A is routed. The BIOS will fill this field when it initializes and configures the system. The STE10/100A driver can use this value to determine priority and vector information.
0
R/W
CR16 (offset = 40h), DS - Driver space for special purpose 31~16 Reserved Driver space for implementation-specific purpose. Since this area won't be cleared upon software reset, an STE10/100A driver can use this R/W area as user-specified storage. Reserved
15~8
DS
0
R/W
7~0
---
CR32 (offset = 80h), SIG - Signature of STE10/100A
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Registers and descriptors description Table 6.
Bit # 31~16 15~0
STE10/100A
Configuration registers description (continued)
Name DID VID Description Device ID, the device ID number of the STE10/100A Vendor ID, the vendor ID number of STMicroelectronics Default 2774h 104Ah RW type RO RO
CR48 (offset = c0h), PMR0, Power management register 0 PME_Suppor t. The STE10/100A will assert PME# signal while in the D0, D1, D2, D3hot and D3cold power state. The STE10/100A supports Wake-up from the above five states. Bit 31 (support wake-up from D3cold) is loaded from EEPROM after power-up or hardware reset. To support the D3cold wake-up function, an auxiliary power source will be sensed during reset by the STE10/100A Vaux_detect pin. If sensed low, PSD3c will be set to 0; if sensed high, and if D3CS (bit 31of CSR18) is set (CSR18 bits 16~31 are recalled from EEPROM at reset), then bit 31 will be set to 1. D2_Suppor t. The STE10/100A supports the D2 Power management state. D1_Suppor t. The STE10/100A supports the D1 Power management state.
31 30 29 28 27
PSD3c, PSD3h, PSD2, PSD1, PSD0
X1111b
RO
26 25
D2S D1S
24~22
AUXC
Aux current. These three bits report the maximum 3.3Vaux current requirements for STE10/100A chip. If bit 31 of PMR0 is `1', the default value is 111b, meaning the STE10/100A needs 375 mA to support remote wake-up in D3cold power state. Otherwise, the default value is 000b, meaning the STE10/100A does not support remote wake-up from D3cold power state. The device specific initialization bit indicates whether any special initialization of this function is required before the generic class device driver is able to use it. 0: indicates that the function does not require a device-specific initialization sequence following transition to the D0 uninitialized state. Reserved PME Clock. Indicates that the STE10/100A does not rely on the presence of the PCI clock for PME# operation. Version. The value of 010b indicates that the STE10/100A complies with revision 1.0a of the PCI power management interface specification. Next item pointer. This value is always 0h, indicating that there are no additional items in the capabilities list.
O
bs
let o
Pr e
21 20 19
du o
DSI ---
(s) ct
so Ob -
te le
ro P
uc d
1 1 XXXb
s) t(
RO RO
RO
0
RO
PMEC
0
RO
18~16
VER
010b
RO
15~8
NIP
00h
RO
36/82
STE10/100A Table 6.
Bit # 7~0
Registers and descriptors description Configuration registers description (continued)
Name CAPID Description Capability identifier. This value is always 01h, indicating the link list item as being the PCI power management registers. Default 01h RW type RO
CR49 (offset = c4h), PMR1, Power management register 1 31~16 --Reserved PME_Status. This bit is set whenever the STE10/100A detects a wake-up event, regardless of the state of the PME-En bit. Writing a "1" to this bit will clear it, causing the STE10/100A to deassert PME# (if so enabled). Writing a "0" has no effect. If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not support PME# generation from D3cold), this bit is by default 0; otherwise, PMEST is cleared upon powerup reset only and is not modified by either hardware or software reset. Data_Scale. Indicates the scaling factor to be used when interpreting the value of the data register. This field is required for any function that implements the data register. The STE10/100A does not support data register and Data_Scale. Data_Select. This four bit field is used to select which data is to be reported through the data register and Data_Scale field. This field is required for any function that implements the data register. The STE10/100A does not support Data_select.
15
PMEST
X
R/W1C(1)
14,13
DSCAL
12~9
DSEL
8
bs O
let o
ro P e
PME_En. When set, enables the STE10/100A to assert PME#. When cleared, disables the PME# assertion. PME_En If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not support PME# generation from D3cold), this bit is by default 0; otherwise, PME_En is cleared upon power up reset only and is not modified by either hardware or software reset.
du
(s) ct
so Ob -
te le
ro P
uc d
00b 0000b
s) t(
RO
R/W
X
R/W
37/82
Registers and descriptors description Table 6.
Bit # 7~2
STE10/100A
Configuration registers description (continued)
Name --Reserved PowerState. This two bit field is used both to determine the current power state of the STE10/100A and to place the STE10/100A in a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported state to this field, the write operation will complete normally on the bus, but the data is discarded and no state change occurs. Description Default 0 0 00b RW type RO
1,0
PWRS
00b
R/W
1. R/W1C: Read only and write one cleared
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
38/82
STE10/100A
Registers and descriptors description
4.2
PCI control/status registers
Table 7. PCI control/status registers list
Index CSR0 CSR1 CSR2 CSR3 CSR4 CSR5 CSR6 CSR7 CSR8 CSR9 CSR10 CSR11 CSR12 CSR13 CSR14 CSR15 CSR16 CSR17 Name PAR TDR RDR RDB TDB SR NAR IE R LPC SPR --TMR --WCSR WPDR PCI access register Transmit demand register Receive demand register Receive descriptor base address Transmit descriptor base address Status register Network access register interrupt enable register Lost packet counter Serial port register Reserved Timer Reserved Descriptions Offset from base address of CSR 00h 08h 10h 18h 20h 28h 30h 38h 40h 48h 50h 58h 60h 68h 70h 78h 80h 84h 88h 8ch 90h
Wake-up control/status register Wake-up pattern data register
WTMR
ACSR5 ACSR7 CR
CSR18
bs O
let o
Pr e
94h 98h 9ch a0h a4h a8h ach b0h
du o
CSR19
CSR20 CSR21 CSR22
(s) ct
so Ob Reserved Reserved
te le
ro P
uc d
s) t(
Watchdog timer Status register 2
Interrupt enable register 2
Command register PCI bus performance counter Power management command and status
PCIC
PMCSR ----TXBR FROM PAR0 PAR1 MAR0 MAR1
CSR23 CSR24 CSR25 CSR26 CSR27 CSR28
Transmit burst counter/time-out register Flash(boot) ROM port Physical address register 0 Physical address register 1 Multicast address hash table register 0 Multicast address hash table register 1
39/82
Registers and descriptors description Table 8.
Bit #
STE10/100A
Control/status register description
Name Description Default RW type
CSR0 (offset = 00h), PAR - PCI access register 31~25 --Reserved Memory write and invalidate enable. 1: enable STE10/100A to generate memory write invalidate command. The STE10/100A will generate this command while writing full cache lines. 0: disable generating memory write invalidate command. The STE10/100A will use memory write commands instead. Memory read line enable. 1: enable STE10/100A to generate memory read line command when read access instruction reaches the cache line boundary. If the read access instruction doesn't reach the cache line boundary then the STE10/100A uses the memory read command instead. Reserved
24
MWIE
0
R/W*
23
MRLE
0
22
---
21
MRME
Memory read multiple enable. 1: enable STE10/100A to generate memory read multiple commands when reading a full cache line. If the memory is not cache-aligned, the STE10/100A uses the memory read command instead. Reserved
20~19
---
18,17
TAP
bs O
let o
Pr e
16
du o
---
Transmit auto-polling in transmit suspended state. 00: disable auto-polling (default) 01: polling own-bit every 200 us 10: polling own-bit every 800 us 11: polling own-bit every 1600 us
(s) ct
so Ob -
te le
ro P
uc d
0
s) t(
R/W*
R/W*
00
R/W*
Reserved
15, 14
CAL
Cache alignment. Address boundary for data burst, set after reset 00: reserved (default) 01: 8 DW boundary alignment 10: 16 DW boundary alignment 11: 32 DW boundary alignment Programmable burst length. This value defines the maximum number of DW to be transferred in one DMA transaction. Value: 0 (unlimited), 1, 2, 4, 8, 16 (default), 32
00
R/W*
13 ~ 8
PBL
0 0 00
R/W*
40/82
STE10/100A Table 8.
Bit #
Registers and descriptors description Control/status register description (continued)
Name Description Big or little endian selection. 0: little endian (for example INTEL) 1: big endian (only for data buffer) Descriptor skip length. Defines the gap between two descriptors in the units of DW. Bus arbitration 0: receive operations have higher priority 1: transmit operations have higher priority Software reset 1: Reset all internal hardware (excluding transceivers and configuration registers). This signal will be cleared by the STE10/100A itself after the reset process is completed. Default RW type
7
BLE
0
R/W*
6~2
DSL
0
R/W*
1
BAR
0
R/W*
0
SWR
0
R/W*
R/W* = Before writing the transmit and receive operations should be stopped.
CSR1 (offset = 08h), TDR - Transmit demand register Transmit poll demand. While the STE10/100A is in the suspended state, a write to this register (any value) will trigger the read-tx-descriptor process, which checks the own-bit; if set, the transmit process is then started.
31~ 0
TPDM
R/W* = Before writing the transmit process should be in the suspended state
CSR2 (offset = 10h), RDR - Receive demand register
31 ~ 0
RPDM
R/W* = Before writing the receive process should be in the suspended state
bs O
let o
CSR3 (offset = 18h), RDB - Receive descriptor base address 31~ 2 1, 0 SAR Star t address of receive descriptor Must be 00, DW boundary 0 00 R/W* RO
Pr e
du o
Receive poll demand. While the STE10/100A is in the suspended state, a write to this register (any value) will trigger the read-rx-descriptor process, which checks the own-bit, if set, the process to move data from the FIFO to buffer is then started.
(s) ct
so Ob -
te le
ro P
uc d
s) t(
R/W*
FFFFFFFFh
FFFFFFFFh
R/W*
RBND
R/W* = Before writing the receive process should be stopped
CSR4 (offset = 20h), TDB - Transmit descriptor base address 31~ 2 1, 0 SAT TBND Star t address of transmit descriptor Must be 00, DW boundary 0 00 R/W* RO
R/W* = Before writing the transmit process should be stopped
41/82
Registers and descriptors description Table 8.
Bit #
STE10/100A
Control/status register description (continued)
Name Description Default RW type
CSR5 (offset = 28h), SR - Status register 31~ 26 ---Reserved Bus error type. This field is valid only when bit 13 of CSR5(fatal bus error) is set. There is no interrupt generated by this field. 000: parity error, 001: master abort, 010: target abort 011, 1xx: reserved Transmit state. Reports the current transmission state only, no interrupt will be generated. 000: stop 001: read descriptor 010: transmitting 011: FIFO fill, read the data from memory and put into FIFO 100: reserved 101: reserved 110: suspended, unavailable transmit descriptor or FIFO overflow 111: write descriptor Receive state. Reports current receive state only, no interrupt will be generated. 000: stop 001: read descriptor 010: check this packet and pre-fetch next descriptor 011: wait for receiving data 100: suspended 101: write descriptor 110: flush the current FIFO 111: FIFO drain, move data from receiving FIFO into memory
25~ 23
BET
000
RO
22~ 20
TS
000
19~17
RS
bs O
let o
Pr e
16
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
RO
000
RO
NISS
Normal interrupt status summary. Set if any of the following bits of CSR5 are asserted: TCI, transmit completed interrupt (bit 0) TDU, transmit descriptor unavailable (bit 2) RCI, receive completed interrupt (bit 6)
0
RO/LH*
42/82
STE10/100A Table 8.
Bit #
Registers and descriptors description Control/status register description (continued)
Name Description Abnormal interrupt status summary. Set if any of the following bits of CSR5 are asserted: TPS, transmit process stopped (bit 1) TJT, transmit jabber timer time-out (bit 3) TUF, transmit under-flow (bit 5) RDU, receive descriptor unavailable (bit 7) RPS, receive process stopped (bit 8) RWT, receive watchdog time-out (bit 9) GPTT, general purpose timer time-out (bit 11) FBE, fatal bus error (bit 13) Reserved Fatal bus error. 1: on occurrence of parity error, master abort, or target abort (see bits 25~23 of CSR5). The STE10/100A will disable all bus access. A software reset is required to recover from a parity error. Reserved Default RW type
15
AISS
0
RO/LH*
14
----
13
FBE
12 11 10 9 8
--GPTT --RWT RPS
General purpose timer timeout, based on CSR11 timer register Reserved
Receive watchdog timeout, based on CSR15 watchdog timer register Receive process stopped, receive state = stop Receive descriptor unavailable. 1: when the next receive descriptor can not be obtained by the STE10/100A. The receive process is suspended in this situation. To restart the receive process, the ownership bit of the next receive descriptor should be set to STE10/100A and a receive poll demand command should be issued (if the receive poll demand is not issued, the receive process will resume when a new recognized frame is received). Receive completed interrupt. 1: when a frame reception is completed. Transmit under-flow. 1: when an under-flow condition occurs in the transmit FIFO during transmitting. The transmit process will enter the suspended state and report the under-flow error on bit 1 of TDES0.
bs O
let o
Pr e
7 6
du o
(s) ct
Ob -
so
te le
ro P
uc d
0 0
s) t(
RO/LH* RO/LH*
0 0
RO/LH* RO/LH*
RDU
0
RO/LH*
RCI
0
RO/LH*
5
TUF
0
RO/LH*
43/82
Registers and descriptors description Table 8.
Bit # 4
STE10/100A
Control/status register description (continued)
Name --Reserved Transmit jabber timer time-out. 1: when the transmit jabber timer expires. The transmit processor will enter the stop state and TO (bit 14 of TDES0, transmit jabber time-out flag) will be asserted. Transmit descriptor unavailable. 1: when the next transmit descriptor can not be obtained by the STE10/100A. The transmission process is suspended in this situation. To restart the transmission process, the ownership bit of the next transmit descriptor should be set to STE10/100A and, if the transmit automatic polling is not enabled, a transmit poll demand command should then be issued. Transmit process stopped. 1: while transmit state = stop Transmit completed interrupt. 1: set when a frame transmission completes with IC (bit 31 of TDES1) asserted in the first transmit descriptor of the frame. Description Default RW type
3
TJ T
0
RO/LH*
2
TDU
0
RO/LH*
1
TPS
0
TCI
LH = High Latching and cleared by writing 1.
CSR6 (offset = 30h), NAR - Network access register 31~22 21 20 --SF --Reserved
O
bs
let o
18~16
Pr e
19
SQE
od
----TR
ct u
Store and forward for transmit 0: disable 1: enable, ignore the transmit threshold setting Reserved
(s)
so Ob -
te le
ro P
uc d
0
0
s) t(
RO/LH*
RO/LH*
0
R/W*
SQE disable 0: enable SQE function for 10BASE-T operation. The STE10/100A provides SQE test function for 10BASE-T half duplex operation. 1: disable SQE function. Reserved Transmit threshold control 00: 128-bytes (100Mbps), 72-bytes (10Mbps) 01: 256-bytes (100Mbps), 96-bytes (10Mbps) 10: 512-bytes (100Mbps), 128-bytes (10Mbps) 11: 1024-bytes (100Mbps), 160-bytes (10Mbps) Stop transmit 0: stop (default) 1: start
1
R/W*
15~14
00
R/W*
13
ST
0
R/W
44/82
STE10/100A Table 8.
Bit #
Registers and descriptors description Control/status register description (continued)
Name Description Force collision mode 0: disable 1: generate collision upon transmit (for testing in loop-back mode) Operating mode 00: normal 01: MAC loop-back, regardless of contents of XLBEN (bit 14 of XR0, XCVR loop-back) 10,11: reserved Reserved Multicast mode 1: receive all multicast packets Promiscuous mode 1: receive any good packet. 0: receive only the right destination address packets Stop back-off counter 1: back-off counter stops when carrier is active, and resumes when carrier is dropped. 0: back-off counter is not effected by carrier Reserved 0 R/W*** Default RW type
12
FC
0
R/W**
11, 10
OM
00
R/W**
9, 8 7
--MM
6
PR
1
5
SBC
4
---
3
PB
Pass bad packet 1: receives any packets passing address filter, including runt packets, CRC error, truncated packets. For receiving all bad packets, PR (bit 6 of CSR6) should be set to 1. 0: filters all bad packets Reserved
2
bs O
let o
Pr e
1 0
du o
SR
---
Star t/stop receive 0: receive processor will enter stop state after the current frame reception is completed. This value is effective only when the receive processor is in the running or suspending state. Note: In "Stop Receive" state, the PAUSE packet and remote wake up packet will not be affected and can be received if the corresponding function is enabled. 1: receive processor will enter running state. Reserved
(s) ct
so Ob -
te le
ro P
uc d
0
s) t(
R/W***
R/W**
0
R/W***
0
R/W
---
W* = only write when the transmit processor stopped. W** = only write when the transmit and receive processor both stopped. W*** = only write when the receive processor stopped.
45/82
Registers and descriptors description Table 8.
Bit #
STE10/100A
Control/status register description (continued)
Name Description Default RW type
CSR7 (offset = 38h), IER - Interrupt enable register 31~17 16 --NIE Reserved Normal interrupt enable. 1: enables all the normal interrupt bits (see bit 16 of CSR5). Abnormal interrupt enable. 1: enables all the abnormal interrupt bits (see bit 15 of CSR5). Reserved Fatal bus error interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the fatal bus error interrupt. Reserved General purpose timer interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the general purpose timer expired interrupt. Reserved 0 R/W 0 R/W
15 14 13 12
AIE --FBEIE ---
0
R/W
11
GPTIE
10
---
9
RWTIE
Receive watchdog time-out interrupt enable 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the receive watchdog time-out interrupt. Receive stopped interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the receive stopped interrupt. Receive descriptor unavailable interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the receive descriptor unavailable interrupt. Receive completed interrupt enable. 1: this bit in conjunction with NIE (bit 16 of CSR7) will enable the receive completed interrupt. Transmit under-flow interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the transmit under-flow interrupt. Reserved
8
RSIE
7
RUIE
bs O
let o
Pr e
6 5 4
du o
(s) ct
so Ob -
te le
ro P
uc d
0 0
s) t(
R/W R/W
0
R/W
0
R/W
RCIE
0
R/W
TUIE
0
R/W
---
3
TJTTIE
Transmit jabber timer time-out interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the transmit jabber timer timeout interrupt.
0
R/W
46/82
STE10/100A Table 8.
Bit #
Registers and descriptors description Control/status register description (continued)
Name Description Transmit descriptor unavailable interrupt enable. 1: this bit in conjunction with NIE (bit 16 of CSR7) will enable the transmit descriptor unavailable interrupt. Transmit processor stopped interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the transmit processor stopped interrupt. Transmit completed interrupt enable. 1: this bit in conjunction with NIE (bit 16 of CSR7) will enable the transmit completed interrupt. Default RW type
2
TDUIE
0
R/W
1
TPSIE
0
R/W
0
TCIE
0
R/W
CSR8 (offset = 40h), LPC - Lost packet counter 31~17 16 --LPCO Reserved Lost packet counter overflow. 1: when lost packet counter overflow occurs. Cleared after read. Lost packet counter. The counter is incremented whenever a packet is discarded as a result of no host receive descriptors being available. Cleared after read. 0
15~0
LPC
CSR9 (offset = 48h), SPR - Serial port register 31~15 14 --SRC Reserved
Serial EEPROM read control. When set, enables read access from EEPROM, when SRS (CSR9 bit 11) is also set. Serial EEPROM write control. When set, enables write access to EEPROM, when SRS (CSR9 bit 11) is also set. Reserved
13 12
SWC ---
bs O
let o
ro P e
11 --3
du
(s) ct
so Ob -
eP let
od r
0
uc
s) t(
RO/LH
RO/LH
0
R/W
0
R/W
SRS
Serial EEPROM select. When set, enables access to the serial EEPROM (see description of CSR9 bit 14 and CSR9 bit 13). Reserved Serial EEPROM data out. This bit serially shifts data from the EEPROM to the STE10/100A. Serial EEPROM data in. This bit serially shifts data from the STE10/100A to the EEPROM.
0
R/W
10~4
SDO
1
RO
2
SDI
1
R/W
47/82
Registers and descriptors description Table 8.
Bit #
STE10/100A
Control/status register description (continued)
Name Description Serial EEPROM clock. High/Low this bit to provide the clock signal for EEPROM. Serial EEPROM chip select. 1: selects the serial EEPROM chip. Default RW type
1
SCLK
1
R/W
0
SCS
1
R/W
CSR11 (offset = 58h), TMR - General - Purpose timer 31~17 16 --COM Reserved Continuous operation mode. 1: sets the general-purpose timer in continuous operating mode. General-purpose timer value. Sets the counter value. This is a count-down counter with a cycle time of 204us. 0 R/W
15~0
GTV
0
CSR13 (offset = 68h), WCSR Wake-up control/status register 31 30 29 28 27 26 25 24-18 17 --CRCT WP1E WP2E WP3E WP4E WP5E --LinkOFF Reserved CRC-16 type 0: Initial contents = 0000h 1: Initial contents = FFFFh
Wake-up pattern one matched enable Wake-up pattern two matched enable
Wake-up pattern three matched enable Wake-up pattern four matched enable Wake-up pattern five matched enable Reserved
O
bs
let o
15-11
Pr e
16 10
du o
---
Link off detect enable. The STE10/100A will set the LSC bit of CSR13 after it has detected that link status has switched from ON to OFF.
(s) ct
Ob -
so
te le
ro P
uc d
0 0 0 0 0 0
s) t(
R/W R/W R/W R/W R/W R/W
R/W
0
R/W
LinkON
Link on detect enable. The STE10/100A will set the LSC bit of CSR13 after it has detected that link status has switched from OFF to ON.
0
R/W
Reserved Wake-up frame received enable. The STE10/100A will include the "Wake-up Frame Received" event in its set of wake-up events. If this bit is set, STE10/100A will assert PMEST bit of PMR1 (CR49) after STE10/100A has received a matched wake-up frame.
WFRE
0
R/W
48/82
STE10/100A Table 8.
Bit #
Registers and descriptors description Control/status register description (continued)
Name Description Default RW type
9
MPRE
Magic packet received enable. The STE10/100A will include the "Magic Packet Received" event in Default 1 if PM its set of wake-up events. If this bit is set, & WOL bits of STE10/100A will assert PMEST bit of PMR1 CSR 18 are (CR49) after STE10/100A has received a Magic both enabled. packet. Link status changed enable. The STE10/100A will include the "Link status changed" event in its set of wake-up events. If this bit is set, STE10/100A will assert PMEST bit of PMR1 after STE10/100A has detected a link status changed event. Reserved Wake-up frame received, 1: Indicates STE10/100A has received a wakeup frame. It is cleared by writing a 1 or upon power-up reset. It is not affected by a hardware or software reset. Magic packet received, 1: Indicates STE10/100A has received a magic packet. It is cleared by writing a 1 or upon powerup reset. It is not affected by a hardware or software reset. Link status changed, 1: Indicates STE10/100A has detected a link status change event. It is cleared by writing a 1 or upon power-up reset. It is not affected by a hardware or software reset.
R/W
8
LSCE
0
R/W
7-3
---
2
WFR
X
1
MPR
0
LSC
R/W1C*, Read only and write one cleared.
CSR14 (offset = 70h), WPDR Wake-up pattern data register Offset
bs O
let o
Pr e
0000h 0004h 0008h 000ch 0010h 0014h 0018h 001ch 0020h
31
du o
(s) ct
so Ob 16 15
te le
ro P
uc d
X X
s) t(
R/W1C*
R/W1C*
R/W1C*
8
7
0
Wake-up pattern 1 mask bits 31:0 Wake-up pattern 1 mask bits 63:32 Wake-up pattern 1 mask bits 95:64 Wake-up pattern 1 mask bits 127:96 CRC16 of pattern 1 Reserved Wake-up pattern 1 offset
Wake-up pattern 2 mask bits 31:0 Wake-up pattern 2 mask bits 63:32 Wake-up pattern 2 mask bits 95:64 Wake-up pattern 2 mask bits 127:96
49/82
Registers and descriptors description Table 8.
Bit #
STE10/100A
Control/status register description (continued)
Name Description CRC16 of pattern 2 Default Reserved RW type Wake-up pattern 2 offset
0024h 0028h 002ch 0030h 0034h 0038h 003ch 0040h 0044h 0048h 004ch 0050h 0054h 0058h 005ch 0060h
Wake-up pattern 3 mask bits 31:0 Wake-up pattern 3 mask bits 63:32 Wake-up pattern 3 mask bits 95:64 Wake-up pattern 3 mask bits 127:96 CRC16 of pattern 3 Reserved Wake-up pattern 3 offset
Wake-up pattern 4 mask bits 31:0 Wake-up pattern 4 mask bits 63:32 Wake-up pattern 4 mask bits 95:64 Wake-up pattern 4 mask bits 127:96 CRC16 of pattern 4
Wake-up pattern 5 mask bits 31:0 Wake-up pattern 5 mask bits 63:32
Offset value is from 0-255 (8-bit width). To load the whole wake-up frame filtering information, consecutive 25 long words write operation to CSR14 should be done.
CSR15 (offset = 78h), WTMR - Watchdog timer 31~6
bs O
let o
Pr e
5 4
du o
---
(s) ct
CRC16 of pattern 5
so Ob -
Wake-up pattern 5 mask bits 95:64
te le
ro P
Reserved
uc d
s) t(
Wake-up pattern 4 offset
Wake-up pattern 5 mask bits 127:96 Reserved Wake-up pattern 5 offset
Reserved Receive watchdog release. The time (in bittimes) from sensing dropped carrier to releasing watchdog timer. 0: 24 bit-times 1: 48 bit-times Receive watchdog disable 0: If the received packet`s length exceeds 2560 bytes, the watchdog timer will expire. 1: disable the receive watchdog. Reserved
RWR
RWD
3
---
50/82
STE10/100A Table 8.
Bit #
Registers and descriptors description Control/status register description (continued)
Name Description Jabber clock 0: cut off transmission after 2.6 ms (100Mbps) or 26 ms (10Mbps). 1: cut off transmission after 2560 byte-time. Non-Jabber 0: if jabber expires, re-enable transmit function after 42 ms (100Mbps) or 420ms (10Mbps). 1: immediately re-enable the transmit function after jabber expires. Jabber disable 1: disable transmit jabber function Default RW type
2
JCLK
1
NJ
0
JBD
CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2) Transmit early interrupt status Transmit early interrupt status is set to 1 when TEIE (bit 31 of CSR17 set) is enabled and the transmitted packet is moved from descriptors to the TX-FIFO buffer. This bit is cleared by writing a 1. Receive early interrupt status. Receive early interrupt status is set to 1 when REIE (CSR17 bit 30) is enabled and the received packet has filled up its first receive descriptor. This bit is cleared by writing a 1.
31
TEIS
0
30
REIS
29 28 27 26
XIS TDIS --PFR
Transceiver (XCVR) interrupt status. Formed by the logical OR of XR8 bits 6~0. Transmit deferred interrupt status. Reserved
bs O
let o
25~ 23
ro P e
du
PAUSE frame received interrupt status. 1: indicates receipt of a PAUSE frame while the PAUSE function is enabled.
(s) ct
so Ob -
eP let
od r
0 1 0
uc
s) t(
RO/LH*
RO/LH*
RO/LH* RO/LH*
0
RO/LH*
BET
Bus error type. This field is valid only when FBE (CSR5 bit 13, fatal bus error) is set. There is no interrupt generated by this field. 000: parity error, 001: master abort, 010: target abort. 011, 1xx: reserved
000
RO
51/82
Registers and descriptors description Table 8.
Bit #
STE10/100A
Control/status register description (continued)
Name Description Transmit state. Reports the current transmission state only, no interrupt will be generated. 000: stop 001: read descriptor 010: transmitting 011: FIFO fill, read the data from memory and put into FIFO 100: reserved 101: reserved 110: suspended, unavailable transmit descriptor or FIFO overflow 111: write descriptor Receive state. Reports current receive state only, no interrupt will be generated. 000: stop 001: read descriptor 010: check this packet and pre-fetch next descriptor 011: wait for receiving data 100: suspended 101: write descriptor 110: flush the current FIFO 111: FIFO drain, move data from receiving FIFO into memory Added normal interrupt status summary. 1: whenever any of the added normal interrupts occur. Added abnormal interrupt status summary. 1: whenever any of the added abnormal interrupts occur. Default RW type
22~ 20
TS
000
RO
19~17
RS
16
ANISS
15
AAISS
14~0
O
bs
let o
LH* = High Latching and cleared by writing 1
CSR17 (offset = 84h), ACSR7- Assistant CSR7 (Interrupt enable register 2) 31 30 29 28 27 26 25~17 TEIE REIE XIE TDIE --PFRIE --Transmit early interrupt enable Receive early interrupt enable Transceiver (XCVR) interrupt enable Transmit deferred interrupt enable Reserved PAUSE frame received interrupt enable Reserved 0 R/W 0 0 0 0 R/W R/W R/W R/W
Pr e
du o
These bits are the same as the status register of CSR5, and are accessible through either CSR5 or CSR16.
(s) ct
so Ob -
te le
ro P
uc d
000
s) t(
RO
0
RO/LH*
1
RO/LH*
52/82
STE10/100A Table 8.
Bit #
Registers and descriptors description Control/status register description (continued)
Name Description Added normal interrupt summary enable. 1: adds the interrupts of bits 30 and 31 of ACSR7 (CSR17) to the normal interrupt summary (bit 16 of CSR5). Added abnormal interrupt summary enable. 1: adds the interrupt of bits 27, 28, and 29 of ACSR7 (CSR17) to the abnormal interrupt summary (bit 16 of CSR5). These bits are the same as the interrupt enable register of CSR7, and are accessible through either CSR7 or CSR16. Default RW type
16
ANISE
0
R/W
15
AAIE
0
R/W
14~0
CSR18 (offset = 88h), CR - Command register bit31 to bit16 automatically recall from EEPROM D3cold power state wake up support. If this bit is reset then bit 31 of PMR0 will be reset to `0'. If this bit is asserted and an auxiliary power source is detected then bit 31 of PMR0 will be set to `1'. Aux. current load. These three bits report the maximum 3.3Vaux current requirements for STE10/100A chip. If bit 31 of PMR0 is `1', the default value is 111b, which means the STE10/100A need 375 mA to support remote wake-up in D3cold power state. Otherwise, the default value is 000b, which means the STE10/100A does not support remote wake-up from D3cold power state. Reserved 0 from EEPROM
31
D3CS
30-28
AUXCL
27-24
---
bs O
let o
Pr e
23
This bit is used to control the LED mode selection. If this bit is reset, mode 1 (3 LEDs) is selected; the LEDs definition is: - 100/10 speed - Link/activity 4LEDmod - Full duplex/collision e_on If this bit is set, mode 2 (4 LEDs) is selected; the LEDs definition is: - 100 link - 10 link - Activity - Full duplex/collision
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
R/W R/W
000b from EEPROM
0 from EEPROM
R/W
22, 21
RFS
Receive FIFO size control 11: 1K bytes 10: 2K bytes 01,00: reserved Reserved
10 from EEPROM
R/W
20
---
53/82
Registers and descriptors description Table 8.
Bit #
STE10/100A
Control/status register description (continued)
Name Description Default RW type
19
PM
Power management. Enables the STE10/100A power management abilities. When this bit is set into "0" the STE10/100A will set the Cap_Ptr register to zero, indicating no PCI compliant X power management capabilities. The value of from EEPROM this bit will be mapped to NC (CR1 bit 20). In PCI power management mode, the wake up frames include "Magic Packet", "Unicast", and "Muliticast". Wake on LAN mode enable. When this bit is set to `1', then the STE10/100A enters wake on LAN mode and enters the sleep state. Once the STE10/100A enters the sleep state, it X remains there until: the wake up event occurs, from EEPROM the WOL bit is cleared, or a reset (software or hardware) happens. In wake on LAN mode the wake-up frame is "Magic Packet" only. Reserved Reset wake-up pattern data register pointer Disable or enable the PAUSE function for flow control. The default value of PAUSE is determined by the result of auto-negotiation. The driver software can overwrite this bit to enable or disable it after the auto-negotiation has completed. 0: PAUSE function is disabled. 1: PAUSE function is enabled
RO
18
WOL
R/W
17~7 6
--RWP
5
PAUSE
4
RTE
bs O
let o
3~2
Pr e
1 0
du o
Receive threshold enable. 1: the receive FIFO threshold is enabled. 0: disable the receive FIFO threshold selection in DRT (bits 3~2), and the receive threshold is set to the default 64 bytes. Drain receive threshold 00: 32 bytes (8 DW) 01: 64 bytes (16 DW) 10: store-and -forward 11: reserved Software interrupt. 1: enable automatically transmit-underrun recovery.
(s) ct
Ob -
so
eP let
ro
uc d
0
s) t(
R/W R/W
Depends on the result of autonegotiation
0
R/W
DRT
01
R/W
SINT ATUR
0 0
R/W R/W
54/82
STE10/100A Table 8.
Bit #
Registers and descriptors description Control/status register description (continued)
Name Description Default RW type
CSR19 (offset = 8ch), PCIC - PCI bus performance counter The number of PCI clocks from read request asserted to access completed. This PCI clock CLKCNT count is accumulated for all the read command cycles from the last CSR19 read to the current CSR19 read. --Reserved The number of double words accessed by the last bus master. This double word count is accumulated for all bus master data transactions from the last CSR19 read to the current CSR19 read.
31~16
0
RO*
15~8
7~0
DWCNT
0
RO*
RO* = Read only and cleared by reading.
CSR20 (offset = 90h), PMCSR - Power management command and status (The same register value mapping to CR49-PMR1) 31~16 --Reserved PME_Status. This bit is set whenever the STE10/100A detects a wake-up event, regardless of the state of the PME-En bit. Writing a "1" to this bit will clear it, causing the STE10/100A to deassert PME# (if so enabled). Writing a "0" has no effect.
15
PMES
14,13
DSCAL
Data_Scale. Indicates the scaling factor to be used when interpreting the value of the data register. This field is required for any function that implements the data register. The STE10/100A does not support data register and Data_Scale. Data_Select. This four bit field is used to select which data is to be reported through the data register and Data_Scale field. This field is required for any function that implements the data register. The STE10/100A does not support Data_select.
12~9
bs O
let o
ro P e
8 ---
DSEL
du
(s) ct
so Ob -
te le
ro P
uc d
0
s) t(
RO
00b
RO
0000b
RO
PME_En. When set, enables the STE10/100A to PME_En assert PME#. When cleared, disables the PME# assertion. Reserved
0 0 0 00b
RO RO
7~2
55/82
Registers and descriptors description Table 8.
Bit #
STE10/100A
Control/status register description (continued)
Name Description PowerState, this two-bit field is used both to determine the current power state of the STE10/100A and to set the STE10/100A into a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported state to this field, the write operation will complete normally on the bus, but the data is discarded and no state change occurs. Default RW type
1,0
PWRS
00b
RO
CSR23 (offset = 9ch), TXBR - Transmit burst count / time-out 31~21 --Reserved Transmit burst count Specifies the number of consecutive successful transmit burst writes to complete before the transmit completed interrupt will be generated. Reserved 1
20~16
TBCNT
15~12
---
11~0
TTO
Transmit time-out = (deferred time + back-off time). When TDIE (ACSR7 bit 28) is set, the timer is decreased in increments of 2.56us (@100M) or 25.6us (@10M). If the timer expires before another packet transmit begins, then the TDIE interrupt will be generated.
CSR24 (offset = a0h), FROM - Flash ROM (also the boot ROM) port This bit is only valid when 4 LEDmode_on (CSR18 bit 23) is set. In this case, when bra16_on bra16_on is set, pin 87 functions as brA16; otherwise it functions as LED pin fd/col.
31
30~28
O
bs
let o
Pr e
27 26 25
du o
-----
(s) ct
so Ob -
te le
ro P
uc d
0 1 0
s) t(
R/W
R/W
1
R/W
Reserved 0 0 R/W R/W
REN
Read enable. Clear if read data is ready in DATA, bit7-0 of FROM. Write enable. Cleared if write completed. Reserved Flash ROM address Read/Write data of flash ROM
WEN
24~8 7~0
ADDR DATA
0 0
R/W R/W
56/82
STE10/100A Table 8.
Bit #
Registers and descriptors description Control/status register description (continued)
Name Description Default RW type
CSR25 (offset = a4h), PAR0 - Physical address register 0 automatically recalled from EEPROM 31~24 23~16 15~8 7~0 PAB3 PAB2 PAB1 PAB0 Physical address byte 3 Physical address byte 2 Physical address byte 1 Physical address byte 0 From EEPROM From EEPROM From EEPROM From EEPROM R/W R/W R/W R/W
CSR26 (offset = a8h), PAR1 - Physical address register 1 automatically recalled from EEPROM 31~24 23~16 15~8 7~0 ----PAB5 PAB4 Reserved Reserved Physical address byte 5 Physical address byte 4 From EEPROM
For example, physical address = 00-00-e8-11-22-33 - PAR0= 11 e8 00 00 - PAR1= XX XX 33 22 - PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bits 19-17=000).
CSR27 (offset = ach), MAR0 - Multicast address register 0 31~24 23~16 15~8 7~0 MAB3 MAB2 MAB1 MAB0
Multicast address byte 3 (hash table 31:24) Multicast address byte 2 (hash table 23:16) Multicast address byte 1 (hash table 15:8) Multicast address byte 0 (hash table 7:0)
CSR28 (offset = b0h), MAR1 - Multicast address register 1 31~24 23~16 15~8
bs O
let o
7~0
od Pr e
MAB6 MAB5 MAB4
MAB7
ct u
(s)
Ob -
so
te le
ro P
From EEPROM
uc d
00h 00h 00h 00h
s) t(
R/W R/W
R/W R/W R/W R/W
Multicast address byte 7 (hash table 63:56) Multicast address byte 6 (hash table 55:48) Multicast address byte 5 (hash table 47:40) Multicast address byte 4 (hash table 39:32)
00h 00h 00h 00h
R/W R/W R/W R/W
MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped(CSR5 bit19-17=000)
57/82
Registers and descriptors description
STE10/100A
4.3
Transceiver(XCVR) registers
There are 11 16-bit registers supporting the transceiver portion of STE10/100A, including 7 basic registers defined according to clause 22 "Reconciliation Sublayer and Media Independent Interface" and clause 28 "Physical Layer link signaling for 10 Mb/s and 100 Mb/s auto-negotiation on twisted pair" of the IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status.
Note:
Since only double word access is supported for register R/W in the STE10/100A, the higher word (bit 31~16) of the XCVR registers (XR0~XR10) should be ignored.
Table 9. Transceiver registers list
Reg. index XR0 XR1 XR2 XR3 XR4 XR5 XR6 XR7 XR8 XR9 XR10 Name XCR XSR PID1 PID2 ANA ANLPA ANE XMC XCIIS XIE Register descriptions XCVR control register XCVR status register PHY identifier 1 PHY identifier 2
Offset from base address of CSR b4h b8h bch c0h c4h c8h cch d0h d4h d8h dch
Auto-negotiation advertisement register
Auto-negotiation link partner ability register Auto-negotiation expansion register XCVR mode control register
100CTR
bs O
let o
Pr e
du o
(s) ct
so Ob -
XCVR configuration information and interrupt status register XCVR interrupt enable register
te le
ro P
uc d
s) t(
100BASE-TX PHY control/status register
58/82
STE10/100A
Registers and descriptors description
Table 10.
Bit #
Transceiver registers description
Name Description Default RW type
XR0(offset = b4h) - XCR, XCVR control register. The default value is chosen as listed below. Transceiver reset control. 1: reset transceiver. This bit will be cleared by STE10/100A after transceiver reset has completed. Transceiver loop-back mode select. 1: transceiver loop-back mode is selected. OM (CSR6 bits 11,10) of must contain 00. Network speed select. This bit will be ignored if Auto-negotiation is enabled (ANEN, XR0 bit 12). 1:100Mbps is selected. 0:10Mbps is selected. Auto-negotiation ability control. 1: Auto-negotiation function is enabled. 0: Auto-negotiation is disabled. Power down mode control. 1: transceiver power-down mode is selected. In this mode, the STE10/100A transceivers are turned off. reserved
15
XRST
0
R/W
14
XLBEN
0
R/W
13
SPSEL
1
R/W
12
ANEN
1
11
PDEN
10
---
9
RSAN
Re-star t auto-negotiation process control. 1: Auto-negotiation process will be restarted. This bit will be cleared by STE10/100A after the Auto-negotiation has restarted. Full/half duplex mode select. 1: full duplex mode is selected. This bit will be ignored if auto-negotiation is enabled (ANEN, XR0 bit 12). Collision test control. 1: collision test is enabled. Reserved
8
DPSEL
6~0
O
bs
let o
R/W = Read/Write able. RO = Read only.
XR1(offset = b8h) - XSR, XCVR status register. All the bits of this register are read only. 15 T4 100BASE-T4 ability. Always 0, since STE10/100A has no T4 ability. 100BASE-TX full duplex ability. Always 1, since STE10/100A has 100BASE-TX full duplex ability. 100BASE-TX half duplex ability. Always 1, since STE10/100A has 100BASE-TX half duplex ability. 0 RO
ro P e
--14
7
COLEN
uc d
(s) t
so Ob -
eP let
ro
uc d
0 0 0
s) t(
R/W R/W RO
R/W
0
R/W
0 0
R/W RO
TXFD
1
RO
13
TXHD
1
RO
59/82
Registers and descriptors description Table 10.
Bit # 12
STE10/100A
Transceiver registers description (continued)
Name 10FD Description 10BASE-T full duplex ability. Always 1, since STE10/100A has 10Base-T full duplex ability. 10BASE-T half duplex ability. Always 1, since STE10/100A has 10Base-T half duplex ability. Reserved Auto-negotiation completed. 0: Auto-negotiation process incomplete. 1: Auto-negotiation process complete. Result of remote fault detection. 0: no remote fault condition detected. 1: remote fault condition detected. Auto-negotiation ability. Always 1, since STE10/100A has autonegotiation ability. Link status. 0: a link failure condition occurred. Readin clears this bit. 1: valid link established. Jabber detection. 1: jabber condition detected (10Base-T only). Extended register support. Always 1, since STE10/100A supports extended register Default 1 RW type RO
11 10~6 5
10HD --ANC
1
0
RO
RO
0
RO
4
RF
0
RO/LH*
3
AN
2
LINK
1
JAB
0
EXT
LL* = Latching Low and clear by read. LH* = Latching High and clear by read.
XR2(offset = bch) - PID1, PHY identifier 1
15~0
bs O
let o
XR3(offset = c0h) - PID2, PHY identifier 2 15~10 PHYID2 Par t two of PHY identifier. Assigned to the 19th to 24th bits of the organizationally unique identifier (OUI). Model number of STE10/100A. 6-bit manufacturer's model number. Revision number of STE10/100A. 4-bits manufacturer's revision number. 0 0 00b RO
Pr e
PHYID1
du o
Par t one of PHY identifier. Assigned to the 3rd to 18th bits of the Organizationally Unique Identifier (The ST OUI is 0080E1 hex).
(s) ct
so Ob -
te le
ro P
uc d
0 0 1
1
s) t(
RO RO/LL* RO/LH*
RO
1C04h
RO
9~4 3~0
MODEL REV
0 0 01b 0000b
RO RO
60/82
STE10/100A Table 10.
Bit #
Registers and descriptors description Transceiver registers description (continued)
Name Description Default RW type
XR4(offset = c4h) - ANA, Auto-negotiation advertisement 15 14 13 12,11 10 NXTPG --RF --FC Next page ability. Always 0; STE10/100A does not provide next page ability. reserved Remote fault function. 1: remote fault function present Reserved Flow control function ability. 1: supports PAUSE operation of flow control for full duplex link. 100BASE-T4 ability. Always 0; STE10/100A does not provide 100BASE-T4 ability. 100BASE-TX full duplex ability. 1: 100Base-TX full duplex ability supported 100BASE-TX half duplex ability. 1: 100Base-TX ability supported. 10BASE-T full duplex ability. 1: 10Base-T full duplex ability supported. 10BASE-T half duplex ability. 1: 10Base-T ability supported. 1 R/W 0 R/W 0 RO
9
T4
0
8 7 6 5 4~0
TXF TXH 10F 10H SF
Select field. Default 00001=IEEE 802.3
XR5(offset = c8h) - ANLP, Auto-negotiation link partner ability Link partner next page ability. 0: link partner without next page ability. 1: link partner with next page ability.
15
LPNP
O
bs
let o
Pr e
14 13
LPACK
du o
(s) ct
so Ob -
te le
ro P
uc d
1 1 1 1
s) t(
RO R/W R/W R/W R/W RO
00001
0
RO
Received link partner acknowledge. 0: link code word not yet received. 1: link partner successfully received STE10/100A's link code word.
0
RO
LPRF ---
Link partner's remote fault status. 0: no remote fault detected. 1: remote fault detected. Reserved Link partner's flow control ability. 0: link partner without PAUSE function ability. 1, link partner with PAUSE function ability for full duplex link.
0 0
RO RO
12,11
10
LPFC
0
RO
61/82
Registers and descriptors description Table 10.
Bit #
STE10/100A
Transceiver registers description (continued)
Name Description Link partner's 100BASE-T4 ability. 0: link partner without 100BASE-T4 ability. 1: link partner with 100BASE-T4 ability. Link partner's 100BASE-TX full duplex ability. 0: link partner without 100BASE-TX full duplex ability. 1: link partner with 100BASE-TX full duplex ability. Link partner's 100BASE-TX half duplex ability. 0: link partner without 100BASE-TX. 1: link partner with 100BASE-TX ability. Link partner's 10BASE-T full duplex ability. 0: link partner without 10BASE-T full duplex ability. 1: link partner with 10BASE-T full duplex ability. Link partner's 10BASE-T half duplex ability. 0: link partner without 10BASE-T ability. 1: link partner with 10BASE-T ability. Link partner select field. Standard IEEE 802.3 = 00001 Default RW type
9
LPT4
0
RO
8
L PTXF
0
RO
0
RO
7
L PTXH
0
RO
6
LP10F
0
5
LP10H
4~0
L PSF
XR6(offset = cch) - ANE, auto-negotiation expansion 15~5 4 --PDF reserved
Parallel detection fault. 0: no fault detected. 1: a fault detected via parallel detection function. Link partner's next page ability. 0: link partner without next page ability. 1: link partner with next page ability. STE10/100A's next page ability. Always 0; STE10/100A does not support next page ability. Page received. 0: no new page has been received. 1: a new page has been received. Link partner auto-negotiation ability. 0: link partner has no auto-negotiation ability. 1: link partner has auto-negotiation ability.
3
LPNP
O
bs
let o
ro P e
2 1 0
du
(s) ct
so Ob -
eP let
od r
0
uc
s) t(
RO RO
0 0
RO RO/LH*
0
RO
NP
0
RO
PR
0
RO/LH*
LPAN
0
RO
LH = High Latching and cleared by reading.
62/82
STE10/100A Table 10.
Bit #
Registers and descriptors description Transceiver registers description (continued)
Name Description Default RW type
XR7(offset = d0h) - XMC, XCVR mode control 15~12 --Reserved Long distance mode of 10BASE-T. 0: normal squelch level. 1: reduced 10Base-T squelch level for extended cable length. Reserved 0 RO
11
LD
0
R/W
10~0
---
0
RO
XR8(offset = d4h) - XCIIS, XCVR configuration information and interrupt status 15~10 9 ---SPEED Reserved Speed configuration setting. 0: the speed is 10Mb/s. 1: the speed is 100Mb/s. 0 1 RO
8
Duplex configuration setting. DUPLEX 0: the duplex mode is half. 1: the duplex mode is full. PAUSE function configuration setting for flow control. 0: PAUSE function is disabled. 1: PAUSE function is enabled Auto-negotiation completed interrupt. 0: Auto-negotiation has not completed yet. 1: Auto-negotiation has completed. Remote fault detected interrupt. 0: there is no remote fault detected. 1: remote fault is detected.
7
PAUSE
6
ANC
5
RFD
bs O
let o
Pr e
4 3 2
du o
LS
Link fail interrupt. 0: link test status is up. 1: link is down.
(s) ct
so Ob -
te le
ro P
uc d
0 0 0
s) t(
RO RO RO
RO/LH*
0
RO/LH*
0
RO/LH*
ANAR
Auto-negotiation acknowledge received interrupt. 0: there is no link code word received. 1: link code word is receive from link partner. Parallel detection fault interrupt. 0: there is no parallel detection fault. 1: parallel detection is fault. Auto-negotiation page received interrupt. 0: there is no auto-negotiation page received. 1: auto-negotiation page is received.
0
RO/LH*
PDF
0
RO/LH*
1
ANPR
0
RO/LH*
63/82
Registers and descriptors descr |
