PSD3XX ZPSD3XX ZPSD3XXV PSD3XXR ZPSD3XXR ZPSD3XXRV
Low Cost Field Programmable Microcontroller Peripherals
FEATUR ES SUMMARY s Single Supply Voltage: 5 V10% for PSD3xx, ZPSD3xx, PSD3xxR, ZPSD3xxR 2.7 to 5.5 V for ZPSD3xxV, ZPSD3xxRV
s s s s s s
Figure 1. Packages
Up to 1 Mbit of EPROM Up to 16 Kbit SRAM Input Latches Programmable I/O ports Page Logic Programmable Security
PLDCC44 (J)
CLDCC44 (L)
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PQFP44 (M) TQFP44 (U)
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January 2002
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PSD3XX Family
PSD3XX ZPSD3XX ZPSD3XXV PSD3XXR ZPSD3XXR ZPSD3XXRV Low Cost Microcontroller Peripherals Table of Contents
1 2 3 4 5 6 7 8 9 10 Introduction . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .1 Notation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .2 Key Features . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...4 PSD3XX Family Feature Summary . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....5 Partial Listing of Microcontrollers Supported . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....6 Applications . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....6 ZPSD Background . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....6 7.1 Integrated Power ManagementTM Operation . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....7 Operating Modes (MCU Configurations) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....10 Programmable Address Decoder (PAD). . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....12 I/O Port Functions . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....15 10.1 CSIOPORT Registers . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..15 10.2 Port A (PA0-PA7). . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....16 10.2.1 Port A (PA0-PA7) in Multiplexed Address/Data Mode. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....16 10.2.2 Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..17 10.3 Port B (PB0-PB7). . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....18 10.3.1 Port B (PA0-PA7) in Multiplexed Address/Data Mode. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....18 10.3.2 Port B (PA0-PA7) in Non-Multiplexed Address/Data Mode . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..19 10.4 Port C (PC0-PC2) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...20 10.5 ALE/AS Input Pin . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....20 PSD Memory . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .21 11.1 EPROM. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....21 11.2 SRAM (Optional). . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....21 11.3 Page Register (Optional) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..21 11.4 Programming and Erasure. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....21 Control Signals . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...22 12.1 ALE or AS . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....22 12.2 WR or R/W. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....22 12.3 RD/E/DS (DS option not available on 3X1 devices) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .22 12.4 PSEN or PSEN . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..22 12.5 A19/CSI . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...23 12.6 Reset Input . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...24 Program/Data Space and the 8031 . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..26 Systems Applications. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....27 Security Mode . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....30 Power Management. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .30 16.1 CSI Input. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..30 16.2 CMiser Bit . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....30 16.3 Turbo Bit (ZPSD Only). . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .31 16.4 Number of Product Terms in the PAD Logic. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...31 16.5 Composite Frequency of the Input Signals to the PAD Logic . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ..32 16.6 Loading on I/O Pins . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....33 Calculating Power . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....34
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13 14 15 16
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PSD3XX Family
PSD3XX ZPSD3XX ZPSD3XXV PSD3XXR ZPSD3XXR ZPSD3XXRV Low Cost Microcontroller Peripherals Table of Contents (cont.)
18 Specifications . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .37 18.1 Absolute Maximum Ratings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...37 18.2 Operating Range . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....37 18.3 Recommended Operating Conditions. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...37 18.4 Pin Capacitance. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .37 18.5 AC/DC Characteristics PSD3XX/ZPSD3XX (All 5 V devices) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...38 18.6 AC/DC Characteristics PSD3XXV (3 V devices only). . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .39 18.7 Timing Parameters PSD3XX/ZPSD3XX (All 5 V devices). . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....40 18.8 Timing Parameters ZPSD3XXV (3 V devices only) . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....42 18.9 Timing Diagrams for PSD3XX Parts. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....44 18.10 AC Testing . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....65 Pin Assignments . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .66 Package Information . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....67 Package Drawings . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...68 PSD3XX Product Ordering Information . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .72 22.1 PSD3XX Selector Guide. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...72 22.2 Part Number Construction . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .....73 22.3 Ordering Information. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ....73 Data Sheet Revision History . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . ...80
19 20 21 22
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Programmable Peripheral
PSD3XX Family
Field-Programmable Microcontroller Peripheral
1.0 Introduction
The low cost PSD3XX family integrates high-performance and user-configurable blocks of EPROM, programmable logic, and optional SRAM into one part. The PSD3XX products also provide a powerful microcontroller interface that eliminates the need for external "glue logic". The part's integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller. The major functional blocks of the PSD3XX include: · Two programmable logic arrays · 256Kb to 1 Mb of EPROM · Optional 16 Kb SRAM · Input latches · Programmable I/O ports · Page logic · Programmable security.
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The PSD3XX family architecture (Figure 1) can efficiently interface with, and enhance, almost any 8- or 16-bit microcontroller system. This solution provides microcontrollers the following: · Chip-select logic, control logic, and latched address signals that are otherwise implemented discretely · Port expansion (reconstructs lost microcontroller I/O) · Expanded microcontroller address space (up to 16 times) · An EPROM (with security) and optional SRAM · Compatible with 8031-type architectures that use separate Program and Data Space · Interface to shared external resources.
1
PSD3XX Family
1.0 Introduction
(cont.)
The PSD3XX I/O ports can be used for: · Standard I/O ports · Programmable chip select outputs · Address inputs · Demultiplexed address outputs · A data bus port for non-multiplexed MCU applications · A data bus "repeater" port that shares and arbitrates the local MCU data bus with external devices. Implementing your design has never been easier than with PSDsoft -- ST's software development suite. Using PSDsoft, you can do the following: · Configure your PSD3XX to work with virtually any microcontroller · Specify what you want implemented in the programmable logic using a high-level Hardware Description Language (HDL) · Simulate your design · Download your design to the part using a programmer.
2. Notation
For a complete product comparison, refer to Table 1.
PSD3XX references the standard version of the PSD3XX family, which are ideal for general-purpose embedded control applications.
PSD3XXR SRAM-less version of the PSD3XX. If you don't require the 16 Kb SRAM or need a larger external SRAM, go with this part to save cost. ZPSD3XX has improved technology that helps reduce current consumption using the Turbo bit. Excellent if you require a 5 V version of the PSD3XX that uses less power. ZPSD3XXR SRAM-less version of the ZPSD3XX.
ZPSD3XXV 2.7 V to 5.5 V operation, ideal for very low-power and low-voltage applications. ZPSD3XXRV SRAM-less version of the ZPSD3XXV. Throughout this data sheet, references are made to the PSD3XX. In most cases, these references also cover the entire family. Exceptions will be noted. References, such as "3X1 only" cover all parts that have a 301 or 311 in the part number. Use the following table to determine what references cover which product versions:
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PSD3XX
X X X
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Reference
PSD3XXR
X X X
ZPSD3XX
X
ZPSD3XXR
X
ZPSD3XXV
X
ZPSD3XXRV
X
PSD3XX PSD PSD3XX only Non-ZPSD ZPSD only ZPSD3XX Non-V versions V versions only V suffix ZPSD3XXV only SRAM-less Non-R
X X X X
X X
X
X
X X X X
X
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PSD3XX Family
Figure 1. PSD3XX Family Architecture
L A T C H A11A15 A8A10 A19/CSI ALE/AS RD WR ALE/AS RESET
OPTIONAL PAGE LOGIC* P3P0 A16A18 PROG. PORT EXP. PC0 PC2
CSIOPORT A19/CSI PAD A ALE/AS RD 13 P.T. WR RESET
LOGIC IN
AD8AD15
PAD B CS8 CS10
PORT C
27 P.T.
AD0AD7
L A T C H
ES7 ES6 ES5 ES4 ES3 ES2 ES1 ES0 16/8 MUX D8D15 EPROM 256Kb TO 1Mb
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ALE/AS
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D0D7
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OPTIONAL SRAM 16K BIT
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CS0 CS7
PROG. PORT EXP. PB0 PB7
PORT B
CSIOPORT
**
A0A7 AD0AD7/D0D7
TRACK MODE SELECTS
PROG. PORT EXP. PA0 PA7
PORT A
RD/E/DS WR/R/W BHE/PSEN RESET A19/CSI PROG. CONTROL SIGNALS
PROG. CHIP CONFIGURATION X8, X16 MUX or NONMUX BUSSES SECURITY MODE
**Not available for 3X1 devices. **SRAM not available on "R" versions.
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PSD3XX Family
3.0 Key Features
t Single-chip programmable peripheral for microcontroller-based applications t 256K to 1 Mbit of UV EPROM with the following features: · Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16 · Divided into eight equally-sized mappable blocks for optimized address mapping · As fast as 70 ns access time, which includes address decoding t Optional 16 Kbit SRAM is configurable as 2K x 8 or 1K x 16. The access time can be
as quick as 70 ns, including address decoding.
t 19 I/O pins that can be individually configured for : · Microcontroller I/O port expansion · Programmable Address decoder (PAD) I/O · Latched address output · Open-drain or CMOS output t Two Programmable Arrays (PAD A and PAD B) replace your PLD or decoder, and have
the following features: · Up to 18 Inputs and 24 outputs · 40 Product terms (13 for PAD A and 27 for PAD B) · Ability to decode up to 1 MB of address without paging
t Microcontroller logic that eliminates the need for external "glue logic" has the following
features: · Ability to interface to multiplexed and non-multiplexed buses · Built-in address latches for multiplexed address/data bus · ALE and Reset polarity are programmable (Reset polarity not programmable on V-versions) · Multiple configurations are possible for interface to many different microcontrollers
t Optional built-in page logic expands the MCU address space by up to 16 times t Programmable power management with standby current as low as 1A for low-voltage
version · CMiser bit -- programmable option to reduce AC power consumption in memory · Turbo Bit (ZPSD only)--programmable bit to reduce AC and DC power consumption in the PADs.
t Track Mode that allows other microcontrollers or host processors to share access to the
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local data bus
t Built-in security locks the device and PAD decoding configuration t Wide Operating Voltage Range · V-versions: 2.7 to 5.5 volts · Others: 4.5 to 5.5 volts t Available in a variety of packaging (44-pin PLDCC, CLDCC, TQFP, and PQFP) t Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC.
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PSD3XX Family
4.0 PSD3XX Family Feature Summary
Use the following table to determine which PSD product will fit your needs. Refer back to this page whenever there is confusion as to which part has what features.
Part
PSD301R PSD311R PSD302R PSD312R PSD303R PSD313R ZPSD301R ZPSD311R ZPSD302R ZPSD312R ZPSD303R ZPSD313R PSD301 PSD311 PSD302 PSD312 PSD303 PSD313 ZPSD301 ZPSD311 ZPSD302 ZPSD312 ZPSD303 ZPSD313
# PLD Inputs
14 14 18 18 18 18 14 14 18 18 18 18 14 14 18 18 18 18 14 14 18 18 18 18
EPROM Size
256 Kb 256 Kb 512 Kb 512 Kb 1 Mb 1 Mb 256 Kb 256 Kb 512 Kb 512 Kb 1 Mb 1 Mb 256 Kb 256 Kb 512 Kb 512 Kb 1 Mb 1 Mb 256 Kb 256 Kb 512 Kb 512 Kb 1 Mb 1 Mb
SRAM Size
Page Reg
Voltage
5V 5V
Turbo Bit
Bus Width
x8 or x16 x8 x8 or x16 x8 x8 or x16 x8
Typical Standby Current
50 A 50 A 50 A 50 A 50 A 50 A 10 A 10 A 10 A 10 A 10 A 10 A 50 A 50 A 50 A 50 A 50 A 50 A 10 A 10 A 10 A 10 A 10 A 10 A 1 A 1 A 1 A 1 A 1 A 1 A
X X X X
5V 5V 5V 5V 5V 5V X X X X X X
x8 or x16 x8 x8 or x16 x8
X X X X 16 Kb 16 Kb 16 Kb 16 Kb 16 Kb 16 Kb X X
5V 5V 5V 5V 5V 5V
ZPSD301V1 ZPSD311V1
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ZPSD302V1 ZPSD312V1 ZPSD303V1 ZPSD313V1
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14 14 18 18 18 18
so Ob 256 Kb 256 Kb 512 Kb 512 Kb 1 Mb 1 Mb
16 Kb 16 Kb 16 Kb 16 Kb
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X X X X X X
5V 5V
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x8 or x16 x8
x8 or x16 x8 x8 or x16 x8
5V 5V 5V 5V 5V 5V 5V 5V
x8 or x16 x8 x8 or x16 x8 x8 or x16 x8 x8 or x16 x8 x8 or x16 x8 x8 or x16 x8 x8 or x16 x8
16 Kb 16 Kb
16 Kb 16 Kb 16 Kb 16 Kb 16 Kb 16 Kb X X X X
2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
NOTES: 1. Low power versions of the ZPSD3XX (ZPSD3XXV) can only accept an active-low level Reset input.
5
PSD3XX Family
5.0 Partial Listing of Microcontrollers Supported
t Motorola family: 68HC11, 68HC16, M68000/10/20, M68008, M683XX, 68HC05C0 t Intel family: 80C31, 80C51, 80C196/198, 80C186/188 t Philips family: 80C31 and 80C51 based MCUs t Zilog: Z8, Z80, Z180 t National: HPC16000, HPC46400 t Echelon/Motorola/Toshiba: NEURON 3150TM Chip
6.0 Applications
t Telecommunications: · Cellular phone · Digital PBX · Digital speech · FAX · Digital Signal Processing (DSP) t Portable Industrial Equipment: · Industrial control · Measurement meters · Data recorders t Instrumentation t Medical Instrumentation: · Hearing aids · Monitoring equipment · Diagnostic tools
t Computers -- notebooks, portable PCs, and palm-top computers: · Peripheral control (fixed disks, laser printers, etc.) · Modem Interface · MCU peripheral interface
7.0 ZPSD Background
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Portable and battery-powered systems have recently become major embedded control application segments. As a result, the demand for electronic components having extremely low power consumption has increased dramatically. Recognizing this trend, ST developed a new lower power 3XX part, denoted ZPSD3XX. The Z stands for Zero-power because ZPSD products virtually eliminate the DC component of power consumption, reducing it to standby levels. Virtual elimination of the DC component is the basis for the words "Zero-power" in the ZPSD name. ZPSD products also minimize the AC power component when the chip is changing states. The result is a programmable microcontroller peripheral family that replaces discrete circuit components, while drawing less power.
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PSD3XX Family
7.0 ZPSD Background
(cont.)
Integrated Power Management TM Operation
Upon each address or logic input change to the ZPSD, the device powers up from low power standby for a short time. Then the ZPSD consumes only the necessary power to deliver new logic or memory data to its outputs as a response to the input change. After the new outputs are stable, the ZPSD latches them and automatically reverts back to standby mode. The ICC current flowing during standby mode and during DC operation is identical and is only a few microamperes. The ZPSD automatically reduces its DC current drain to these low levels and does not require controlling by the CSI (Chip Select Input). Disabling the CSI pin unconditionally forces the ZPSD to standby mode independent of other input transitions. The only significant power consumption in the ZPSD occurs during AC operation. The ZPSD contains the first architecture to apply zero power techniques to memory and logic blocks. Figure 2 compares ZPSD zero power operation to the operation of a discrete solution. A standard microcontroller (MCU) bus cycle usually starts with an ALE (or AS) pulse and the generation of an address. The ZPSD detects the address transition and powers up for a short time. The ZPSD then latches the outputs of the PAD, EPROM and SRAM to the new values. After finishing these operations, the ZPSD shuts off its internal power, entering standby mode. The time taken for the entire cycle is less than the ZPSD's "access time." The ZPSD will stay in standby mode while its inputs are not changing between bus cycles. In an alternate system implementation using discrete EPROM, SRAM, and other discrete components, the system will consume operating power during the entire bus cycle. This is because the chip select inputs on the memory devices are usually active throughout the entire cycle. The AC power consumption of the ZPSD may be calculated using the composite frequency of the MCU address and control signals, as well as any other logic inputs to the ZPSD.
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ALE ADDRESS EPROM ACCESS SRAM ACCESS DISCRETE EPROM, SRAM & LOGIC ICC ZPSD ZPSD
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EPROM ACCESS
ZPSD
TIME
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PSD3XX Family
Table 2. PSD3XX Pin Descriptions
Name
Type
Description
When the data bus is 8 bits: This pin is for 8031 or compatible MCUs that use PSEN to separate program space from data space. In this case, PSEN is used for reads from the EPROM. Note: if your MCU does not output a PSEN signal, pull up this pin to VCC. When the data bus is 16 bits: This pin is BHE. When low, D8-D15 are read from or written to. Note: in programming mode, this pin is pulsed between VPP and 0 V. The following control signals can be connected to this port, based on your MCU (and the way you configure the PSD in PSDsoft): 1. WR -- active-low write pulse. 2. R/W -- active-high read/active-low write input. Note: in programming mode, this pin must be tied to VPP. The following control signals can be connected to this port, based on your MCU (and the way you configure the PSD in PSDsoft): 1. RD -- active-low read input. 2. E -- E clock input. 3. DS--active-low data strobe input (3X2/3X3 devices only) The following control signals can be connected to this port: 1. CSI --Active-low chip select input. If your MCU supports a chip select output, and you want the PSD to save power when not selected, use this pin as a chip select input. 2. If you don't wish to use the CSI feature, you may use this pin as an additional input (logic or address) to the PAD. A19 can be latched (with ALE/AS), or a transparent logic input. PSD3XX/ZPSD3XX: This pin is user-programmable and can be configured to reset on a high- or low-level input. Reset must be applied for at least 100 ns.
BHE/ PSEN
I
WR/VPP or R/W/VPP
I
RD/E/DS
I
A19/CSI
I
Reset
I
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PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
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ZPSD3XXV: This pin is not configurable, and the chip will only reset on an active-low level input. Reset must be applied for at least 500 ns, and no operations may take place for an additional 500 ns minimum. (See Figure 8.) If you use an MCU that has a multiplexed bus: Connect ALE or AS to this pin. The polarity of this pin is configurable. The trailing edge of ALE/AS latches all multiplexed address inputs (and BHE where applicable). If you use an MCU that does not have a multiplexed bus: If your MCU uses ALE/AS, connect the signal to this pin. Otherwise, use this pin for a generic logic input to the PAD. (Non-3X1 devices only.) These pins make up Port A. These port pins are configurable, and can have the following functions: (see Figure 5A and 5B) 1. Track AD7-AD0. This feature repeats the MCU address and data bus on all Port A pins. 2. MCU I/O--in this mode, the direction of the pin is defined by its direction bit, which resides in the direction register. 3. Latched address output. 4. CMOS or open-drain output. 5. If your MCU is non-multiplexed: data bus input--connect your data bus (D0-7) to these pins. See Figure 3.
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ALE/AS
I/O
Legend: The Type column abbreviations are: I = input only; I/O = input/output; P = power.
8
PSD3XX Family
Table 2. PSD3XX Pin Descriptions
(cont.)
Name
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
Type
Description
These pins make up Port B. These port pins are configurable, and can have the following functions: (see Figure 6) 1. MCU I/O -- in this mode, the direction of the pin is defined by its direction bit, which resides in the direction register. 2. Chip select output -- each of PB0-3 has four product terms available per pin, while PB4-7 have 2 product terms each. See Figure 4. 3. CMOS or open-drain. 4. If your MCU is non-multiplexed, and the data bus width is 16 bits: data bus input--connect your data bus (D8-D15) to these pins. See Figure 3. These pins make up Port C. These port pins are configurable, and can have the following functions (see Figure 7): 1. PAD input--when configured as an input, a bit individually becomes an address or a logic input, depending on your PSDsoft design file. When declared as an address, the bit(s) can be latched with ALE/AS. 2. PAD output--when configured as an output (i.e. there is an equation written for it in your PSDsoft design file), there is one product term available to it. If your MCU is multiplexed: These pins are the multiplexed, low-order address/data byte (AD0-AD7). As inputs, address information is latched by the ALE/AS signal and used internally by the PSD. The pins also serve as MCU data bus inputs or outputs, depending on the MCU control signals (RD, WR, etc.). If your MCU is non-multiplexed: These pins are the low-order address inputs (A0-A7) If your MCU is multiplexed with a 16-bit data bus: These pins are the multiplexed, high-order address/data byte (AD8-AD15). As inputs, address information is latched by the ALE/AS signal and used internally the PSD. The pins also serve as MCU data bus inputs or outputs, depending on the MCU control signals (RD, WR, etc.). If your MCU is non-multiplexed or has a 8-bit data bus: These pins are the high-order address inputs (A8-A15). Ground Pin Supply voltage input.
I/O
PC0 PC1 PC2
I/O
AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 GND VCC
I/O
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Legend: The Type column abbreviations are: I = input only; I/O = input/output; P = power.
9
PSD3XX Family
8.0 Operating Modes (MCU Configurations)
The PSD3XX's four operating modes enable it to interface directly to most 8- and 16-bit microcontrollers with multiplexed and non-multiplexed address/data busses. The 16-bit modes are not available to some devices; see Table 1. The following are the four operating modes available:
t t t t
Multiplexed 8-bit address/data bus Multiplexed 16-bit address/data bus Non-multiplexed 8-bit data bus Non-multiplexed 16-bit data bus
Please read the section below that corresponds to your type of MCU. Then check the appropriate Figure (3A/3B/3C/3D) to determine your pin connections. Table 3 lists the Port connections in tabular form.
Multiplexed 8-bit address/data bus (Figure 3A) This mode is used to interface to microcontrollers with a multiplexed 8-bit data bus. Since the low-order address and data are multiplexed together, your MCU will output an ALE or AS signal. The PSD3XX contains a transparent latch to demultiplex the address/data lines internally. All you have to do is connect the ALE/AS signal and select 8-bit multiplexed bus mode in PSDsoft. If your MCU outputs more than 16 bits of address, and you wish to connect them to the PSD, connect A16-A18 to Port C and A19 to A19/CSI, where applicable. Multiplexed 16-bit address/data bus (Figure 3B) This mode is used to interface to microcontrollers with a multiplexed 16-bit data bus. Since the low address bytes and data are multiplexed together, your MCU will output an ALE or AS signal. The PSD3XX contains a transparent latch to demultiplex the address/data lines internally. All you have to do is connect the ALE/AS signal and select 8-bit multiplexed bus mode in PSDsoft. If your MCU outputs more than 16 bits of address, and you wish to connect them to the PSD, connect A16-A18 to Port C and A19 to A19/CSI, where applicable. Non-multiplexed 8-bit data bus (Figure 3C) This mode is used to interface to microcontrollers with a non-multiplexed 8-bit data bus. Connect the MCU's address bus to AD0/A0-AD15/A15 on the PSD. Connect the data bus signals of your MCU to Port A of the PSD. If your MCU outputs more than 16 bits of address, and you wish to connect them to the PSD, connect A16-A18 to Port C and A19 to A19/CSI, where applicable.
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Non-multiplexed 16-bit data bus (Figure 3D) This mode is used to interface to microcontrollers with a non-multiplexed 16-bit data bus. Connect the MCU's address bus to AD0/A0-AD15/A15 on the PSD. Connect the low byte data bus signals of your MCU to Port A, and the high byte data output of your MCU to Port B of the PSD. If your MCU outputs more than 16 bits of address, and you wish to connect them to the PSD, connect A16-A18 to Port C and A19 to A19/CSI, where applicable.
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For users with multiplexed MCUs that have data multiplexed on address lines other than A0-A7 note: You can still use the PSD3XX, but you will have to connect your data to Port A (and Port B where required), as shown in Figure 3C or 3D. That is, you will be connecting it as if you were using a non-multiplexed MCU. In this case, you must connect the ALE/AS signal so that the address will still be properly latched. This option is not available on the 3X1 versions.
10
PSD3XX Family
Figure 3A. Connecting a PSD3XX to an 8-Bit Multiplexed-Bus MCU 8.0 Operating Modes AD0 -AD7 (MCU A8 -A15 PA Configurations) ALE/AS
(cont.)
Your 8-bit MCU
PSEN R / W or WR RD/E / DS1 A19 / CSI RESET A16-A182
PSD3XX
PB PC
Figure 3B. Connecting a PSD3XX to a 16-Bit Multiplexed-Bus MCU
AD0 -AD7 AD8 -AD15 ALE/AS BHE/ PSEN R / W or WR RD/E / DS1 A19 / CSI RESET A16-A182
PA PSD3XX PB PC
Your 16-bit MCU
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Your 8-bit MCU
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PA
PSD3XX
PB PC
Your 16-bit MCU
D0 -D15 A0-A15 ALE/AS BHE / PSEN R / W or WR RD/E / DS1 A19 / CSI RESET A16-A182
D0 -D7
PA PSD3XX PB PC
D8-D15
NOTES: 1. DS is a valid input on 3X2/3X3 and devices only. 2. Connect A16-A18 to Port C if your MCU outputs more than 16 bits of address.
11
PSD3XX Family
8.0 Operating Modes (MCU Configurations)
(cont.)
Table 3. Bus and Port Configuration Options Multiplexed Address/Data
8-bit Data Bus
Port A Port B AD0/A0AD7/A7 AD8/A8AD15/A15 I/O or low-order address lines or Low-order multiplexed address/data byte I/O and/or CS0CS7 Low-order multiplexed address/data byte High-order address bus byte D0D7 data bus byte I/O and/or CS0CS7 Low-order address bus byte High-order address bus byte
Non-Multiplexed Address/Data
16-bit Data Bus
Port A Port B AD0/A0AD7/A7 AD8/A8AD15/A15 I/O or low-order address lines or low-order multiplexed address/data byte I/O and/or CS0CS7 Low-order multiplexed address/data byte High-order multiplexed address/data byte Low-order data bus byte High-order data bus byte
Low-order address bus byte
9.0 Programmable Address Decoder (PAD)
The PSD3XX contains two programmable arrays, referred to as PAD A and PAD B (Figure 4). PAD A is used to generate chip select signals derived from the input address to the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals. PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the decoding to select external devices or as a random logic replacement. PAD A and PAD B receive the same inputs. The PAD logic is configured by PSDsoft based on the designer's input. The PAD's non-volatile configuration is stored in a re-programmable CMOS EPROM. Windowed packages are available for erasure by the user. See Table 4 for a list of PAD A and PAD B functions.
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12
PSD3XX Family
Figure 4. PAD Description
P3 P2 ES0 ES1 ES2 ES3 ES4 ES5 ES6 ES7 RS0 8 EPROM BLOCK SELECT LINES
P1
P0
ALE or AS
PAD A
SRAM BLOCK SELECT* I/O BASE ADDRESS TRACK MODE CONTROL SIGNALS
RD/E/DS
WR or R/W
CSIOPORT CSADIN CSADOUT1 CSADOUT2
A19
CS0/PB0 A18 CS1/PB1 A17
A16
A15
A14
A13
A12
A11
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PAD B
CS3/PB3
CS4/PB4
CS5/PB5
CS6/PB6
CS7/PB7
CS8/PC0 CS9/PC1 CS10/PC2
*SRAM no available on "R" versions
NOTES: 1. CSI is a power-down signal. When high, the PAD is in stand-by mode and all its outputs become non-active. See Tables 12 and 13. 2. RESET deselects all PAD output signals. See Tables 10 and 11. 3. A18, A17, and A16 are internally multiplexed with CS10, CS9, and CS8, respectively. Either A18 or CS10, A17 or CS9, and A16 or CS8 can be routed to the external pins of Port C. Port C pins can be configured as either input or output, individually. 4. P0P3 are not included on 3X1 devices. 5. DS is not available on 3X1 devices.
13
PSD3XX Family
Table 4. PSD3XX PAD A and PAD B Functions
Function
PAD A and PAD B Inputs
A19/CSI When the PSD is configured to use CSI and while CSI is a logic 1, the PAD deselects all of its outputs and enters a power-down mode (see Tables 12 and 13). When the PSD is configured to use A19, this signal is another input to the PAD. These are general purpose inputs from Port C. See Figure 4, Note 3. These are address inputs. These are inputs from the page register (not available on 3X1 versions). This is the read pulse or strobe input. (DS not available on 3X1 versions). This is the write pulse or R/W select signal. This is the ALE or AS input to the chip. Use to demultiplex address and data. This deselects all outputs from the PAD; it can not be used in product term equations. See Tables 10 and 11. These are internal chip-selects to the 8 EPROM banks. Each bank can be located on any boundary that is a function of one product term of the PAD address inputs. This is an internal chip-select to the SRAM. Its base address location is a function of one term of the PAD address inputs. This internal chip-select selects the I/O ports. It can be placed on any boundary that is a function of one product term of the PAD inputs. See Tables 5A and 5B. This internal chip-select, when Port A is configured as a low-order address/data bus in the track mode controls the input direction of Port A. CSADIN is gated externally to the PAD by the internal read signal. When CSADIN and a read operation are active, data presented on Port A flows out of AD0/A0AD7/A7. This chip-select can be placed on any boundary that is a function of one product term of the PAD inputs. See Figure 5B. This internal chip-select, when Port A is configured as a low-order address/data bus in track mode, controls the output direction of Port A. CSADOUT1 is gated externally to the PAD by the ALE signal. When CSADOUT1 and the ALE signal are active, the address presented on AD0/A0AD7/A7 flows out of Port A. This chip-select can be placed on any boundary that is a function of one product term of the PAD inputs. See Figure 5B. This internal chip-select, when Port A is configured as a low-order address/data bus in the track mode, controls the output direction of Port A. CSADOUT2 must include the write-cycle control signals as part of its product term. When CSADOUT2 is active, the data presented on AD0/A0AD7/A7 flows out of Port A. This chip-select can be placed on any boundary that is a function of one product term of the PAD inputs. See Figure 5B. These chip-select outputs can be routed through Port B. Each of them is a function of up to four product terms of the PAD inputs. These chip-select outputs can be routed through Port B. Each of them is a function of up to two product terms of the PAD inputs. These chip-select outputs can be routed through Port C. See Figure 4, Note 3. Each of them is a function of one product term of the PAD inputs.
A16A18 A11A15 P0P3 RD/E/DS WR or R/W ALE/AS RESET
PAD A Outputs
ES0ES7 RS0 CSIOPORT
CSADIN
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CSADOUT2
PAD B Outputs
CS0CS3 CS4CS7 CS8CS10
14
PSD3XX Family
10.0 I/O Port Functions
The PSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level. This permits great flexibility and a high degree of customization for specific applications. The next section describes the control registers for the ports. Following that are sections that describe each port. Figures 5 through 7 show the structure of Ports A through C, respectively. Note: any unused input should be connected directly to ground or pulled up to VCC (using a 10K to 100K resistor).
10.1 CSIOPORT Registers
Control of the ports is primarily handled through the CSIOPORT registers. There are 24 bytes in the address space, starting at the base address labeled CSIOPORT. Since the PSD3XX uses internal address lines A15-A8 for decoding, the CSIOPORT space will occupy 2 Kbytes of memory, on a 2 Kbyte boundary. This resolution can be improved to reduce wasted address space by connecting lower order address lines (A7 and below) to Port C. Using this method, resolution down to 256 Kbytes may be achieved. The CSIOPORT space must be defined in your PSDsoft design file. The following tables list the registers located in the CSIOPORT space.
16-Bit Users Note When referring to Table 5B, realize that Ports A and B are still accessible on a byte basis. Note: When accessing Port B on a 16-bit data bus, BHE must be low.
Table 5A. CSIOPORT Registers for 8-Bit Data Busses
Register Name
Port A Pin Register Port A Direction Register Port A Data Register Port B Pin Register
Port B Direction Register Port B Data Register
Power Management Register (Note 1)
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Page Register
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Offset (in hex) from CSIOPORT Base Address
+2 +4 +6 +3 +5 +7 +10 +18
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Type of Access Allowed
Read Read/Write Read/Write Read Read/Write Read/Write Read/Write Read/Write
NOTE: 1. ZPSD only.
Table 5B. CSIOPORT Registers for 16-Bit Data Busses Offset (in hex) from CSIOPORT Base Address
+2 +4 +6 +10 +18
Register Name
Port A/B Pin Register Port A/B Direction Register Port A/B Data Register Power Management Register (Note 1) Page Register
NOTE: 1. ZPSD only.
Type of Access Allowed
Read Read/Write Read/Write Read/Write Read/Write
15
PSD3XX PSD3XX Family
10.0 I/O Port Functions (cont.)
10.2 Port A (PA0-PA7)
The control registers of Port A are located in CSIOPORT space; see Table 5.
10.2.1 Port A (PA0-PA7) in Multiplexed Address/Data Mode Each pin of Port A can be individually configured. The following table summarizes what the control registers (in CSIOPORT space) for Port A do:
Register Name
Port A Pin Register Port A Direction Register Port A Data Register
0 Value
Sampled logic level at pin = `0' Pin is configured as input Data in DFF = `0'
1 Value
Sampled logic level at pin = `1' Pin is configured as output Data in DFF = `1'
Default Value
(Note 1)
X 0 0
NOTE: 1. Default value is the value after reset.
MCU I/O Mode The default configuration of Port A is MCU I/O. In this mode, every pin can be set (at runtime) as an input or output by writing to the respective pin's direction flip-flop (DIR FF, Figure 5A). As an output, the pin level can be controlled by writing to the respective pin's data flip-flop (DFF, Figure 5A). The Pin Register can be read to determine logic level of the pin. The contents of the Pin Register indicate the true state of the PSD driving the pin through the DFF or an external source driving the pin. Pins can be configured as CMOS or open-drain using ST's PSDsoft software. Open-drain pins require external pull-up resistors. Latched Address Output Mode Alternatively, any bit(s) of Port A can be configured to output low-order demultiplexed address bus bit. The address is provided by the internal PSD address latch, which latches the address on the trailing edge of ALE/AS. Port A then outputs the desired demultiplexed address bits. This feature can eliminate the need for an external latch (for example: 74LS373) if you have devices that require low-order latched address bits. Although any pin of Port A may output an address signal, the pin is position-dependent. In other words, pin PA0 of Port A may only pass A0, PA1 only A1, and so on. Track Mode Track Mode sets the entire port to track the signals on AD0/A0-AD7/A7, depending on specific address ranges defined by the PAD's CSADIN, CSADOUT1, and CSADOUT2 signals. This feature lets the user interface the microcontroller to shared external resources without requiring external buffers and decoders. In Track Mode, Port A effectively operates as a bi-directional buffer, allowing external MCUs or host processors to access the local data bus. Keep the following information in mind when setting up Track Mode: t The direction is controlled by: · ALE/AS · RD/E or RD/E/DS (DS on non-3X1 devices only) · WR or R/W · PAD outputs CSADOUT1, CSADOUT2, and CSADIN defined in PSDsoft design. t When CSADOUT1 and ALE/AS are true, the address on AD0/A0-AD7/A7 is output on Port A. Note: carefully check the generation of CSADOUT1 to ensure that it is stable during the ALE/AS pulse. t When CSADOUT2 is active and a write operation is performed, the data on the AD0/A0-AD7/A7 input pins flows out through Port A. t When CSADIN is active and a read operation is performed, the data on Port A flows out through the AD0/A0-AD7/A7 pins. t Port A is tri-stated when none of the above conditions exist.
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PSD3XX Family
10.0 I/O Port Functions (cont.)
10.2.2 Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode In this mode, Port A becomes the low-order data bus byte of the chip. When reading an internal location, data is presented on Port A pins to the MCU. When writing to an internal location, data present on Port A pins from the MCU is written to the desired location.
Figure 5A. Port A Pin Structure
I N T E R N A L A D D R / D A T A B U S A D 0 / A D 7 READ PIN
READ DATA CMOS / OD(1) PORT A PIN
WRITE DATA
CK DFF D R
MCU I/O OUT
ALE
LATCHED ADDR OUT G LATCH D R ADn/ Dn READ DIR MUX
ENABLE
D WRITE DIR CK
O
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RESET CONTROL DECODER WR or R/W RD / E AD0 AD7 ALE or AS
DIR FF R
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INTERNAL READ
I
CSADIN PA0 PA7
INTERNAL ALE O CSADOUT1
AD8 AD15
LATCH
A11 A15
PAD CSADOUT2
(1)
A16 A19
NOTE: 1. The expression for CSADOUT2 must include the following write operation cycle signals: For CRRWR = 0, CSADOUT2 must include WR = 0. For CRRWR = 1, CSADOUT2 must include E = 1 and R/W = 0.
17
PSD3XX PSD3XX Family
10. I/O Port Functions (cont.)
10.3 Port B (PB0-PB7)
The control registers of Port B are located in CSIOPORT space; see Table 5A and 5B.
10.3.1 Port B (PB0-PB7) in Multiplexed Address/Data Mode Each pin of Port B can be individually configured. The following table summarizes what the control registers (in CSIOPORT space) for Port B do:
Register Name
Port B Pin Register Port B Direction Register Port B Data Register
0 Value
Sampled logic level at pin = `0' Pin is configured as input Data in DFF = `0'
1 Value
Sampled logic level at pin = `1' Pin is configured as output Data in DFF = `1'
Default Value
(Note 1)
X 0 0
NOTE: 1. Default value is the value after reset.
MCU I/O Mode The default configuration of Port B is MCU I/O. In this mode, every pin can be set (at run-time) as an input or output by writing to the respective pin's direction flip-flop (DIR FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin's data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the pin. The contents of the Pin Register indicate the true state of the PSD driving the pin through the DFF or an external source driving the pin. Pins can be configured as CMOS or open-drain using ST's PSDsoft software. Open-drain pins require external pull-up resistors. Chip Select Output Alternatively, each bit of Port B can be configured to provide a chip-select output signal from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins is not limited to chip selects only; they can be used for generic combinatorial logic as well. Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7 signals is comprised of two product terms.
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18
PSD3XX PSD3XX Family
10. I/O Port Functions (cont.)
10.3.2 Port B (PB0-PB7) in 16-bit Multiplexed Address/Data Mode In this mode, Port B becomes the low-order data bus byte to the MCU chip. When reading an internal high-order location, data is presented on Port B pins to the MCU. When writing to an internal high-order location, data present on Port B pins from the MCU is written to the desired location.
Figure 6. Port B Pin Structure
READ PIN I N T E R N A L C S O U T B U S I N T E R N A L D A T A B U S CSn D 8 READ DIR
READ DATA CMOS/OD (1) PORT B PIN
WRITE DATA
CK DFF D R Dn
MCU I/O OUT
ENABLE MUX
C S 0
· · ·
7
· · ·
D 1 5 RESET WRITE DIR
D
NOTE: 1. CMOS/OD determines whether the output is open drain or CMOS.
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CONTROL
19
PSD3XX Family
10. I/O Port Functions (cont.)
10.4 Port C (PC0-PC2) Each pin of Port C (Figure 7) can be configured as an input to PAD A and PAD B, or as an output from PAD B. As inputs, the pins are referenced as A16-A18. Although the pins are given this reference, they can be used for any address or logic input. [For example, A8-A10 could be connected to those pins to improve the resolution (boundaries) of CS0-CS7 to 256 bytes.] How they are defined in the PSDsoft design file determines:
· Whether they are address or logic inputs · Whether the input is transparent or latched by the trailing edge of ALE/AS.
Notes: 1) If the inputs are addresses, they are routed to PAD A and PAD B, and can be used in any or all PAD equations. 2) A logic input is routed to PAD B and can be used for Boolean equations that are implemented in any or all of the CS0-CS10 PAD B outputs. Alternately, PC0-PC2 can become CS8-CS10 outputs, respectively, providing the user with more external chip-select PAD outputs. Each of the signals (CS8-CS10) is comprised of one product term.
Figure 7. Port C (PC0-PC2) Pin Structure
CS8 / CS9 / C S10 From PAD Latched Address Input A16/A17/A18 To PAD
Q
D En
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NOTES: 1. Port C pins can be individually configured as inputs or outputs, but not both. Pins can be individually configured as address or logic and latched or transparent, except for the 3X1 devices, which must be set to all address or all logic. 2. PSDsoft sets this configuration prior to run-time based on your PSDsoft design file.
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Address In or Chip Select Out Port C I/O1 (PC0 / P C1/ P C2)
D E M U X
Input or Output Set by PSDsoft 2
PSDsoft 2
10.5 ALE/AS Input Pin The ALE/AS pin may be used as a generic logic input signal to the PADs if a non-multiplexed MCU configuration is chosen in PSDsoft.
20
PSD3XX Family
11. PSD Memory
The following sections explain the various memory blocks and memory options within the PSD3XX.
11.1 EPROM For all of the PSD3XX devices, the EPROM is built using Zero-power technology. This means that the EPROM powers up only when the address changes. It consumes power for the necessary time to latch data on its outputs. After this, it powers down and remains in Standby Mode until the next address change. This happens automatically, and the designer has to do nothing special.
The EPROM is divided into eight equal-sized banks. Each bank can be placed in any address location by programming the PAD. Bank0-Bank7 are selected by PAD A outputs ES0-ES7, respectively. There is one product term for each bank select (ESi). Refer to Table 1 to see the size of the EPROM for each PSD device.
11.2 SRAM (Optional) Like the EPROM, the optional SRAM in the PSD3XX devices is built using Zero-power technology.
All PSD3XX parts which do not have an R suffix contain 2 Kbytes of SRAM (Table 1). The SRAM is selected by the RS0 output of the PAD. There is one product term dedicated to RS0. If your design requires a SRAM larger than 2K x 8, then use one of the RAMless (R versions) of the 3XX devices with an external SRAM. The external SRAM can be addressed trhough Port A and all require logic will be taken care of by the PSD3XXR.
11.3 Page Register (Optional) All PSD3XX parts, except 3X1devices, have a four-bit page register. Thus the effective address space of your MCU can be enlarged by a factor of 16. Each bit of the Page Register can be individually read or written. The Page Register is located in CSIOPORT space (at offset 18h); see Table 5. The Page Register is connected to the lowest nibble of the data bus (D3-D0). The outputs of the Page Register, P3-P0, are connected to PAD A, and therefor can be used in any chip select (internal or external) equations. The contents of the page register are reset to zero at power-up and after any chip-level reset. 11.4 Programming and Erasure Programming the device can be done using the following methods: ·STs main programmer--PSDpro--which is accessible through a parallel port. ' · ST's programmer used specifically with the PSD3XX--PEP300. ·STs discontinued programmer--Magic Pro. ' · A 3rd party programmer, such as Data I/O. Information for programming the device is available directly from ST. Please contact your local sales representative. Also, check our web site (www.st.com/psm) for information related to 3rd party programmers.
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Upon delivery from ST or after each erasure (using windowed part), the PSD3XX device has all bits in PAD and EPROM in the HI state (logic 1). The configuration bits are in the LO state (logic 0). To clear all locations of their programmed contents (assuming you have a windowed version), expose the windowed device to an Ultra-Violet (UV) light source. A dosage of 30 W second/cm2 is required for PSD3XX devices, and 40 W second/cm2 for low-voltage (V suffix) devices. This dosage can be obtained with exposure to a wavelength of 2537 Å and intensity of 12000 W/cm2 for 40 to 45 minutes for the PSD3XX and 55 to 60 minutes for the low-voltage (V suffix) devices. The device should be approximately 1 inch (2.54 cm) from the source, and all filters should be removed from the UV light source prior to erasure. The PSD3XX devices will erase with light sources having wavelengths shorter than 4000 Å. However, the erasure times will be much longer than when using the recommended 2537 Å wavelength. Note: exposure to sunlight will eventually erase the device. If used in such an environment, the package window should be covered with an opaque substance.
21
PSD3XX Family
12.0 Control Signals
Consult your MCU data sheet to determine which control signals your MCU generates, and how they operate. This section is intended to show which control signals should be connected to what pins on the PSD3XX. You will then use PSDsoft to configure the PSD3XX, based on the combination of control signals that your MCU outputs, for example RD, WR, and PSEN. The PSD3XX is compatible with the following control signals: · ALE or AS (polarity is programmable) · WR or R/W · RD/E or RD/E/DS (DS for non-3X1 devices only) · BHE or PSEN · A19/CSI · RESET (polarity is programmable except on low voltage versions with the V suffix).
12.1 ALE or AS
Connect the ALE or AS signal from your MCU to this pin where applicable, and program the polarity using PSDsoft. The trailing edge (when the signal goes inactive) of ALE or AS latches the address on any pins that have an address input. If you are using a non-multiplexed-bus MCU that does not output an ALE or AS signal, this pin can be used for a generic input to the PAD. Note: if your data is multiplexed with address lines other than A0-A7, connect your address pins to AD0/A0-AD15/A15, and connect your data to Port A (and Port B where applicable), and connect the ALE/AS signal to this pin.
12.2 WR or R/W
Your MCU should output a stand-alone write signal (WR) or a multiplexed read/write signal (R/W). In either case, the signal should be connected to this pin.
12.3 RD/E/DS (DS option not available on 3X1 devices)
Your MCU should output any one of RD, E (clock), or DS. In any case, connect the appropriate signal to this pin.
12.4 BHE or PSEN t If your MCU does not output either of these signals, tie this pin to Vcc
(through a series resistor), and skip to the next signal.
t If you use an 8-bit 8031 compatible MCU that outputs a separate signal when
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accessing program space, such as PSEN, connect it to this pin. You would then use PSDsoft to configure the EPROM in the PSD3XX to respond to PSEN only or PSEN and RD. If you have an 8031 compatible MCU, refer to the "Program/Data Space and the 8031" section for further information. BHE enables accessing of the upper byte of the data bus. See Table 6 for information on how this signal is used in conjunction with the A0 address line.
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t If you are using a 16-bit MCU, connect the BHE (or similar signal) output to this pin.
Table 6. Truth Table for BHE and Address Bit A0 (16-bit MCUs only)
BHE
0 0 1 1
A0
0 1 0 1
Operation
Whole Word Upper Byte From/To Odd Address Lower Byte From/To Even Address None
22
PSD3XX Family
12.0 Control Signals (cont.)
12.5 A19/CSI
This pin is configured using PSDsoft to be either a chip select for the entire PSD device or an additional PAD input. If your MCU can generate a chip-select signal, and you wish to save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic input.
t When configured as CSI (active-low PSD chip select): a low on this pin keeps the PSD
in normal operation. However, when a high is detected on the pin, the PSD enters Power-down Mode. See Tables 7A and 7B for information on signal states during Power-down Mode. See section 16 for details about the reduction of power consumption.
t When configured as A19, the pin can be used as an additional input to the PADs.
It can be used for address or logic. It can also be ALE/AS dependent or a transparent input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always enabled.
Table 7A. Signal States During Power-Down Mode Port
AD0A0/AD15/A15 Port Pins PA0PA7 All MCU I/O Tracking AD0/A0-AD7/A7 Latched Address Out MCU I/O Port Pins PB0PB7
Configuration Mode(s)
Chip Select Outputs, CS0CS7, CMOS Chip Select Outputs, CS0CS7, Open Drain
Port Pins PC0PC2
Table 7B. Internal States During Power-down
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PAD A and PAD B
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Address or Logic Inputs, A16-A18 Chip Select Outputs, CS8CS10, CMOS only
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State
Input (Hi-Z) Unchanged Input (Hi-Z) Logic 1 Unchanged Logic 1 Hi-Z Input (Hi-Z) Logic 1
Internal Signal
CS0CS10 CSADIN, CSADOUT1, CSADOUT2, CSIOPORT, ES0-ES7, RS0 N/A
Internal Signal State During Power-Down
Logic 1 (inactive) Logic 0 (inactive)
All registers in CSIOPORT address space, including: Direction Data Page PMR (turbo bit, ZPSD only)
NOTE: N/A = Not Applicable
All unchanged
23
PSD3XX Family
12.0 Control Signals
(cont.)
12.6 Reset Input
This is an asynchronous input to initialize the PSD device. Refer to tables 8A and 8B for information on device status during and after reset. The standard-voltage PSD3XX and ZPSD3XX (non-V) devices require a reset input that is asserted for at least 100 nsec. The PSD will be functional immediately after reset is de-asserted. For these standard-voltage devices, the polarity of the reset input signal is programmable using PSDsoft (active-high or active-low), to match the functionality of your MCU reset. Note: It is not recommended to drive the reset input of the MCU and the reset input of the PSD with a simple RC circuit between power on ground. The input threshold of the MCU and the PSD devices may differ, causing the devices to enter and exit reset at different times because of slow ramping of the signal. This may result in the PSD not being operational when accessed by the MCU. It is recommended to drive both devices actively. A supervisory device or a gate with hysteresis is recommended. For low-voltage ZPSD3XXV devices only, the reset input must be asserted for at least 500 nsec. The ZPSD3XXV will not be functional for an additional 500 nsec after reset is de-asserted (see Figure 8). These low voltage ZPSD3XXV devices must use an active-low polarity signal for reset. Unlike the standard PSDs, the reset polarity for the ZPSD3XXV is not programmable. If your MCU operates with an active high reset, you must invert this signal before driving the ZPSD3XXV reset input. You must design your system to ensure that the PSD comes out of reset and the PSD is active before the MCU makes its first access to PSD memory. Depending on the characteristics and speed of your MCU, a delay between the PSD reset and the MCU reset may be needed.
Table 8A. External PSD Signal States During and Just After Reset
Port
AD0/A0AD15/A15
Configured Mode of Operation
All
MCU I/O
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Port Pins PB0-PB7
Port Pins PA0-PA7
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Signal State During Reset
Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Logic 0 Hi-Z Input (Hi-Z
Signal State Just After Reset
(Note 1) MCU address and/or data Input (Hi-Z) Active Track Mode MCU address MCU address Input (Hi-Z) Per CS equations Per CS equations Per CS equations Per CS equations Input (Hi-Z) Per CS equations Per CS equations
Latched Address Out MCU I/O Chip Select Outputs, CS0-CS7, CMOS Chip Select Outputs, CS0-CS7, Open Drain
PSD3XX, ZPSD3XX ZPSD3XXV PSD3XX, ZPSD3XX ZPSD3XXV PSD3XX, ZPSD3XX ZPSD3XXV
Logic 1 Hi-Z Hi-Z Hi-Z Input (Hi-Z) Logic 1 Hi-Z
Address or Logic Inputs, A16-A18 Port Pins PC0-PC2 Chip Select Outputs, CS8-CS10, CMOS
NOTE: 1. Signal is valid immediately after reset for PSD3XX and ZPSD3XX devices. ZPSD3XXV devices need an additional 500 nsec after reset before signal is valid.
24
PSD3XX Family
12.0 Control Signals
(cont.)
Table 8B. Internal PSD Signal States During and Just After Reset Internal Signal State During Reset Internal Signal State During Power-Down
Component
Internal Signal
CS0-CS10 CSADIN, CSADOUT1, CSADOUT2, CSIOPORT, ES0-ES7, RS0
Logic 1 (inactive) Per CS Equations Per equations for each internal signal
PAD A and PAD B
Logic 0 (inactive)
All registers in CSIOPORT address space, including: Direction Data Page PMR (turbo bit, ZPSD3XX only)
NOTE: N/A = Not Applicable
N/A
Logic 0 in all bit of Logic 0 until all registers changed by MCU
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ZPSD3XXV IS OPERATIONAL
25
PSD3XX Family
13.0 Program/Data Space and the 8031
This section only applies to users who have an 8031 or compatible MCU that outputs a signal such as PSEN when accessing program space. If this applies to you, be aware of the following:
t The PSD3XX can be configured using PSDsoft such that the EPROM is either
1) accessed by PSEN only (Figure 10); or 2) accessed by PSEN or RD (Figure 9). The default is PSEN only unless changed in PSDsoft.
t The SRAM and I/O Ports (including CSIOPORT) can not be placed in program space
only. By default, they are in data space only (Figure 10). However, the SRAM may be placed in Program and Data Space, as shown in Figure 9.
Figure 9. Combined Address Space
CS ADDRESS PAD SRAM*
OE
INTERNAL RD
PSEN
*Not available on "R" versions.
Figure 10. 8031-Compatible Separate Code and Data Address Spaces
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INTERNAL RD
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CS EPROM PSEN OE
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26
PSD3XX Family
14.0 System Applications
In Figure 11, the PSD3XX is configured to interface with Intel's 80C31, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 80C31 uses signals RD to read from data memory and PSEN to read from code memory. It uses WR to write into the data memory. It also uses active high reset and ALE signals. The rest of the configuration bits, as well as the unconnected signals, are application specific, and thus, user dependent.
Figure 11. PSD3XX Interface With Intel's 80C31
VCC
MICROCONTROLLER
31 19 EA/VP X1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7
0.1F 44 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 A19/CSI GND 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43
18
X2
9
RESET
12 13 14 15 1 2 3 4 5 6 7 8
INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
Reset
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AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15
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RD WR/VPP BHE/PSEN ALE RESET
80C31
PSD3XX
34
12
NOTE: RESET to the PSD3XX must be the output of a RESET chip or buffer. If RESET to the 80C31 is the output of an RC circuit, a separate buffered RC RESET to the PSD3XX (shorter than the 80C31 RC RESET) must be provided to avoid a race condition.
27
PSD3XX Family
14.0 System Applications
(cont.)
In Figure 12, the PSD3XX is configured to interface with Motorola's 68HC11, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 68HC11 uses E and R/W signals to derive the read and write strobes. It uses the Address Strobe (AS) for the address latch pulse. RESET is an active-low signal. The rest of the configuration bits, as well as the unconnected signals, are specific, and thus, user dependent.
Figure 12. PSD3XX Interface With Motorola's 68HC11
VCC
MICROCONTROLLER
20 21 22 23 24 25 43 45 47 49 44 46 48 50 34 33 32 31 30 29 28 27 52 51 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 E R/W AS RESET XIRQ IRQ MODB MODA 9 10 11 12 13 14 15 16 42 41 40 39 38 37 36 35 5 6 4 17 18 19 2 3 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 22
0.1F 44 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 A19/CSI 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43
PD0 PD1 PD2 PD3 PD4 PD5 PE0 PE1 PE2 PE3 PD4 PE5 PE6 PE7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
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R/W/VPP AS RESET BHE/PSEN
GND
XTAL EXTAL
PSD3XX
34
12
68HC11
28
PSD3XX Family
14.0 System Applications
(cont.)
In Figure 13, the PSD3XX is configured to work directly with Intel's 80C196KB microcontroller, which is a 16-bit address/16-bit data bus processor. The Address and data lines multiplexed. The PSD3XX is configured to use PC0, PC1, PC2, and A19/CSI as logic inputs. These signals are independent of the ALE pulse (latch-transparent). They are used as four general-purpose inputs that take part in the PAD equations. Port A is configured to work in Track Mode, in which (for certain conditions) PA0PA7 tracks lines AD0/A0AD7/A7. Port B is configured to generate CS0CS7. In this example, PB2 serves as a WAIT signal that slows down the 80C196KB during the access of external peripherals. These 8-bit wide peripherals are connected to the shared bus of Port A. The WAIT signal also drives the buswidth input of the microcontroller, so that every external peripheral cycle becomes an 8-bit data bus cycle. PB3 and PB4 are open-drain output signals; thus, they are pulled up externally.
Figure 13. PSD3XX Interface With Intel's 80C196KB
+5V +5V
0.1F ADDRESS/DATA MULTIPLEXED BUS P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0/AD0 P3.1/AD1 P3.2/AD2 P3.3/AD3 P3.4/AD4 P3.5/AD5 P3.6/AD6 P3.7/AD7 19 20 21 22 23 30 31 32 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 65 41 40 61 62 63 28 29 34 35
0.1F
VCC 67 XTAL1
66 NMI 3 43 64 14 16 6 5 7 4 11 10 8 9 RxD TxD 18 17 15 44 42 39 33 38
XTAL2 NMI READY BUSWIDTH CDE RESET P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
RST
+5V
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FOUR GENERAL PURPOSE INPUTS
0.1F
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24 25 26 27 13 37 12 2 VREF VPP ANGND EA
P2.0/TXD P2.1/RXD P2.2/EXINT P2.3/T2CLK P2.4/T2RST P2.5/PWM P2.6/ T2 UP/DN P2.7/ T2 CAPTR HSI.0 HSI.1 HSI.2/HSO.4 HSI.3/HSO.5
so Ob P4.0/AD8 P4.1/AD9 P4.2/AD10 P4.3/AD11 P4.4/AD12 P4.5/AD13 P4.6/AD14 P4.7/AD15 CLKOUT BHE / WRH WR / WRL RD ALE /ADV INST HSO.0 HSO.1 HSO.2 HSO.3 VSS 36 68
AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7
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AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 1 2 22 13 3
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AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI BHE /PSEN WR / VPP RD ALE RESET
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PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
AD[0 ..15]
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SHARED BUS
AD[0 ..15]
PORT 1 I/O PINS
44 VCC 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4
AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15
WAIT
4.7K
4.7K
+5V
VSS
GND GND
80C196KB
PSD3XX
12
34
ALE
29
PSD3XX Family
15.0 Security Mode
Security Mode in the PSD3XX locks the contents of PAD A, PAD B, and all the configuration bits. The EPROM, optional SRAM, and I/O contents can be accessed only through the PAD. The Security Mode must be set by PSDsoft prior to run-time. The Security Bit can only be erased on the UV parts using a full-chip erase. If Security Mode is enabled, the contents of the PSD3XX can not be uploaded (copied) on a device programmer.
16.0 Power Management
PSDs from all PSD3XX families use Zero-power memory techniques that place memory into Standby Mode between MCU accesses. The memory becomes active briefly after an address transition, then delivers new data to the outputs, latches the outputs, and returns to Standby. This is done automatically and the designer has to do nothing special to benefit from this feature. In addition to the benefits of Zero-power memory technology, there are ways to gain additional savings. The following factors determine how much current the entire PSD device uses: · Use of CSI (Chip Select Input) · Setting of the CMiser bit · Setting of the Turbo Bit (ZPSD only) · The number of product terms used in the PAD · The composite frequency of the input signals to the PAD · The loading on I/O pins. The total current consumption for the PSD is calculated by summing the currents from memory, PAD logic, and I/O pins, based on your design parameters and the power management options used.
16.1 CSI Input
Driving the CSI pin inactive (logic 1) disables the inputs of the PSD and forces the entire PSD to enter Power-down Mode, independent of any transition on the MCU bus (address and control) or other PSD inputs. During this time, the PSD device draws only standby current (micro-amps). Alternately, driving a logic 0 on the CSI pin returns the PSD to normal operation. See Tables 7A and 7B for information on signal states during Power-down Mode.
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The CSI pin feature is available only if enabled in the PSDsoft Configuration utility.
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In addition to power savings resulting from the Zero-power technology used in the memory, the CMiser feature saves even more power under certain conditions. Savings are significant when the PSD is configured for an 8-bit data path because the CMiser feature turns off half of the array when memory is being accessed (the memory is divided internally into odd and even arrays). See the DC characteristics table for current usage related to the CMiser bit. You should keep the following in mind when using this bit: · Setting of this bit is accomplished with PSDsoft at the design stage, prior to run-time. · Memory access times are extended by 10 nsec for standard voltage (non-V) devices, and 20 nsec for low voltage (V) devices. · EPROM access: although CMiser offers significant power savings in 8-bit mode (~50%), CMiser contributes no additional power savings when the PSD is configured for 16-bits. · SRAM access: CMiser reduces power consumption of PSDs configured for either 8-bit or 16-bit operation.
30
PSD3XX Family
16. Power Management
(cont.)
16.3 Turbo Bit (ZPSD only)
The turbo bit is controlled by the MCU at run-time and is accessed through bit zero of the Power Management Register (PMR). The PMR is located in CSIOPORT space at offset 10h.
Power Management Register (PMR)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
*
1= OFF
*
1= OFF
*
1= OFF
*
1= OFF
*
1= OFF
*
1= OFF
*
1= OFF
Bit 0 Turbo bit 1= OFF
*Future Configuration bits are reserved and should be set to one when writing to this register. The default value at reset of all bits in the PMR is logic 0, which means the Turbo feature is enabled. The PAD logic (PAD A and PAD B) of the PSD will operate at full speed and full power. When the Turbo Bit is set to logic 1, the Turbo feature is disabled. When disabled, the PAD logic will draw only standby current (micro-amps) while no PAD inputs change. Whenever there is a transition on any PAD input (including MCU address and control signals), the PAD logic will power up and will generate new outputs, latch those outputs, then go back to Standby Mode. Keep in mind that the signal propagation delay through the PAD logic increases by 10 nsec for non-V devices, and 20 nsec for V devices while in non-turbo mode. Use of the Turbo Bit does not affect the operation or power consumption of memory. Tremendous power savings are possible by setting the Turbo Bit and going into non-turbo mode. This essentially reduces the DC power consumption of the PAD logic to zero. It also reduces the AC power consumption of PAD logic when the composite frequency of all PAD inputs change at a rate less than 40 MHz for non-V devices, and less than 20 MHz for V devices. Use Figures 14 and 15 to calculate AC and DC current usage in the PAD with the Turbo Bit on and off. You will need to know the number of product terms that are used in your design and you will have to calculate the composite frequency of all signals entering the PAD logic.
16.4 Number of Product Terms in the PAD Logic
The number of product terms used in your design relates directly to how much current the PADs will draw. Therefore, minimizing this number will be in your best interest if power is a concern for you. Basically, the amount of product terms your design will use is based on the following (see Figure 4): · Each of the EPROM block selects, ES0-ES7 uses one product term (for a total of 8). · The CSIOPORT select uses one product term. · If your part has SRAM (non-R versions), the SRAM select RS0 uses one product term. · The Track Mode control signals (CSADIN, CSADOUT1, and CSADOUT2) each use one product term if you use these signals. · Port B, pins PB0-PB3 are allocated four product terms each if used as outputs. · Port B, pins PB4-PB7 are allocated two product terms each if used as outputs. · Port C, pins PC0-PC2 are allocated one product term each if used as outputs.
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Given the above product term allocation, keep the following points in mind when calculating the total number of product terms your design will require: 1) The EPROM block selects, CSIOPORT select, and SRAM select will use a product term whether you use these blocks or not. This means you start out with 10 product terms, and go up from there. 2) For Port B, if you use a pin as an output and your logic equation requires only one product term, you still have to include all the available product terms for that pin for power consumption, even though only one product term is specified. For example, if the output equation for pin PB0 uses just one product term, you will have to count PB0 as contributing four product terms to the overall count. With this in mind, you should use Port C for the outputs that only require one product term and PB4-7 for outputs that require two product terms. Use pins PB0-3 if you need outputs requiring more than two product terms or you have run out of outputs. 3) The following PSD functions do not consume product terms: MCU I/O mode, Latched Address Output, and PAD inputs (logic or address).
31
PSD3XX Family
16.0 Power Management
(cont.)
16.5 Composite Frequency of the Input Signals to the PAD Logic
The composite frequency of the input signals to the PADs is calculated by considering all transitions on any PAD input signal (including the MCU address and control inputs). Once you have calculated the composite frequency and know the number of product terms used, you can determine the total AC current consumption of the PAD by using Figure 14 or Figure 15. From the figures, notice that the DC component (f = 0 MHz) of PAD current is essentially zero when the turbo feature is disabled, and that the AC component increases as frequency increases. When the turbo feature is disabled, the PAD logic can achieve low power consumption by becoming active briefly, only when inputs change. For standard voltage (non-V) devices, the PAD logic will stay active for 25 nsec after it detects a transition on any input. If there are more transitions on any PAD input within the 25 nsec period, these transitions will not add to power consumption because the PAD logic is already active. This effect helps reduce the overall composite frequency value. In other words, narrowly spaced groups of transitions on input signals may count as just one transition when estimating the composite frequency. Note that the "knee" frequency in Figure 14 is 40 MHz, which means that the PAD will consume less power only if the composite frequency of all PAD inputs is less than 40 MHz. When the composite frequency is above 40 MHz, the PAD logic never gets a chance to shut down (inputs are spaced less than 25 nsec) and no power savings can be achieved. Figure 15 is for low-voltage devices in which the "knee" frequency is 20 MHz. Take the following steps to calculate the composite frequency: 1) Determine your highest frequency input for either PAD A or PAD B. 2) Calculate the period of this input and use this period as a basis for determining the composite frequency. 3) Examine the remaining PAD input signals within this base period to determine the number of distinct transitions. 4) Signal transitions that are spaced further than 25 nsec apart count as a distinct transition (50 nsec for low-voltage V devices). Signal transitions spaced closer than 25 nsec count as the same transition. 5) Count up the number of distinct transitions and divide that into the value of the base period. 6) The result is the period of the composite frequency. Divide into one to get the composite frequency value. Unfortunately, this procedure is complicated and usually not deterministic since different inputs may be changing in various cycles. Therefore, we recommend you think of the situation that has the most activity on the inputs to the PLD and use this to calculate the composite frequency. Then you will have a number that represents your best estimate at the worst case scenario. Since this is a complicated process, the following example should help.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Example Composite Frequency Calculation
Suppose you had the following circuit:
80C31 (12 MHz Crystal)
AD0-AD7 A8-A15 ALE RD WR PSEN CSI
PSD3XX PA PB PC
Latched Address Output (LA0-LA7) 3 Inputs: Int, Sel, Rdy 5 MCU I/O Outputs 3 Chip-Select Outputs
32
PSD3XX Family
16.0 Power Management
(cont.)
All the inputs shown, except CSI, go to the PAD logic. These signals must be taken into consideration when calculating the composite frequency. Before we make the calculation, let's establish the following conditions: · The input with the highest frequency is ALE, which is 2 MHz. So our base period is 500 nsec for this example. · Only the address information from the multiplexed signals AD0-AD7 reach the PAD logic because of the internal address latch. Signal transitions from data on AD0-AD7 do not reach the PADs. · The three inputs (Int, Sel, or Rdy) change state very infrequently relative to the 80C31 bus signals. Now, lets assume the following is a snapshot in time of all the input signals during a typical 80C31 bus cycle. We'll use a code fetch as an example since that happens most often.
ONE TYPICAL 80C31 BUS CYCLE (2 MHz, 500 nsec)
ALE PSEN 1 AD0-AD7 A8-A15 INT SEL RDY ADDR 2 DATA
bs O
let o
Pr e
The calculation of the composite frequency is as follows: · There are four distinct transitions (first four dotted lines) within the base period of 500 nsec. These first four transitions all count toward the final composite frequency. · The transition at (1) in the diagram does not count as a distinct transition because it is within 25 nsec of a neighboring transition (use 50 nsec for a ZPSD3XXV device). · Transition (2) above does not add to the composite frequency because only the internally latched address signals reach the PADs, the data signal transitions do not. · The transition at (3) just happens to appear in this snapshot, but its frequency is so low that it is not a significant contributor to the overall composite frequency, and will not be used. · Divide the 500 nsec base period by the four (distinct transitions), yielding 125 nsec. 1/125 nsec = 8 MHz. · Use 8 MHz as the composite frequency of PAD inputs when calculating current consumption. (See the next section for a sample current calculation.)
du o
(s) ct
Ob -
so
te le
< 25 nsec
ro P
3
uc d
s) t(
FOUR DISTINCT TRANSITIONS
16.6 Loading on I/O pins
A final consideration when calculating the current usage for the entire PSD device is the loading on I/O pins. All specifications for PSD current consumption in this document assume zero current flowing through PSD I/O pins (including ADIO). I/O current is dictated by the individual design implementation, and must be calculated by the designer. Be aware that I/O current is a function of loading on the pins and the frequency at which the signals toggle.
33
PSD3XX Family
17. Calculating Power
Once you have read the "Power Management" section, you should be able to calculate power. The following is a sample power calculation:
Conditions
Part Used MCU ALE Clock Frequency Composite ZPLD Input Frequency % EPROM Access % SRAM Access % I/O access %Time CSI is high (standby mode) %Time CSI is low (normal operation mode) # Product terms used (see previous section) Turbo bit CMiser bit MCU Bus Configuration = = = = = = = = = = = = ZPSD3XX (VCC = 5.0 V) 2.0 MHz 8.0 MHz (see example in above section) 80% 15% 5% 90% 10% 13 (13/40 = 33%) OFF (Turbo Mode disabled) ON 8-bit multiplexed bus mode
Calculation (Based on Typical AC and DC Currents)
ICC total = Istandby x % time CSI is high + [ICC (AC) + ICC (DC)] x % time CSI is low. = Istandby x % time CSI is high + [% EPROM Access x 0.8 mA/MHz x Freq. of ALE + % SRAM x 1.4 mA/MHz x Freq of ALE + ZPLD AC current (Figure 14: 13 PTs, 8 MHz, Non-Turbo)] x % time CSI is low = 10 A x 0.9 + (0.8 x 0.8 mA/MHz x 2 MHz + 0.15 x 1.4 mA/MHz x 2 MHz + 5.0 mA) x 0.1 = 9.0 A + (1.28 mA + 0.42 mA + 5.0 mA) x 0.1 = 679 A, based on the system operating in standby 90% of the time
bs O
let o
Pr e
NOTES: 1. 2. 3. 4. 5.
du o
Calculation is based on the assumption that IOUT = 0 mA (no I/O pin loading) ICC(DC) is zero for all ZPSD devices operating in non-turbo mode. 13 product terms: 8 for EPROM, 3 for Chip Selects, 1 for SRAM, 1 for CSIOPORT. The 5% I/O access in the conditions section is when the MCU accesses CSIOPORT space. Standby Mode can also be achieved without using the CSI pin. The ZPSD device will automatically go into Standby while no inputs are changing on any pin, and Turbo Mode is disabled.
(s) ct
so Ob -
te le
ro P
uc d
s) t(
34
PSD3XX Family
17.0 Calculating Power
(cont.)
Figure 14. Typical ICC vs. Frequency for the PAD (VCC = 5 V)
45
40 PT Turbo
40 35 30 ICC (mA 25 20 15 10 5 0 0 5
40 PT Non-Turbo 10 PT Turbo 10 PT Non-Turbo
10
15
20
25
30
35
40
Composite Frequency at PAD Inputs (MHz)
bs O
let o
ro Figure 15. Typical I vs. Frequency (V = 3 V)P te ole bs -O (s) ct du ro P e
CC CC
14 12 10 8 6 4 2 0 0 5 10 15
40 PT Turbo 40 PT Non-Turbo 10 PT Turbo 10 PT Non-Turbo
uc d
s) t(
45
50
ICC (mA
20
25
Composite Frequency at PAD Inputs (MHz)
35
PSD3XX Family
Figure 16. IOL vs. VOL (5 V 10%) ZPSD3XXV
40
Figure 17. Normalized ICC (DC vs. VCC ) (VCC = 3.0 V) ZPSD3XXV
3.5 3.0 2.5 ICC 2.0 1.5 1.0
35
30
25 IOL (mA)
20
15
0.5
10 Temp. = 125C Temp. = 25C 5
2.5 3.0 2.7
3.5
4.0
4.5 (V) VCC
5.0
0 0.00 0.10 0.20 0.30 0.40 VOL (V) 0.50 0.60 0.70 0.80
Figure 18. Normalized ICC (AC) (VCC = 3.0 V) ZPSD3XXV
2.2 2.0 1.8 ICC (AC) 1.6 1.4 1.2 1.0 0.8 2.5 3.0 2.7 3.5 4.0 4.5 VCC (V) 5.0 5.5 6.0
ACCESS TIME
bs O
let o
ro P e
du
ct
(s)
so Ob 1.1 1.05 1.0 0.95 0.9 0.85 0.8 0.75 0.7 0.65
Figure 19. Normalized Access Time (T6) (VCC = 3.0 V) ZPSD3XXV
te le
ro P
uc d
s) t(
5.5
6.0
2.5 3.0 2.7
3.5
4.0
4.5 VCC (V)
5.0
5.5
6.0
36
PSD3XX Family
18.0 Specifications
18.1 Absolute Maximum Ratings 1 Symbol Parameter
TSTG Storage Temperature Voltage on any Pin VPP VCC Programming Supply Voltage Supply Voltage ESD Protection
Condition
CERDIP PLASTIC With Respect to GND With Respect to GND With Respect to GND
Min
65 65 0.6 0.6 0.6
Max
+ 150 + 125 +7 + 14 +7
Unit
C C V V V V
>2000
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
18.2 Operating Range Range
Commercial Industrial
Temperature
0 C to +70C 40 C to +85C +3
VC C
+ 3 V1, + 5 V V1, +5V
NOTES: 1. 3 V version available for ZPSD3XXV devices only.
18.3 Recommended Operating Conditions Symbol
VCC VCC
Parameter
Supply Voltage Supply Voltage
18.4 Pin Capacitance 1
bs O
let o
ro P e
CIN
Symbol
COUT
du
(s) ct
so Ob Parameter
Conditions
ZPSD Versions, All Speeds
te le
ro P
uc d
Min
4.5 2.7
s) t(
VC C Tolerance
10% 10%
Typ Max Unit
5 3.0 5.5 5.5 V V
ZPSD V Versions Only, All Speeds
Conditions
VIN = 0 V VOUT = 0 V VPP = 0 V
Typical 2 Max Unit
4 8 18 6 12 25 pF pF pF
Capacitance (for input pins only) Capacitance (for input/output pins) Capacitance (for WR/VPP or R/W/VPP)
CVPP
NOTES: 1. This parameter is only sampled and is not 100% tested. 2. Typical values are for TA = 25C and nominal supply voltages.
37
PSD3XX Family
18.5 AC/DC Characteristics PSD3XX/ZPSD3XX (All 5 V devices)
Symbol
VCC VI H VI L VOH
Parameter
Supply Voltage High-Level Input Voltage Low-Level Input Voltage Output High Voltage Output Low Voltage (See Figure 16) ZPSD3XX Standby Supply Current Standby Supply Current All Speeds
Conditions
Min
4.5 2 0.5 4.4 2.4
Typ
5
Max
5.5 VCC + .1 0.8
Unit
V V V V V
4.5 V < VCC > 5.5 V 4.5 V < VCC > 5.5 V IOH = 20 A, VCC = 4.5 V IOH = 2 mA, VCC = 4.5 V IOL = 20 A, VCC = 4.5 V IOL = 8 mA, VCC = 4.5 V
4.49 3.9 0.01 0.15 10 50 0.1 0.45 20 100 1
V V A A A A A
VOL
ISB
(Notes 1,4) PSD3XX
ILI ILO
Input Leakage Current Output Leakage Current
VSS < VIN > VCC .45 < VIN > VCC ZPLD Turbo Mode = Off, f = 0 MHz
1 10
.1 5
ZPSD3XX Operating Suppy Current ICC (DC) (Note 3) PSD3XX Operating Supply Current
ZPLD Turbo Mode = On, f = 0 MHz EPROM, f = 0 MHz SRAM, f = 0 MHz PLD, f = 0 MHz
EPROM, f = 0 MHz SRAM, f = 0 MHz
ZPLD AC Base EPROM Access AC Adder
ICC (AC) (Note 3)
NOTES: 1. 2. 3. 4. 5.
O
bs
let o
ro P e
du
(s) ct
Ob -
so
te le
ro P
See ISB 0.5 0 0 0.5 0 0 See Fig. 14 0.8 1.8 1.4 2 3.8
uc d
s) t(
10 1 0 0 1 0 0 1.0 2.0 4.0 2.7 4 7.5
mA/PT A A mA/PT A A mA/MHz mA/MHz mA/MHz mA/MHz mA/MHz mA/MHz
CMiser = On and 8-Bit Bus Mode All Other Cases (Note 5) CMiser = On and 8-Bit Bus Mode CMiser = On and 16-Bit Bus Mode CMiser = Off
SRAM Access AC Adder
CMOS inputs: GND 0.3 V or VCC 0.3V. TTL inputs: VIL 0.8 V, VIH 2.0 V. I OUT = 0 mA. CSI/A19 is high and the part is in a power-down configuration mode. All other cases include CMiser = On and 16-bit bus mode and CMiser = Off and 8- or 16-bit bus mode.
38
PSD3XX Family
18.6 AC/DC DC Characteristics ZPSD3XXV (3 V devices only)
Symbol
VCC VI H VI L VOH
Parameter
Supply Voltage High-Level Input Voltage Low-Level Input Voltage Output High Voltage
Conditions
All Speeds 2.7 V < VCC > 5.5 V 2.7 V < VCC > 5.5 V IOH = 20 A, VCC = 2.7 V IOH = 1 mA, VCC = 2.7 V IOL = 20 A, VCC = 2.7 V IOL = 4 mA, VCC = 2.7 V VCC = 3.0 V VIN = VCC or GND VOUT = VCC or GND ZPLD Turbo Mode = Off, f = 0 MHz, VCC = 3.0 V
Min
2.7 .7 VCC 0.5 2.6 2.3
Typ
3
Max
5.5 VCC + .5 .3 VCC
Unit
V V V V V
2.69 2.4 0.01 0.15 1 0.1 0.45 5 1 1
V V A A A A mA/PT A mZ/MHz mA/MHz mA/MHz mA/MHz mA/MHz mA/MHz
VOL ISB
(Notes 1,4)
Output Low Voltage Standby Supply Current Input Leakage Current Output Leakage Current
ILI ILO
1 1
.1 .1 See ISB
ICC (DC)
(Note 3)
Operating Supply Current
ZPLD Turbo Mode = On, f = 0 MHz, VCC = 3.0 V EPROM, f = 0 MHz, VCC = 3.0 V
ZPLD AC Base
See Figure 15 (VCC = 3.0 V) CMiser = On and 8-Bit Bus Mode (VCC = 3.0 V)
EPROM Access AC Adder ICC (AC)
(Note 3)
SRAM Access AC Adder
bs O
NOTES: 1. 2. 3. 4. 5.
let o
CMOS inputs: GND 0.3 V or VCC 0.3V. TTL inputs: VIL 0.8 V, VIH 2.0 V. I OUT = 0 mA. CSI/A19 is high and the part is in a power-down configuration mode. All other cases include CMiser = On and 16-bit bus mode and CMiser = Off and 8- or 16-bit bus mode.
Pr e
du o
(s) ct
All Other Cases (Note 5) (VCC = 3.0 V) CMiser = On and 8-Bit Bus Mode (VCC = 3.0 V) CMiser = On and 16-Bit Bus Mode (VCC = 3.0 V)
so Ob -
te le
ro P
uc d
0.17 0 See Fig. 15 0.4 0.9 0.7 1 1.9
s) t(
0 0.5 1 1.7 1.4 2 3.8
0.35
CMiser = Off (VCC = 3.0 V)
39
PSD3XX Family
18.7 Timing Parameters PSD3XX/ZPSD3XX (All 5 V devices)
-70
Symbol
T1 T2 T3 T4 T5 T6 T7 T8
-90*
Min
20 5 8 0 80 70 80 20 100 90 100 32
-15
Min
40 12 10 0 160 150 160 55
Parameter
ALE or AS Pulse Width Address Set-up Time Address Hold Time Leading Edge of Read to Data Active ALE Valid to Data Valid Address Valid to Data Valid CSI Active to Data Valid Leading Edge of Read to Data Valid Leading Edge of Read to Data Valid in 8031-Based Architecture Operating with PSEN and RD in Separate Mode Read Data Hold Time Trailing Edge of Read to Data High-Z Trailing Edge of ALE or AS to Leading Edge of Write RD, E, PSEN, or DS Pulse Width WR Pulse Width Trailing Edge of Write or Read to Leading Edge of ALE or AS Address Valid to Trailing Edge of Write CSI Active to Trailing Edge of Write Write Data Set-up Time Write Data Hold Time Port to Data Out Valid Propagation Delay Port Input Hold Time Trailing Edge of Write to Port Output Valid ADi1 or Control to CSOi2 Valid ADi1 or Control to CSOi2 Invalid
Min
18 5 7 0
Max
Max
Max
CMiser Turbo On = Off = Add Add
0 0 0 0 10 10 10 0 0 0 0 0 0 0 0 0
Unit
ns ns ns ns ns ns ns ns
T8A
32
32
55
T9 T10 T11 T12 T12A T13 T14 T15 T16 T17 T18
0 20 0 35 18 5
0
32 0
T19 T20
bs O
let o
Pr e
du o
(s) ct
70 80 18 5
so Ob 40 20 5 90 100 20 5 25
eP let
0 0 60 35 5 150 160 30 10
od r
35
uc
0 0 0 0 0 0 0 0 0 0 0
s) t(
0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 10
ns
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
30 0 0 40 6 5 25 25 6 4
35
0 0
0 30 6 5 20 20
50 35 35
0 0 0
T21 T22
*-90 speed available only on Industrial Temperature versions.
40
PSD3XX Family
18.7 Timing Parameters PSD3XX/ZPSD3XX (All 5 V devices)
-70
Symbol Parameter
Track Mode Address Propagation Delay: CSADOUT1 Already True Latched Address Outputs, Port A Track Mode Address Propagation Delay: CSADOUT1 Becomes True During ALE or AS Track Mode Trailing Edge of ALE or AS to Address High-Z Track Mode Read Propagation Delay Track Mode Read Hold Time Track Mode Write Cycle, Data Propagation Delay Track Mode Write Cycle, Write to Data Propagation Delay Hold Time of Port A Valid During Write CSOi2 Trailing Edge CSI Active to CSOi2 Active CSI Inactive to CSOi2 Inactive Direct PAD Input3 as Hold Time 6 2 8 5
(cont.)
-90*
Min Max
22
-15
Min Max
28
Min
Max
22
CMiser Turbo On = Off = Add Add
0 0
Unit
ns
T23
22
22
28
0
0
T23A
33
33
50
0
10
ns
T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36
NOTES:
30 27 29 18 30 8 2 11
32 29 29 20 11
35 35 29
0
0 0 0 0 10 0 0 0 0 0 0 0 0
ns ns ns ns ns ns ns ns ns ns ns ns ns
8 0
R/W Active to E or DS Start E or DS End to R/W
AS Inactive to E high
bs O
1. ADi = any address line. 2. CSOi = any of the chip-select output signals coming through Port B (CS0CS7) or through Port C (CS8CS10). 3. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or R/W, transparent PC0PC2, ALE (or AS). 4. Control signals RD/E/DS or WR or R/W.
let o
Address to Leading Edge of Write
ro P e
du
ct
(s)
so Ob 37 9 37 9 10 20 20 0 20
Pr te le
30 9 2 40 40 9 9 12 30 30 0 25
od
30 40
uc
s) t(
0 0 0 0 0
50 50
0 0 0 0 0 0 0
18 18 0 18
*-90 speed available only on Industrial Temperature versions.
41
PSD3XX Family
18.8 Timing Parameters ZPSD3XXV (3 V devices only)
-15*
Symbol
T1 T2 T3 T4 T5 T6 T7 T8
-20
Min
50 15 15 0
-25
Min
60 20 20 0
Parameter
ALE or AS Pulse Width Address Set-up Time Address Hold Time Leading Edge of Read to Data Active ALE Valid to Data Valid Address Valid to Data Valid CSI Active to Data Valid Leading Edge of Read to Data Valid Leading Edge of Read to Data Valid in 8031-Based Architecture Operating with PSEN and RD in Separate Mode Read Data Hold Time Trailing Edge of Read to Data High-Z Trailing Edge of ALE or AS to Leading Edge of Write RD, E, PSEN, or DS Pulse Width WR Pulse Width Trailing Edge of Write or Read to Leading Edge of ALE or AS Address Valid to Trailing Edge of Write CSI Active to Trailing Edge of Write Write Data Set-up Time Write Data Hold Time Port to Data Out Valid Propagation Delay Port Input Hold Time Trailing Edge of Write to Port Output Valid ADi1 or Control to CSOi2 Valid ADi1 or Control to CSOi2 Invalid
Min
40 12 10 0
Max
Max
Max
CMiser Turbo On = Off = Add Add
0 0 0 0 0 0 0 0 0 0 0 0
Unit
ns ns ns ns ns ns ns ns
170 150 160 45
200 200 200 50
250 250 250 60
20 20 20 0
T8A
65
70
80
T9 T10 T11 T12 T12A T13 T14 T15 T16 T17 T18
0 45 0 60 35 5
0
50 0
T19 T20
bs O
let o
Pr e
du o
(s) ct
150 160 30 10
so Ob 75 45 5 200 200 40 12 45
eP let
0 0 85 55 5 250 250 50 15
od r
uc
0 0 0 0 0 0 0 0 0 0 0
s) t(
0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20
ns
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
55
50 0 0 60 5 4 55 55 5 4
60
0 0
0 50 6 4 50 50
70 60 60
0 0 0
T21 T22
*-15 speed available only on ZPSD311V.
42
PSD3XX Family
18.8 Timing Parameters ZPSD3XXV (3 V devices only) (cont.)
-15*
Symbol Parameter
Track Mode Address Propagation Delay: CSADOUT1 Already True Latched Address Outputs, Port A Track Mode Address Propagation Delay: CSADOUT1 Becomes True During ALE or AS Track Mode Trailing Edge of ALE or AS to Address High-Z Track Mode Read Propagation Delay Track Mode Read Hold Time Track Mode Write Cycle, Data Propagation Delay Track Mode Write Cycle, Write to Data Propagation Delay Hold Time of Port A Valid During Write CSOi2 Trailing Edge CSI Active to CSOi2 Active CSI Inactive to CSOi2 Inactive Direct PAD Input 3 as Hold Time 8 2 9 10
-20
Min Max
60
-25
Min Max
60
Min
Max
50
CMiser Turbo On = Off = Add Add
0 0
Unit
ns
T23
50
60
60
0
0
T23A
70
80
90
0
20
ns
T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36
NOTES:
50 45 70 45 65 8 3 10
60 55 70 55 10
60 60 70
0
0 0 0 0 20 0 0 0 0 0 0 0 0
ns ns ns ns ns ns ns ns ns ns ns ns ns
9 0
R/W Active to E or DS Start E or DS End to R/W
AS Inactive to E high
bs O
1. ADi = any address line. 2. CSOi = any of the chip-select output signals coming through Port B (CS0CS7) or through Port C (CS8CS10). 3. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or R/W, transparent PC0PC2, ALE (or AS). 4. Control signals RD/E/DS or WR or R/W.
let o
Address to Leading Edge of Write
ro P e
du
ct
(s)
so Ob 70 9 70 9 0 40 40 0 35
Pr te le
75 8 3 80 80 9 9 0 50 50 0 40
od
60 80
uc
s) t(
0 0 0 0 0
90 90
0 0 0 0 0 0 0
30 30 0 30
*-15 speed available only on ZPSD311V.
43
PSD3XX Family
18.9 Timing Diagrams for all PSD3XX Parts
Figure 20. Timing of 8-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X1)
READ CYCLE 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 32 STABLE INPUT 6 Multiplexed (2) Inputs 6 A0/AD0A7/AD7 Active High ALE Active Low ALE ADDRESS A 2 1 3 10 DATA VALID 9 2 14 ADDRESS B 3 16 DATA IN STABLE INPUT 14 WRITE CYCLE 32
17
1 11 4 8 12 13
RD/E as RD 5 BHE/PSEN as PSEN WR/VPP or RW as WR Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs
bs O
let o
23
ro P e
du
18
(s) ct
INPUT INPUT
Ob 19
so
te le
ro P
uc d
s) t(
36
12A
13
20 OUTPUT
OUTPUT 23
ADDRESS A
ADDRESS B
See referenced notes on page 64.
44
PSD3XX Family
Figure 21. Timing of 8-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X2/3X3)
READ CYCLE 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 32 STABLE INPUT 6 Multiplexed (2) Inputs 6 A0/AD0A7/AD7 Active High ALE Active Low ALE ADDRESS A 2 1 3 DATA VALID 9 2 10 14 ADDRESS B 3 DATA IN STABLE INPUT 14 WRITE CYCLE 32
16 1 4 8 12 11
13
RD/E/DS as RD 5 BHE/PSEN as PSEN WR/VPP or RW as WR Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs
bs O
let o
od Pr e
23
uc
(s) t
18
so Ob 19 INPUT INPUT
te le
ro P
36
uc d
s) t(
17
12A
13
20 OUTPUT
OUTPUT 23
ADDRESS A
ADDRESS B
See referenced notes on page 64
45
PSD3XX Family
Figure 22. Timing of 8-Bit Multiplexed Address/Data Bus Using R/W, E or R/W, DS (PSD3X1)
READ CYCLE 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 32 STABLE INPUT 6 Multiplexed (2) Inputs 6 A0/AD0A7/AD7 Active High AS Active Low AS ADDRESS A 2 1 3 10 DATA VALID 9 2 14 ADDRESS B 3 16 1 17 DATA IN STABLE INPUT 14 WRITE CYCLE 32
35 4 13 8 5 33 12 34
35
RD/E as E
WR/VPP or R/W as R/W 18 Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs
bs O
let o
23
Pr e
du o
(s) ct
Ob 19
so
te le
36
ro P
33
uc d
12
s) t(
34
13
20 OUTPUT
INPUT
INPUT 23
OUTPUT
ADDRESS A
ADDRESS B
See referenced notes on page 64.
46
PSD3XX Family
Figure 23. Timing of 8-Bit Multiplexed Address/Data Bus Using R/W E or R/W, DS (PSD3X2/3X3)
READ CYCLE 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 32 STABLE INPUT 6 Multiplexed (2) Inputs 6 A0/AD0A7/AD7 Active High AS Active Low AS ADDRESS A 2 1 3 10 DATA VALID 9 2 14 ADDRESS B 3 DATA IN STABLE INPUT 14 WRITE CYCLE 32
16 1
35 4 13 8 5 34
RD/E/DS as E
RD/E/DS as DS 33 WR/VPP or R/W as R/W Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin
12
O
bs
Any of PA0-PA7 Pins as Address Outputs
let o
ro P e
23
du
(s) ct
18
so Ob 19 INPUT INPUT
te le
ro P
35 36
uc d
33
s) t(
17
34
12
13
20 OUTPUT
OUTPUT 23
ADDRESS A
ADDRESS B
See referenced notes on page 64.
47
PSD3XX Family
Figure 24. Timing of 16-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X1)
READ CYCLE 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 32 STABLE INPUT 6 Multiplexed (2) Inputs 6 10 14 STABLE INPUT 14 WRITE CYCLE 32
BHE/PSEN as BHE A0/AD0A15/AD15 Active High ALE Active Low ALE 5 12 RD/E as RD
ADDRESS A 2 1 3 4
DATA VALID 9 2
ADDRESS B 3
1 8
WR/VPP or R/W as WR Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs
bs O
let o
23
Pr e
du o
18
(s) ct
INPUT INPUT
so Ob 19
13
eP let
11
ro
uc d
16
17
s) t(
DATA IN
36
13 12A
20
OUTPUT
OUTPUT 23
ADDRESS A
ADDRESS B
See referenced notes on page 64.
48
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