STA003
MPEG 2.5 LAYER III AUDIO DECODER
CHIP MPEG2 LAYER 3 DECODER SUPPORTING:
SINGLE
All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) except 44.1KHz Audio All features specified for Layer III 2 channels in ISO/IEC13818-3.2 (MPEG 2 Audio) except 22.05KHz Audio Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5 except 11.025KHz Audio LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO)
DECODES
SO 28
EXTERNAL INPUT CLOCK OR BUILT-IN XTAL OSCILLATOR
14.72MHz
THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5: 48, 32, 24, 16, 12, 8 KHz
SUPPORTING ACCEPTS
APPLICATIONS STARMAN SATELLITE RADIO RECEIVER
MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 128 Kbit/s
DIGITAL DIGITAL SERIAL
VOLUME CONTROL
BASS & TREBLE CONTROL
BITSTREAM INPUT INTERFACE
ANCILLARY
DATA EXTRACTION VIA I2C INTERFACE.
PCM OUTPUT INTERFACE (I2S AND OTHER FORMATS)
SERIAL
bs O
CRC I
FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION
PLL
POWER DATA ELABORATION FOR POWER CONSUMPTION OPTIMISATION
LOW
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DES CRIPTION
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The STA003T is a fully integrated high flexibility MPEG Layer III Audio Decoder, capable of decoding Layer III compressed elementary streams, as specified in MPEG 1 and MPEG 2 ISO standards. The device decodes also elementary streams compressed by using low sampling rates, as specified by MPEG 2.5. STA003T receives the input data through a Serial Input Interface. The decoded signal is a stereo, mono, or dual channel digital output that can be sent directly to a D/A converter, by the PCM Output Interface. This interface is software programmable to adapt the STA003T digital output to the most common DACs architectures used on the market. The functional STA003T chip partitioning is described in fig. 1.
CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE INDICATORS
2
C CONTROL BUS POWER 3.3V CMOS TECHNOLOGY
LOW
August 2009
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Figure 1. BLOCK DIAGRAM: MPEG 2.5 Layer III Decoder Hardware Partitioning.
RESET 26
SDA 3
SCL 4
I2C CONTROL
SDI SCKR BIT_EN
5 6 7 SERIAL INPUT INTERFACE MPEG 2.5 LAYER III DECODER CORE CHANNEL CONFIG. & VOLUME CONTROL OUTPUT BUFFER PCM OUTPUT INTERFACE
9 10 11
SDO SCKT LRCKT
BUFFER
PARSER
SYSTEM & AUDIO CLOCKS
TEST INTERFACE
8 SRC_INT
28 VDD_5/CLK_OUT
21 XTI
20 XTO
12 OCLK
24 TESTEN
25 SCANEN
Figure 2. PIN CONNECTION
VDD_1 VSS_1 SDA SCL SDI
1 2
bs O
let o
Pr e
SRC_INT SDO
du o
SCKR BIT_EN SCKT LRCKT OCLK VSS_2 VDD_2
(s) ct
4 5 6 7 8 9 10 11 12 13 14
3
so Ob 28 27 26 25 24 23 22 21 20 19 18 17 16 15
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D99AU1005
VDD_5/CLK_OUT VSS_5 RESET
SCANEN TESTEN VDD_4 VSS_4 XTI XTO FILT PVSS PVDD VDD_3 VSS_3
D99AU1003
THERMAL DATA
Symbol Rth j-amb Parameter Thermal resistance junction to Ambient Value 85 Unit C/W
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PIN DESCRIPTION
Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name VDD _1 VSS_1 SDA SCL S DI SCKR B IT_E N SRC_INT SDO SCKT LRCLKT OCLK VSS_2 VDD _ 2 VSS_3 VDD _ 3 PVDD PVSS FILT XTO X TI VSS_4 VDD _ 4 TESTEN S CANEN O O I I/O I I I I I O O O I/O Type Ground I2C Serial Data + Acknowledge I2C Serial Clock Receiver Serial Data Receiver Serial Clock Bit Enable Interrupt Line For S.R. Control Transmitter Serial Data (PCM Data) Transmitter Serial Clock Transmitter Left/Right Clock Oversampling Clock for DAC Ground Supply Voltage Ground Supply Voltage PLL Power PLL Ground CMOS Input Pad Buffer CMOS 4mA Output Drive CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up CMOS Input Pad Buffer CMOS 4mA Output Drive CMOS 4mA Output Drive CMOS 4mA Output Drive CMOS Input Pad Buffer CMOS 4mA Output Drive Function Supply Voltage PAD Description
PLL Filter Ext. Capacitor Conn. Cr ystal Output Cr ystal Input (Clock Input)
bs O
VDD Vi VO Tstg Toper
Note: In functional mode TESTEN must be connected to VDD, SCANEN to ground.
let o
Pr e
RESE T VSS_5 VDD_5/ CLK_OU T
du o
I I I
(s) ct
Ground Ground
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CMOS 4mA Output Drive Specific Level Input Pad (see paragraph 2.1)
Supply Voltage Test Enable CMOS Input Pad Buffer with pull up CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up CMOS 4mA Output Drive
Scan Enable System Reset Power/14.72MHz Buffered Output Clock
ABSOLUTE MAXIMUM RATINGS
Symbol Power Supply Voltage on Input pins Voltage on output pins Storage Temperature Operative ambient temp Parameter Value -0.3 to 4 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -40 to +150 -20 to +85 Unit V V V C C
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1.0 ELECTRICAL CHARACTERISTICS VDD = 3.3V 0.3V; TAMB = 0 TO 70C; RG = 50 UNLESS OTHERWISE SPECIFIED DC OPERATING CONDITIONS
Symbol VDD Tj Power Supply Voltage Operating Junction Temperature Parameter Value 2.7 to 3.6V -20 to 125C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol IIL IIH Vesd Parameter Low Level Input Current Without pull-up device High Level Input Current Without pull-up device Electrostatic Protection Test Condition Vi = 0V Vi = V DD Leakage < 1A Min. -10 -10 2000 Typ. M ax. 10 10 Unit A A V Note 1 1 2
Note: 1. The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin. 2. Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol VI L VIH Vol Voh Parameter Low level input voltage High level input voltage Low level Input Voltage High level Output Voltage Iol = Xma Test Condition Min. Typ.
0.8*V DD
Note: 1. Takes into account 200mV voltage drop in both supply lines. 2. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
PULL_UP CHARACTERISTICS
Symbol
Ipu R
Parameter Pull-up current
pu
Equivalent Pull-up Resistance
Notes: 1. Min. condition: VDD = 2.7V, 125C Min process Max. condition: VDD = 3.6V, -20C Max.
bs O
PD
POWER DISSIPATION
Symbol Parameter Test Condition Sampling_freq 24kHz Sampling_freq 24kHz Sampling_freq 24kHz Min. Typ. 120 125 135 Max. Unit mW mW mW Note
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Min. -25
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V V
Unit
Note
0.2*VDD
0. 4
V V
1 ,2 1,2
0.85*VDD
Test Condition
Typ. -66 50
M ax. -125
Unit A k
Note 1
Vi = 0V; pin numbers 7, 24 and 26
Power Dissipation @ VDD = 3V
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STA003
Figure 3. Test Circuit
VDD_5/CLK_OUT VDD 100nF VSS VDD 100nF VSS VDD 100nF VSS VDD 100nF VSS VDD 4.7F PVDD 4.7F PVDD VSS PVSS PVSS
D99AU1004
28 1
3 4 9 10 11 12
SDA SCL SDO SCKT LRCKT OCLK SDI SCKR BIT_EN SCR_INT XTI XTO 10K
2 14
13 16
5 6 7 8 21 20
15 23
22 17 100nF 18 27 26 RESET 25 SCANEN 24
19
TESTEN 470pF
1K 4.7nF
Test Load Circuit
VDD IOL
Test Load
Output
OUTPUT
VREF CL IOH
2.0 FUNCTIONAL DESCRIPTION 2.1 Clock Signal
The STA003T input clock is derivated from an external ource or from a 14.72 MHz crystal.
bs O
XTI is an input Pad with specific levels.
Symbol VIL Parameter Test Condition Min. Typ. Max. VDD-1.8 VDD-0.8 Unit V V Low Level Input Voltage High Level Input Voltage
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(s) ct
D98AU967
Ob SDA
so
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IOL
5mA 100A
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IOH
100A
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CL
100pF 100pF
VREF
3.6V 1.5V
Other Outputs
VI H
CMOS compatibility The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD = 3V TTL min high level = 2.0V while XTI min high level = 2.2V)
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Figure 4. MPEG Decoder Interfaces.
P
XTO MASTER CLK XTI SCL SDA FILT IIC
SRC-INT SDI CHANNEL DECODER SCKR BIT_EN
PLL
IIC SDO
MPEG DECODER
SERIAL AUDIO INTERFACE RX TX
SCKT LRCKT
DAC
OCLK
D97AU665A
Figure 5. Serial Input Interface Clocks
SDI DATA IGNORED
SCKR
SCKR
BIT_EN
2.2 Serial Input Interface
STA003T receives the input data thought the Serial Input Interface (Fig.4). It is a serial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Serial Clock). The interface can be configured to receive data sampled on both rising and falling edge of the SCKR clock.The BIT_EN pin, when set to low, forces the bitstream input interface to ignore the incoming data. The possible configurations are described in Fig. 5. The bitstream must be sent MSB first to STA003T.
bs O
2.3 PLL & Clocks Generation System The STA003T has a clock generation system that is used by the device core to adjust the core speed, for power saving, adapting the processing speed to the needs of the decoded audio program. The clocks generation system is even used to generate all the PCM output interface clocks: SCKT, LRCKT, and OCLK. The block diagram in Fig. 6 is a description of STA003T clocks generation system. The input of STA003T clocks system is a 14.72MHz input clock. Internally it is composed by a PLL loop, and the VCO output is fed into a divider stage, used to program the Core speed and the PCM interface clocks. Several registers are programmed by the Layer III decoder core, and by the user, when a specific interface configuration is required. The PLL can be programmed by a set of registers, as described in the I2C Registers section, The partic-
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D98AU968
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SCLK_POL=0
SCLK_POL=2
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STA003
ularity of the STA003T clocks generation system is the possibility to modify the Audio Sampling Frequency (LRCKT) in steps of few ppm to compensate dynamically the audio sampling rate offset between the receiver and the broadcasting station. The compensation is done by the STA003T core without requiring interaction with the application controller and the sampling rate compensation produces a jittering effect outside the audible range. The device implements a sampling rate offset control receiving by STA002 (WorldSpace Channel Decoder) a dedicated signal every decoded Broadcast Channel Frame (432ms). This signal is used as interrupt signal inside STA003T. Within a WorldSpace Broadcast Frame, there are a fixed number of PCM samples, depending on the nominal audio sampling rate (Fig. 7). Using this information, with the SRC_INT signal as external timer source, STA003T performs the compensation of the audio sampling rate. The sampling rate control is done by the STA003T core, by setting PLLFRAC internal register. The PLLFRAC value is updated, in steps of few ppms, by Update PLLFRAC signal. Figure 6. PLL and Clocks Generation System
Figure 7. WorldSpace BC Framing
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STA003
2.4 PCM Output Interface The decoded audio data are output in serial PCM format. The interface consists of the following signals: S DO S CK T LRCLK PCM Serial Data Output PCM Serial Clock Output Left/Right Channel Selection Clock
The output samples precision is selectable from 16 to 24 bits/word, by setting the output precision (16, 18, 20 and 24 bits) with PCMCONF register. Data can be output either with the most significant bit first (MS) or least significant bit first (LS), selected by writing into a flag of the PCMCONF register. Figure 8 gives a description of the STA003T PCM Output Formats. The sample rates set decoded by STA003T is described in Table 1. Figure 8. PCM Output Formats
Table 1. MPEG Sampling Rates (KHz)
M PEG 1 48 32
2.5 STA003T Decoding States
bs O
There are three different decoder states: Idle, Init, and Decode. Commands to change the decoding states are described in the STA003T I2C registers description. Idle Mode In this mode the decoder is waiting for the RUN command. This mode should be used to initialise the configuration register of the device. The DAC connected to STA003T can be initialised during this mode (set MUTE to 1).
PLAY X X M UTE 0 1 Clock State Not Running R unning PCM Output 0 0
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so Ob M PEG 2 24 16
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MPEG 2.5 12 8
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Init Mode "PLAY" and "MUTE" changes are ignored in this mode. The internal state of the decoder will be updated only when the decoder changes from the state "init" to the state "decode". The "init" phase ends when the first decoded samples are at the output stage of the device. Decode Mode This mode is completely described by the following table:
PLAY 0 0 1 1 MUTE 0 1 0 1 Clock State Not Running Running Running Running PCM Output 0 0 Decoded Samples 0 Decoding No No Yes Yes
DEVICE OPERATION 3.0 I2C BUS SPECIFICATION
The STA003T supports the I2C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the others as the slave. The master will always start the transfer and provides the serial clock for synchronisation. The STA003T is always a slave device in all its communications. 3.1 COMMUNICATION PROTOCOL 3.1.0 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transitions while the clock is high are used to identify START or STOP condition. 3.1.1 Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 3.1.2 Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communications between STA003T and the bus master. 3.1.3 Acknowledge bit
bs O
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data. 3.1.4 Data input During the data input the STA003T samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock and the data can change only when the SCL line is low. 3.2 DEVICE ADDRESSING To start communication between the master and the STA003T, the master must initiate with a start condition. Following this the master sends onto the SDA line 8 bits (MSB first) corresponding to the device
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STA003
select address and read or write mode. The 7 most significant bits are the device address identifier, corresponding to the I2C bus definition. For the STA003T these are fixed as 1000011. The 8th bit (LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in write mode). After a START condition the STA003T identifies on the bus the device address and if match is found, it acknowledges the identification on SDA bus during the 9th bit time. The following byte after the device identification byte are the internal space address. 3.3 WRITE OPERATION (see fig. 9) Following a START condition the master sends a device select code with the RW bit set to 0. The STA003T acknowledges this and waits for the byte of internal address. After receiving the internal bytes address the STA003T again responds with an acknowledge. 3.3.1 Byte write In the byte write mode the master sends one data byte and this is acknowledged by STA003T. The master then terminates the transfer by generating a STOP condition. 3.3.2 Multibyte write
The multibyte write mode can start from any internal address. The transfer is terminated by the master generating a STOP condition. Figure 9. Write Mode Sequence
ACK BYTE WRITE START DEV-ADDR SUB-ADDR ACK DATA IN ACK
RW
ACK MULTIBYTE WRITE START DEV-ADDR SUB-ADDR
ACK
RW
Figure 10. Read Mode Sequence
ACK CURRENT ADDRESS READ START
DEV-ADDR
DATA
RW ACK
RANDOM ADDRESS READ START
DEV-ADDR
SEQUENTIAL CURRENT READ
DEV-ADDR
O
3.4 READ OPERATION (see Fig. 10) 3.4.1 Current byte address read The STA003T has an internal byte address counter. Each time a byte is written or read, this counter, is incremented .
bs
SEQUENTIAL RANDOM READ
let o
START START
ro P e
RW RW= ACK HIGH ACK RW
du
SUB-ADDR DATA SUB-ADDR
(s) ct
NO ACK STOP ACK START ACK DATA ACK
so Ob DATA IN
ACK DEV-ADDR DATA RW ACK DATA
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ACK
STOP
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D98AU825B
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ACK DATA IN
STOP
NO ACK
STOP NO ACK
STOP ACK DEV-ADDR DATA ACK DATA ACK DATA NO ACK
DEV-ADDR
START
RW
D98AU826A
STOP
For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1. The STA003T acknowledges this and outputs the byte addressed by the internal byte address counter.
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The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. 3.4.2 Sequential address read This mode can be initiated with either a current address read or a random address read. However in this case the master does acknowledge the data byte output and the STA003T continues to output the next byte in sequence. To terminate the stream of bytes the master does not acknowledge the last received byte, but terminates the transfer with a STOP condition. The output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. 4.0 I2C REGISTERS The following table gives a description of the MPEG Source Decoder (STA003T) register list. The first column (HEX_COD) is the hexadecimal code for the sub-address. The second column (DEC_COD) is the decimal code. The third column (DESCRIPTION) is the description of the information contained in the register. The fourth column (RESET) inidicate the reset value if any. When no reset value is specifyed, the default is "undefined". The fifth column (R/W) is the flag to distinguish register "read only" and "read and write", and the useful size of the register itself. Each register is 8 bit wide. The master shall operate reading or writing on 8 bits only. I2C REGISTER
H EX_COD 0x00 0x01 0x05 0x06 0x07 0x0B 0x0C 0x0D 0x0F 0x10 DEC_COD 0 1 5 6 7 11 12 VER SIO N I DENT PLLCTL [7:0] PLLCTL_M PLLCTL_N DESCRIPTIO N
bs O
0x13 0x14 0x16
let o
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13 15 16 19 20 22 24 64 65 66
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reser ved PLAY M UT E
reser ved
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RE SET
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0xAC 0x21 0x0C 0x00
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R/W R (8) R (8)
R/W (8) R/W (8) R/W (8)
SCLK _POL
0x04 0x00 0x00 0x01 0x00 0x00
R/W (8) R (8) W (8) R/W(8) R/W(8) R/W(8)
ERROR_CODE SO FT_RESET
CMD_INTERRUPT reser ved SYNCSTATUS ANC COUNT_L ANC COUNT_H
0x18 0x40 0x41 0x42
0x00 0x00 0x00
R (8) R (8) R (8)
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I2C REGISTER (continued)
0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x54 0x55 0x56 0x59 0x5A 0x5B 0x5C 0x5D 0x61 0x63 0x64 0x65 0x67 0x68 0x69 0x6A 0x71 0x72 67 68 69 70 71 72 73 84 85 86 89 90 91 92 93 97 99 100 101 103 104 105 106 HEA D_H[23:16] HEAD_M[15:8] HEA D_L[7:0] DLA DLB DR A DR B PCM DIV IDER PCM CONF PCMCROSS ANC_DATA_1 [7:0] ANC_DATA_2 [15:8] ANC_DATA_3 [23:16] ANC_DATA_4 [31:24] ANC_DATA_5 [39:32] MFSDF (X) DAC_CLK_MODE PLLFRAC_L PLLFRAC_H FRAM E_CNT_L 0x00 0x00 0x00 0x00 0xFF 0x00 0xFF 0x01 0x21 0x00 0x00 0x00 0x00 0x00 R(8) R(8) R(8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8)
FRAM E_CNT_M FRAM E_CNT_H
0x77
O
bs
0x78 0x79
let o
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113 114 119 120 121 122 123 124 125
AVERAGE_BITRATE SO FTVERSION RUN TREBLE_FREQUENCY_LOW
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(s)
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0x00
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R (8) R (8) R (8) R (8) R (8)
0x0F 0x00
R/W (8) R/W (8) R/W (8) R/W (8) R (8) R (8) R (8) R (8) R (8)
0xC8 0x59 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8)
TREBLE_FREQUENCY_HIGH BASS_FREQUENCY_LOW BASS_FREQUENCY_HIGH TREB LE_ENHANC E BAS S_ENHANC E TONE_ATTEN
0x7A 0x7B 0x7C 0x7D
Note: 1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information. 2) RESERVED: register used for production test only, or for future use.
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4.1 STA003T REGISTER DESCRIPTION The STA003T device includes 128 I2C registers. In this document, only the user-oriented registers are described. The undocumented registers are reserved. These registers must never be accessed (in Read or in Write mode). The Read- Only registers must never be written. The following table describes the meaning of the abbreviations used in the I2C registers description:
Symbol NA U ND NC RO WO R/W R/WS Comment Not Applicable Undefined No Charge Read Only Write Only Read and Write Read, Write in specific mode
VERSION Address: 0x00 Type: RO
MSB b7 V8 b6 V7 b5 V6 b4 V5 b3 V4 b2
The VERSION register is read-only and it is used to identify the IC on the application board. IDENT Address: 0x01 Type: RO Software Reset: 0xAC Hardware Reset: 0xAC
MSB b7 1
IDENT is a read-only register and is used to identify the IC on an application board. IDENT always has the value "0xAC"
bs O
PLLCTL
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LSB b0 V1
V2
LSB b2 1 b1 0 b0 0
Address: 0x05 Type: R/W Software Reset: 0x21 Hardware Reset: 0x21
MSB b7 XTO_BUF b6 XTODIS b5 O CLKEN b4 SY S2OCLK b3 PPLDIS b2 XTI2DSPCLK b1 XTI2OCLK LSB b0 UPD_FRAC
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UPD_FRAC: when is set to 1, updates FRAC in the switching circuit. It is set to 1 after autoboot. XTI2OCLK: when is set to 1, uses the XTI as input of the divider X instead of VCO output. It is set to 0 on HW reset. XTI2DSPCLK: when is set to 1, uses the XTI as nput of the divider S instead of VCO output. It is set to 0 on HW reset. PLLDIS: when set to 1, the VCO output is disabled. It is set to 0 on HW reset. SYS2OCLK: when is set to 1, the OCLK frequency is equal to the system frequency. It is useful for testing. It is set to 0 on HW reset. OCLKEN: when is set to 1, the OCLK pad is enable as output pad. It is set to 1 on HW reset. XTODIS: when is set to 1, the XTO pad is disabled. It is set to 0 on HW reset. XTO_BUF: when this bit is set, the pin nr. 28 (VDD_5/CLK_OUT) is enabled as buffered (4mA) aster clock output (CLK_OUT). It is set to 0 after autoboot. PLLCTL_M Address: 0x06 Type: R/W Software Reset: 0x0C Hardware Reset: 0x0C PLLCTL_N Address: 0x07 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
The M and N registers are used to configure the STA003T PLL by DSP embedded software. M and N registers are R/W type but they are completely controlled, on STA003T, by DSP software. S CKL_POL Address: 0x0D Type: R/W Software Reset: 0x04
Hardware Reset: 0x04
MS B
bs O
X
b7
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X
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LSB b3 X b2 0 1 b1 0 0 b0 0 0 (1) (2)
b6
X = don't care SCKL_POL is used to select the working polarity of the Input Serial Clock (SCKR). (1) If SCKL_POL is set to 0x00, the data (SDI) are sent with the falling edge of SCKR and sampled on the rising edge. (2) If SCKL_POL is set to 0x04, the data (SDI) are sent with the rising edge of SCKR and sampled on the falling edge.
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E RROR_CODE Address: 0x0F Type: RO Software Reset: 0x00 Hardware Reset: 0x00
MS B b7 X b6 X b5 X b4 X b3 0 0 0 b2 0 0 0 b1 0 0 1 LSB b0 0 1 0 (1) (2) (3)
X = don't care ERROR_CODE register contains the last error occourred if any. The codes can be as follows: Code Description
Code (1) (2) (3) 0 x00 0 x01 0 x02 Description No error since the last SW or HW Reset CRC Failure DATA not available
SOFT_RESET Address: 0x10 Type: WO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X
X = don't care; 0 = normal operation; 1 = reset When this register is written, a soft reset occours. The STA003T core command register and the interrupt register are cleared. The decoder goes in to idle mode. PLAY
bs O
X
Address: 0x13 Type: R/W
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(s)
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LSB b1 X b0 0 1
Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
X = don't care; 0 = normal operation; 1 = play
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STA003
The PLAY command is handled according to the state of the decoder, as described in section 2.5. PLAY only becomes active when the decoder is in DECODE mode. MUTE Address: 0x14 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
X = don't care; 0 = normal operation; 1 = mute The MUTE command is handled according to the state of the decoder, as described in section 2.5. MUTE sets the clock running. CMD_INTERRUPT Address: 0x16 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X
X = don't care; 0 = normal operation; 1 = write into I2C/Ancillary Data
The INTERRUPT is used to give STA003T the command to write into the I2C/Ancillary Data Buffer (Registers: 0x59 ... 0x5D). Every time the Master has to extract the new buffer content (5 bytes) it writes into this register, setting it to a non-zero value. SYNCSTATUS
Address: 0x40
bs O
MSB b7 X
Type: RO
let o
Pr e
du o
(s) ct
Ob -
so
te le
b2 X
ro P
uc d
s) t(
LSB b0 0 1
b1 X
Software Reset: 0x00 Hardware Reset: 0x00
b6 X b5 X b4 X b3 X b2 X b1 SS1 0 0 1 1 LSB b0 SS0 0 1 0 1
Research of sync word Wait for Confirmation Synchronised not used
16/39
STA003
ANCCOUNT_L Address: 0x41 Type: RO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 AC7 b6 AC6 b5 AC5 b4 AC4 b3 AC3 b2 AC2 b1 AC1 LSB b0 AC0
ANCCOUNT_H Address: 0x42 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_H
MSB b7 AC15 b6 AC14 b5 AC13 b4 AC12 b3 AC11 b2
ANCCOUNT registers are logically concatenated and indicate the number of Ancillary Data bits available at every correctly decoded MPEG frame. HEAD_H[23:16]
MSB b7 X b6 X b5 X b4
x = don't care HEAD_M[15:8]
MSB b7 H15
HEAD_L[7:0]
O
bs
MSB b7
let o
od Pr e
b6 H14 b6 H6
ct u
(s)
b4
H20
so Ob b3 H19 b3 H11
eP let
AC10 b2 H18
ro
b1
uc d
s) t(
LSB b0 AC8
AC9
LSB b1 H17 b0 H16
LSB b2 H10 b1 H9 b0 H8
b5
H 13
H12
LSB b5 H5 b4 H4 b3 H3 b2 H2 b1 H1 b0 H0
H7
Address: 0x43, 0x44, 0x45 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis
17/39
STA003
Head[2] original/copy Head[3] copyrightHead [5:4] mode extension Head[7:6] mode Head[8] private bit Head[9] padding bit Head[11:10] sampling frequency index Head[15:12] bitrate index Head[16] protection bit Head[18:17] layer Head[19] ID Head[20] ID_ex The HEAD registers can be viewed as logically concatenated to store the MPEG Layer III Header content. The set of three registers is updated every time the synchronisation to the new MPEG rame is achieved . The HEAD registers can be viewed as logically concatenated to store the MPEG Layer III Header content. The set of three registers is updated every time the synchronisation to the new MPEG frame is achieved . The meaning of the flags are shown in the following tables:
IDex 0 0 1 1 ID 0 1 0 1
Layer Protection_bit Bitrate_index
bitrate index '0000' '0001' '0010'
in Layer III these two flags must be set always to "01".
It equals "1" if no redundancy has been added and "0" if redundancy has been added. indicates the bitrate (Kbit/sec) depending on the MPEG ID.
O
bs
let o
'0011' '0100' '0101' '0110' '0111' '1000' '1001' '1010' '1011' '1100' '1101' '1110' '1111'
Pr e
du o
(s) ct
so Ob ID = 1 free 32 40 48 56 64 80 96 112 128
te le
ro P
MPEG 2.5 reserved MPEG 2 MPEG 1
uc d
s) t(
ID = 0 free 8 16 24 32 40 48 56 64 80 96 112 128 not supported not supported forbidden
not supported not supported not supported not supported not supported forbidden
18/39
STA003
Sampling Frequency indicates the sampling frequency of the encoded audio signal (KHz) depending on the MPEG ID
Sampling Frequency '00' '01' '10' '11' MPEG1 not supported 48 32 reser ved M PEG2 not supported 24 16 reser ved MPEG 2.5 not supported 12 8 reser ved
Padding bit if this bit equals '1', the frame contains an additional slot to adjust the mean bitrate to the sampling frequency, otherwise this bit is set to '0'. Private bit Bit for private use. This bit will not be used in the future by ISO/IEC.Mode
Indicates the mode according to the following table. The joint stereo mode is intensity_stereo and/or ms_stereo.
mode '00' '01' '10' '11' stereo joint stereo (intensity_stereo and/or ms_stereo) dual_channel single_channel (mono) mode specified
Mode extension
These bits are used in joint stereo mode. They indicates which type of joint stereo coding method is applied. The frequency ranges, over which the intensity_stereo and ms_stereo modes are applied, are implicit in the algorithm. Copyright
If this bit is equal to '0', there is no copyright on the bitstream, '1' means copyright protected. O r igina l/C opy
This bit equals '0' if the bitstream is a copy, '1' if it is original.
bs O
let o
'00' '01' '10' '11'
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Emphasis Indicates the type of de-emphasis that shall be used. emphasis
none 50/15 microseconds reserved CCITT J,17
emphasis specified
19/39
STA003
DLA Address: 0x46 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MS B b7 DLA7 0 0 0 : 0 b6 DLA6 0 0 0 : 1 b5 DLA5 0 0 0 : 1 b4 DLA4 0 0 0 : 0 b3 DLA3 0 0 0 : 0 b2 DLA2 0 0 0 : 0 b1 DLA1 0 0 1 : 0 L SB b0 DLA0 0 1 0 : 0 OUTPUT ATTENUATION NO ATTENUATION - 1dB - 2dB : -96dB
DLA register is used to attenuate the level of audio output at the Left Channel using the butterfly shown in Fig. 11. When the register is set to 255 (0xFF), the maximum attenuation is achieved. A decimal unit correspond to an attenuation step of 1 dB. Figure 11. Volume Control and Output Setup
DSP Left Channel DLA X DLB X DRB X DRA DSP Right Channel X
+
DLB Address: 0x47 Type: R/W
Software Reset: 0xFF
MS B
O
bs
b7 DLA7 0 0 0 : 0
let o
b6 DLA6 0 0 0 : 1
ro P e
b5 DLA5 0 0 0 : 1
uc d
b4 DLA4 0 0 0 : 0
(s) t
so Ob -
te le
Output Left Channel
ro P
uc d
s) t(
+
Output Right Channel
D97AU667
L SB b3 DLA3 0 0 0 : 0 b2 DLA2 0 0 0 : 0 b1 DLA1 0 0 1 : 0 b0 DLA0 0 1 0 : 0 OUTPUT ATTENUATION NO ATTENUATION - 1dB - 2dB : -96dB
DLB register is used to re-direct the Left Channel on the Right, or to mix both the Channels. Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel.
20/39
STA003
D RA Address: 0x48 Type: R/W Software Reset: 0X00 Hardware Reset: 0X00
MS B b7 DRA7 0 0 0 : 0 b6 DRA6 0 0 0 : 1 b5 DRA5 0 0 0 : 1 b4 DRA4 0 0 0 : 0 b3 DRA3 0 0 0 : 0 b2 DRA2 0 0 0 : 0 b1 DRA1 0 0 1 : 0 L SB b0 DRA0 0 1 0 : 0 OUTPUT ATTENUATION NO ATTENUATION - 1dB - 2dB : -96dB
DRA register is used to attenuate the level of audio output at the Right Channel using the butterfly shown in Fig. 11. When the register is set to 255 (0xFF), the maximum attenuation is achieved. A decimal unit correspond to an attenuation step of 1 dB. D RB Address: 0x49 Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF
MS B b7 DRA7 0 0 0 : 0 b6 DRA6 0 0 0 : b5 DRA5 0 0 0 b4 DRA4 0 b3 DRA3
DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels. Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel.
bs O
7
PCMDIVIDER Type: RW
let o
1
Pr e
: 1
du o
0 0 : 0
ct
(s)
0 0 0 : 0
so Ob b2 b1 DRA2 0 0 0 : 0 DRA1 0 0 1 : 0
te le
L SB b0 DRA0 0 1 0 : 0
ro P
uc d
s) t(
OUTPUT ATTENUATION NO ATTENUATION - 1dB - 2dB : -96dB
Address: 0x54 Software Reset: 0x01 Hardware Reset: 0x01
6 PD6 5 P D5 4 PD 4 3 PD3 2 PD2 1 PD1 0 PD0
PD7
21/39
STA003
PCMDIVIDER is used to set the frequency ratio between the OCLK (Oversampling Clock for DACs), and the SCKT (Serial Audio Transmitter Clock). The relation is the following:
O C L --- _freq S C K T _freq = ----------------------------K---------------------------2(1 + PCMDIVIDER)
The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression: 1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation) 2) OCLK_ Freq = 2 * (1+PCMDIVIDER) * 32* LRCKT_Freq (when 16 bit PCM mode is used) 3) OCLK_ Freq = 2 * (1+PCMDIVIDER) * 64* LRCKT_Freq (when 32 bit PCM mode is used) 4) PCMDIVIDER = (O_FAC/64) - 1 in 16 bit mode 5) PCMDIVIDER = (O_FAC/128) - 1 in 32 bit mode Example for setting:
M SB b7 PD7 0 0 0 0 0 0 b6 PD6 0 0 0 0 0 0 b5 PD5 0 0 0 0 0 0 b4 PD4 0 0 0 0 0 0 b3 PD3 0 0 0 0 0 0 b2 PD2 1 1 0 0 0 0 b1 PD1 1 0 1 1 1 0 L SB b0 PD0 1 1 1 1 0 1 Descr iption
16 bit mode 16 bit mode 16 bit mode 32 bit mode 32 bit mode 32 bit mode
for 16 bit PCM Mode O_FAC = 512 ; PCMDIVIDER = 7 O_FAC = 256 ; PCMDIVIDER = 3 O_FAC = 384 ; PCMDIVIDER = 5 for 32 bit PCM Mode
O_FAC = 512 ; PCMDIVIDER = 3
bs O
O_FAC = 256 ; PCMDIVIDER = 1 O_FAC = 384 ; PCMDIVIDER = 2
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
512 x Fs 384 x Fs 256 x Fs 512 x Fs 384 x Fs 256 x Fs
22/39
STA003
P CM CO NF Address: 0x55 Type: R/W Software Reset: 0x21 Hardware Reset: 0x21
M SB b7 X X X X X X X X X X X X X X X b6 O RD 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 b5 DIF b4 INV b3 FOR b2 b1 L SB b0 Descr iption
SCL PREC [1] PREC ([0] PCM order the LS bit is transmitted First PCM order the MS bit is transmitted First The word is right padded The word is left padded LRCKT Polarity compliant to I2S format LRCKT Polarity inverted I2S format Different formats
Data are sent on the rising edge of SCKT Data are sent on the falling edge of SCKT 16 bit mode (32 slots transmitted per LRCKT period) 18 bit mode (64 slots transmitted per LRCKT period) 20 bit mode (64 slots transmitted per LRCKT period) 24 bit mode (64 slots transmitted per LRCKT period)
PCMCONF is used to set the PCM Output Interface configuration: ORD: PCM order. If this bit is set to'1', the LS Bit is transmitted first, otherwise MS Bit is transmiited first. DIF: PCM_DIFF. It is used to select the position of the valid data into the transmitted word. This setting is significant only in 18/20/24 bit/word ode. If it is set to '0' the word is right-padded, otherwise it is left-padded. INV (fig.12): It is used to select the LRCKT clock polarity. If it is set to '1' the polarity is compliant to 2S format (low -> left , high -> right), otherwise the LRCKT is inverted. The default value is '0'. (if I2S have to be selected, must be set to '1' in the STA003T configuration phase). Figure 12. LRCKT Polarity Selection
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
FOR: FORMAT is used to select the PCM Output Interface format. After hw and sw reset the value is set to 0 corresponding to I2S format. SCL (fig.13): used to select the Transmitter Serial Clock polarity. If set to '1' the data are sent on the rising edge of SCKT and sampled on the falling. If set to '0' , the data are sent on the falling edge and sampled on the rising. This last option is the most commonly used by the commercial DACs.
23/39
STA003
The default configuration for this flag is '0'. Figure 13. SCKT Polarity Selection
PREC [1:0]: PCM PRECISION It is used to select the PCM samples precision, as follows: '00': 16 bit (16 slots transmitted per LCKT period) '01': 18 bit (32 slots transmitted per LCKT period) '10': 20 bit (32 slots transmitted per LCKT period) '11': 24 bit (32 slots transmitted per LCKT period) The PCM samples precision in STA003T can be 16 or 18-20-24 bits.
When STA003T operates with a 16 (18-20-24) bits precision, the number of bits transmitted during a LRCKT period is 32 (64). P CM C R O S S Address: 0x56 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
M SB b7 X X X X b6 X X X X b5 X X X X b4 X X X X b3 X
The default configuration for this register is '0x00'.
bs O
ANCILLARY DATA BUFFER Address: 0x59 - 0x5D Type: RO Software Reset: 0x00 Hardware Reset: 0x00 STA003T can extract max 56 bytes/MPEG frame. To know the number of A.D. bits available every MPEG frame, the ANCCOUNT_L and ANCCOUNT_H registers (0x41 and 0x42) have to be read. The buffer dimension is 5 bytes, written by STA003T core in sequential order. The timing information to read the buffer can be obtained by reading the FRAME_CNT registers (0x67 - 0x69). To fill up the buffer with a new 5-bytes slot, the STA003T waits until a CMD_INTERRUPT register is written by the master.
let o
ro P e
du
X X X
(s) ct
b2 X X X X b1 0 0 1 1
so Ob L SB b0 0 1 0 1
te le
ro P
uc d
s) t(
Descr iption Left channel is mapped on the left output. Right channel is mapped on the Right output Left channel is duplicated on both Output channels. Right channel is duplicated on both Output channels Right and Left channels are toggled
24/39
STA003
MFSDF (X) Address: 0x61 Type: R/W Software Reset: 0x0F Hardware Reset: 0x0F
MSB b7 X b6 X b5 X b4 M4 b3 M3 b2 M2 b1 M1 LSB b0 M0
The register contains the values for PLL X divider (see Fig. 6). The value is changed by the internal STA003T Core, to set the clock frequencies, according to the incoming bitstream. This value can be even set by the user to select the PCM interface configuration. The VCO output frequency is divided by (X+1). D AC_CLK_MOD E Address: 0x63 Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X
This register is used to select the operating mode for OCLK clock signal. If it is set to '1', the OCLK frequency is fixed, and it is mantained to the value fixed by the user even if the sampling frequency of the incoming bitstream changes. If the MODE flag is set to '0', the OCLK frequency changes, and can be set to (512, 384, 256) * Fs. The default configuration for this mode is 256 * Fs. When this mode is selected, the default OCLK frequency is 12.288 MHz. PLLFRAC_L ([7:0])
MSB
bs O
b7
PF7
let o
Pr e
b6 PF 6
du o
b5 P F5
(s) ct
b4
so Ob X
b3
te le
b2 X
ro P
uc d
X
s) t(
LSB b0 MO D E
b1
LSB b3 PF3 b2 PF 2 b1 PF1 b0 PF 0
PF 4
PLLFRAC_H ([15:8])
MSB b7 PF15 b6 PF14 b5 PF13 b4 PF12 b3 PF11 b2 PF10 b1 PF9 LSB b0 PF8
25/39
STA003
Address: 0x64 - 0x65 Type: R/W Software Reset: 0xC8-0x59 Hardware Reset: 0xC8-0x59 The registers are considered logically concatenated and contain the fractional values for the PLL, used to select the internal configuration. After Reset, the values are NA, and the operational setting are done when the MPEG synchronisation is achieved. The following formula describes the relationships mong all the STA003T fractional PLL parameters:
1 M C L K _freq PLLFRAC O C L K _freq = ---------------------------------------- ------------------------------------ P L L C T L _M + 1 + ---------------------------MFSDF(X) + 1 P L L T L _N + 1 65536
where: PLLFRAC = 256 x FRAC_H + PLLFRAC_L (decimal) FRAME_CNT_L
MSB b7 FC7 b6 FC6 b5 FC 5 b4 FC4 b3 FC3 b2 FC2 b1 FC1 LSB
FRAME_CNT_M
MSB b7 FC15 b6 FC14 b5 FC13 b4 FC12 b3 FC11
FRAME_CNT_H
MSB b7 FC23 b6 FC22 b5 FC21 b4
Address: 0x67, 0x68, 0x69 Type: RO Software Reset: 0x00 Hardware Reset: 0x00
The three registers are considered logically concatenated and compose the Global Frame Counter. They are updated at every decoded MPEG Frame. The registers are reset on both hardware and software reset.
bs O
AVERAGE_BITRATE Address: 0x6A Type: RO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 AB7 b6 AB6 b5 A B5 b4 AB 4 b3 AB3 b2 AB2 b1 AB1 LSB b0 AB0
let o
Pr e
du o
(s) ct
FC20
so Ob b3 FC19
eP let
b2 FC10 b2 FC18
ro
uc d
s) t(
b0 FC0 LSB b0 FC8
b1
FC9
LSB b1 FC 17 b0 FC16
26/39
STA003
AVERAGE_BITRATE is a read-only register and it contains the average bitrate of the incoming bitstream. The value is rounded with an accuracy of 1 Kbit/sec. SOFTVERSION Address: 0x71 Type: RO
MSB b7 SV7 b6 SV6 b5 S V5 b4 SV 4 b3 SV3 b2 SV2 b1 SV1 LSB b0 SV0
After the STA003T boot, this register contains the version code of the embedded software. R UN Address: 0x72 Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X
Setting this register to 1, STA003T leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN flag, once all the control registers have been initialized. TREBLE_FREQUENCY_LOW Address: 0x77 Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TF7
bs O
TREBLE_FREQUENCY_HIGH Address: 0x78 Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TF15 b6 TF14 b5 TF13 b4 TF12 b3 TF11 b2 TF10 b1 TF9 LSB b0 TF8
let o
Pr e
b6 TF6
du o
b5 TF5
(s) ct
b4 TF4
so Ob b3 TF3
eP let
b2 X
ro
uc d
X
s) t(
LSB b0 RUN
b1
LSB b2 TF2 b1 TF1 b0 TF0
27/39
STA003
The registers TREBLE_FREQUENCY_HIGH and TREBLE_FREQUENCY_LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is +12dB respect to the stop band. By setting these registers, the following rule must be kept: Treble_Freq < Fs/2 B AS S _ F R E Q U E N C Y _ L O W Address: 0x79 Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 BF7 b6 BF 6 b5 B F5 b4 BF 4 b3 BF3 b2 BF 2 b1 BF1 LSB b0 BF 0
BASS_FREQUENCY_HIGH Address: 0x7A Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 BF15 b6 BF14 b5 BF13 b4 BF12 b3
The registers BASS_FREQUENCY_HIGH and BASS_FREQUENCY_LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is -12dB respect to the pass-band. By setting the BASS_FREQUENCY registers, the following rules must be kept: Bass_Freq <= Treble_Freq Bass_Freq > 0 Example: Bass = 200Hz Treble = 3kHz
(suggested range: 20 Hz < Bass_Freq < 750 Hz)
bs O
TFS 15 0 BFS 15 0
let o
14 0
Pr e
12 0
du o
11 1
(s) ct
so Ob -
BF11
te le
b2
ro P
uc d
s) t(
LSB b0 BF8
b1
BF10
BF9
13 0
10 0
9 1
8 1
7 1
6 0
5 1
4 1
3 1
2 0
1 0
0 0
14 0
13 0
12 0
11 1
10 0
9 0
8 0
7 1
6 1
5 0
4 0
3 1
2 0
1 0
0 0
28/39
STA003
TRE BLE_E NHAN CE Address: 0x7B Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TE7 b6 TE6 b5 TE 5 b4 TE4 b3 TE3 b2 TE2 b1 TE1 LSB b0 TE0
Signed number (2 complement) This register is used to select the enhancement or attenuation STA003T has to perform on Treble Frequency range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhancement range is [-18dB, +18dB].
MSB b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 1 1 1 1 b2 1 0 0 0 b1 0 1 1 0
L SB b0 0 1 0 1
ENHANCE/ATTENUATION 1.5dB step +18
0 0 1
0 0 1
0 0 1
0 0 1
0 0
0
1 1
1
bs O
1
1
let o
1 1 1
ro P e
1 1 1 1
du
ct
1 0 0 0 0
(s)
0 1
Ob 0 0 1 1 1 0 0
so
: : 1 0 1 : :
eP let
ro
+16. 5 +15
uc d
s) t(
+13. 5
+1 0 -1
1 1 1 1
1 1 1 1
1 0 0 0
-13.5 - 15 -16.5 - 18
29/39
STA003
B AS S _ E N H A N C E Address: 0x7C Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 BE7 b6 BE6 b5 B E5 b4 BE 4 b3 BE3 b2 BE2 b1 BE1 LSB b0 BE0
Signed number (2 complement) This register is used to select the enhancement or attenuation STA003T has to perform on Bass Frequency range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhancement range is [-18dB, +18dB].
MSB b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 1 1 1 1 b2 1 0 0 0 b1 0 1 1 0
L SB b0 0 1 0 1 : :
ENHANCE/ATTENUATION 1.5dB step
+16. 5
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0
1 1 1 1
1 1 1 1
1 1
TONE_ATTEN
bs O
Address: 0x7D
Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TA7 b6 TA6 b5 TA5 b4 TA4 b3 TA3 b2 TA2 b1 TA1 LSB b0 TA0
let o
Pr e
1 1
du o
1 1 1
1
(s) ct
0 0 0 0
Ob 0 1 1 1 0 0
so
1 0 1 : : 1 0 0 0
eP let
ro
uc d
+18 +15 +1 0 -1
s) t(
+13. 5
1 1 1 1
-13.5 - 15 -16.5 - 18
In the digital output audio, the full signal is achieved with 0 dB of attenuation. For this reason, before applying Bass & Treble Control, the user has to set the TONE_ATTEN register to the maximum value of enhancement is going to perform.
30/39
STA003
For example, in case of a 0 dB signal (max. level) only attenuation would be possible. If enhancement is desired, the signal has to be attenuated accordingly before in order to reserve a margin in dB. An increment of a decimal unit corresponds to a Tone Attenuation step of 1.5dB.
MSB b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 0 0 1 0 b2 0 0 0 0 b1 0 0 1 1 L SB b0 0 1 0 1 : : 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 -15dB -16.5dB -18dB ATTENUATION -1.5dB step 0dB -1.5dB -3dB -4.5dB
5.0 GENERAL INFORMATION 5.1 MPEG 2.5 Layer III Algorithm.
DEMULTIPLEXING & ERROR CHECK
HUFFMAN DECODING
ANCILLARY DATA ENCODED AUDIO BITSTREAM (8Kbit/s ... 128Kbit/s)
5.2 MPEG Ancillary Data Description: As specifyed in the ISO standard, the MPEG Layer III frames have a variable bit lenght, and are constant in time depending on the audio sampling frequencies. The time duration of the Layer III frames is shown in Tab 2. MPEG Layer III Frames Time Duration
Sampling Frequency (KHz)
O
MPEG Frame Lenght (ms)
The Ancillary Data extraction on STA003T can be described as follow: STA003T has a specific 5 bytes Ancillary Data buffer, mapped into the I2C registers:
0x59 0x5A 0x5B 0x5C 0x5D ANC_DATA_1 ANC_DATA_2 ANC_DATA_3 ANC_DATA_4 ANC_DATA_5
bs
let o
od Pr e
ct u
48 24
(s)
SIDE INFORMATION DECODING
so Ob -
INVERSE QUANTISATION & DESCALING
te le
IMDCT
ro P
uc d
s) t(
INVERSE FILTERBANK
STEREOPHONIC AUDIO SIGNAL (2*768Kbit/s)
D98AU903
32 36
24 24
16 36
12 48
8 72
31/39
STA003
Since the content of Ancillary Data into an MPEG Frame is max. 56 bytes, a specific register, to require new 5 bytes, is needed. This register is:
0x16 CMD_INTERRUPT
The interrupt register, is sensitive to any non-zero value written by the Microcontroller. When this register is updated the Ancillary Data buffer is filled up with new values and the registers
0x41 0x42 ACCOUNT_L ACCOUNT_H
are updated (decremented) accordingly.
5.3 I/O CELL DESCRIPTION 1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pins number 9, 10, 11, 20, 28,
EN Z A
D98AU904
OUTPUT PIN Z
MAX LOAD
2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pins number 3, 12
EN IO A
ZI
3) CMOS Input Pad Buffer / Pin number 4, 5, 6, 8, 21, 25
A
bs O
let o
A
ro P e
uc d
D98AU905
(s) t
Z
so Ob INP U T PIN IO
te le
5pF
ro P
uc d
100pF
s) t(
CAPACITANCE
OUTP UT PIN IO
MAX LOAD 100pF
INPUT PIN A
CAPACITANCE 3 .5pF
D98AU906
4) CMOS Input Pad Buffer with Active Pull-Up / Pins number 7, 24, 26
Z
INPUT PIN A
CAPACITANCE 3 .5pF
D98AU907
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STA003
5.4 TIMING DIAGRAMS 5.4.1 Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC
OCLK (OUTPUT)
SDO tsdo SCKT tsckt LRCLK tlrclk
D98AU969
tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - pad_timing (Cload_ OCLK) Pad-timing versus load
Load (pF) 25 50 75 100
Pad_timing
Cload_XXX is the load in pF on the XXX output. b) OCLK in input
OCLK (INPUT)
Pad_timing (Cload_XXX) is the propagation delay added to the XXX pad due to the load.
O
bs
let o
Pr e
SDO
du o
(s) ct
thi ts d o tsckt
Ob tlo
so
te le
2.90ns 3.82ns 4.68ns 5.52ns
ro P
uc d
s) t(
SCKT
LRCLK tlrclk toclk
D98AU970
Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns
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5.4.2 Bitstream input interface (SDI, SCKR, BIT_EN)
BIT_EN t_biten SCKR(SCLK_POL=2) tsckr_min_hi t_biten
tsckr_min_hi
tlo
SCKR(SCLK_POL=0)
tsckr_min_period
SDI
D98AU971
tsdi_setup
tsdi_hold
tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns 5.4.3 SRC_INT SRC_INT is active low
t_src_hi
This is an asynchronous input used in "broadcast' mode.
SRC_INT
t_src_low min duration is 50ns (1DSP clock period) t_src_high min duration is 50ns (1DSP clock period) 5.4.4 XTI, XTO and CLK_OUT timings
O
bs
let o
XTO
od Pr e
ct u
thi
(s)
so Ob t_src_low
te le
ro P
uc d
s) t(
D98AU972
XTI (INPUT)
tlo
txto CLK_OUT tclk_out
D98AU973
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STA003
txto = 1.40 + pad_timing (Cload_XTO) ns 5.4.5 RESET The Reset min duration (t_reset_low_min) is 100ns
RESET
treset_low_min
D98AU974
5.5 DAC RELATED REGISTERS CONFIGURATION The different DAC registers must be configured for 48kHz audio frequency: this is the reference frequency. The STA003T will use these parameters to derivate the register configurations for the other audio frequencies (32, 24, 16, 12, 8 KHz) according to the bistream informations. The STA003T DAC and PLL register must be configured according to the following steps: 1) OCLK_Freq determination from the DAC oversampling factor O_FAC. As all STA003T registers must be configured for 48KHz reference frequency, the OCLK frquency is: OCLK_Freq = O_FAC × 48KHz ex: O_FAC = 384, OCLK_Freq = 18.432MHz 2) PCMDIVIDER (0 x 54) register configuration. The PCMDIVIDER register is used to configure the frequency ratio between OCLK_Freq and SCKT_Freq:
O C L K _freq S C K T _freq = -------------------------------------------------------------------(2 (1 + PCMDIVIDER))
The SCKT signal is the bit clock for the DAC serial output. The SCKT frequency depends on the number of bits to be transmitted to the DAC during one LRCKT (Left/Right clock) clock period. These number of bit depends on the DAC precision (16, 18, 20 or 24bits) and on the mode that is used to transmit the data to the DAC (see figure 8). Once the PCMCONF register is set according to the DAC requirements, the number of SCKT clock periods per LRCKT clock period is 16x2 or 32x2. a) LRCKT_period = 16x2 SCKT_periods
O C L K _freq S C K T _freq = L R C K T _freq 32 = -------------------------------------------------------------------(2 (1 + PCMDIVIDER))
As the reference audio frequency is 48 KHz, the previous relation becomes: 48KHz · 32 = 48kHz · O_FAC (2 · (1+ PCMDIVIDER)) Consequently: PCMDIVIDER = (O_FAC/64)-1
bs O
ex: O_FAC = 384, PCMCONF[1:0] = 00, PCMDIVIDER = 5 b) LRCKT_period = 32x2 SCKT_periods
O C L K _freq S C K T _freq = L R C K T _freq 64 = -------------------------------------------------------------------(2 (1 + PCMDIVIDER))
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
Consequently:
PCMDIVIDER = (O_FAC/128)-1 3) Configuration of the PLL registers to set OCLK_FREQ to the desired value computed in step 1. The PLL configuration in direct relation with the XTI input clock frequency (14.72 MHz).
1 14.72 M H z PLLFRAC O C L K _freq = ---------------------------------------- ----------------------------------------- P L C T L _M + 1 + ----------------------------- 1 + M F S D F ( X ) 1 + P L L C T L _N 65536
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MFSDF(X) is the value of the MFSDF(X)(0x61) register. PLLCTL_N is the value of the PLLCTL_N (0x07) register. PLLCTL_M is the value of the PLLCTL_N (0x07) register. PLLFRAC (decimal) is the value of the PLLFRAC_H and PLLFRAC_L registers as PLLFRAC = 256 × PLLFRAC_H + PLLFRAC_L. The following table gives the possible values for these registers according to different OCLK_Freq values. Other values can be supported on request to STMicroelectronics.
O_FAC 128 256 384 OCLK_Freq AT 48KHz 6.144MHz 12.288M Hz 18.432M Hz PLLCTL_N 0 0 0 PLLCTL_M 12 12 11 PLLFRAC 23365 23365 34193 MF S D F 31 15 9
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
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STA003
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
8 (max.)
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
o r8 P SO2
uc d
s) t(
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STA003
6.0 REVISION HISTORY Table 2. Document revision history
Date
Januar y-2002 27-Aug-2009
Revision
1 2 Initial release. Updated part number
Changes
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
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STA003
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O
bs
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
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