TDA7400D
ADVANCED CAR SIGNAL PROCESSOR
FULLY INTEGRATED SIGNAL PROCESSOR OPTIMIZED FOR CAR RADIO APPLICATIONS FULLY PROGRAMMABLE BY I2C BUS INCLUDES AUDIOPROCESSOR, STEREO DECODER WITH NOISE BLANKER AND MULTIPATH DETECTOR PROGRAMMABLE ROLL-OFF COMPENSATION NO EXTERNAL COMPONENTS DESCRIPTION The TDA7400D is the newcomer of the CSP family introduced by TDA7460/61. It uses the same innovative concepts and design technologies allowing fully software programmability through I2C bus and overall cost optimisation for the system designer. The device includes an audioprocessor with configurable inputs and absence of external components for filter settings, a last generation BLOCK DIAGRAM
SO28 ORDERING NUMBER: TDA7400D
stereodecoder with multipath detector and a sophisticated stereoblend and noise cancellation circuitry. Strength points of the CSP approach are flexibility and overall cost/room saving in the application, combined with high performances.
CDL CDGND CDR 7 6 5
SMUTE 18
ACOUTL 28
ACOUTR 27 MONO-FADER MONO-FADER 24 26 23 25 OUT LR OUT LF OUT RR OUT RF
AM CassR CassL PhPh+
10 4 3 8 9 INPUT MULTIPLEXER + AUTO ZERO MUXR MUXL FM_R FM_L
VOLUME
SOFT MUTE
TREBLE
BASS
MONO-FADER MONO-FADER
19 DIGITAL CONTROL I2C BUS 20 16 15
SCL SDA MUX R MUX L
MPX
11 80KHz LP
PILOT CANCELLATION
DEMODULATOR + STEREO ADJUST + STEREO BLEND
25KHz LP
S&H
HIGH CUT
QUAL. 22 1 SUPPLY PLL PIL DET MULTIPATHDETECTOR 13 MPIN 14 MPOUT FM NOISE BLANKER PULSE FORMER
17
QUAL
VDD VREF
D A 12 LEVEL
D99AU1046
21 GND
2 CREF
October 2003
1/28
TDA7400D
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Range Operating Storage Temperature Range Parameter Value 10.5 -40 to 85 -55 to 150 Unit V C C
SUPPLY
Symbol VS IS SVRR Parameter Supply Voltage Supply Current Ripple Rejection @ 1KHz VS = 9V Audioprocessor (all filters flat) Stereodecoder + Audioprocessor Test Condition Min. 7.5 25 50 45 Typ. 9 30 60 55 Max. 10 35 Unit V mA dB dB
ESD All pins are protected against ESD according to the MIL883 standard. PIN CONNECTION
VREF CREF CassL CassR CDR CDGND CDL PhPh+ AM MPX LEVEL MPIN MPOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D99AU1047
28 27 26 25 24 23 22 21 20 19 18 17 16 15
ACOUTL ACOUTR OUT LF OUT RF OUT LR OUT RR VDD GND SDA SCL SMUTE QUAL MUX R MUX L
THERMAL DATA
Symbol Rth-j pins Parameter Thermal Resistance Junction-pins Max Value 85 Unit C/W
2/28
TDA7400D
PIN DESCRIPTION
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name VREF CREF TAPEL TAPER CDR CDGND CDL PH PH + AM MPX LEVEL MPIN MPOUT MUXL MUXR QUAL SMUTE SCL SDA GND VS OUTRR OUTLR OUTRF OUTLF ACOUTR ACOUTL Function Reference Voltage Output Reference Capacitor Pin Tape Input Left Tape Input Right CD Right Channel Input CD Input Common Ground CD Input Left Channel Differential Phone Input Differential Phone Input + AM Input FM Stereodecoder Input Level Input Stereodecoder Multipath Input Multipath Output Multiplexer Output Left Channel Multiplexer Output Right Channel Stereodecoder Quality Output Soft Mute Drive I2C Clock Line I2C Data Line Supply Ground Supply Voltage Right Rear Speaker Output Left Rear Speaker Output Right Front Spaeaker Output Left Front Speaker Output Pre-speaker AC Output Right Channel Pre-speaker AC Output Left Channel Type I S I I I I I I I I I I I O O O O I I I/O S S O O O O O O
Pin type legenda: I = Input O = Output I/O = Input/Output S = Supply nc = not connected
3/28
TDA7400D
AUDIO PROCESSOR PART Input Multiplexer Quasi-differential CD and cassette stereo input AM mono input Phone differential input Multiplexer signal after In-Gain available at separate pins Volume control 1dB attenuator Max. gain 15dB Max. attenuation 79dB Bass Control 2nd order frequency response Center frequency programmable in 4(5) steps DC gain programmable 15 x 1dB steps Treble Control 2nd order frequency response Center frequency programmable in 4 steps 15 x 1dB steps Speaker Control 4 independent speaker controls in 1dB steps max gain 15dB max. attenuation 79dB Mute Functions Direct mute Digitally controlled softmute with 4 programmable mute time
ELECTRICAL CHARACTERISTICS (VS = 9V; Tamb = 25C; RL = 10K; all gains = 0dB; f = 1KHz; unless otherwise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit K VRMS dB dB dB dB mV mV K K dB dB 15 V
INPUT SELECTOR
Ri n VCL SIN GIN MIN GIN MAX GSTEP VDC Input Resistance Clipping Level Input Separation Min. Input Gain Max. Input Gain Step Resolution DC Steps Adjacent Gain Step GMIN to GMAX all inputs except Phone 70 2.2 80 -1 13 0.5 -5 -10 100 2.6 100 0 15 1 0.5 5 130
1 17 1.5 5 10
DIFFERENTIAL CD STEREO INPUT
Ri n CMRR eN Input Resistance Common Mode Rejection Ratio Output Noise @ Speaker Outputs Differential Common Mode VCM = 1VRMS @ 1KHz VCM = 1VRMS @ 10KHz 20Hz to 20KHz flat; all stages 0dB 70 70 45 45 100 100 70 60 6 130 130
DIFFERENTIAL PHONE INPUT
Ri n CMRR Input Resistance Common Mode Rejection Ratio Differential VCM = 1VRMS @ 1KHz VCM = 1VRMS @ 10KHz 40 40 40 56 70 60 K dB dB
4/28
TDA7400D
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
VOLUME CONTROL
GMAX AMAX ASTEP EA ET VDC Max Gain Max Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps G = -20 to 20dB G = -60 to 20dB Adjacent Attenuation Steps From 0dB to GMIN 13 70 0.5 -1.25 -4 15 79 1 0 0 0.1 0.5 1.5 1.25 3 2 3 5 17 dB dB dB dB dB dB mV mV
SOFT MUTE
AMUTE TD Mute Attenuation Delay Time T1 T2 T3 T4 VTHlow VTHhigh RPD Low Threshold for SM Pin1 High Threshold for SM Pin Internal Pull-up Resistor 20 200 2.5 70 13 fC1 fC2 fC3 fC4 QBASS Quality Factor Q1 Q2 Q3 Q4 DC = off DC = on 0.5 54 63 72 90 0.9 1.1 1.3 1.8 -1 3.5 13 0.5 fC1 fC2 fC3 fC4 8 10 12 14 80 100 0.48 0.96 40.4 324 1 2 60 600 1 130 17 1.5 66 77 88 110 1.1 1.4 1.7 2.2 1 5.5 17 1.5 12 15 18 21 dB ms ms ms ms V V K
100 15 1 60 70 80 100 (150)(2) 1 1.25 1.5 2 0 4.4 15 1 10 12.5 15 17.5
BASS CONTROL
CRANGE ASTEP fC Control Range Step Resolution Center Frequency dB dB Hz Hz Hz Hz
DCGAIN
Bass-Dc-Gain
dB dB
TREBLE CONTROL
CRANGE ASTEP fC Control Range Step Resolution Center Frequency dB dB KHz KHz KHz KHz
1) The SM pin is active low (Mute = 0) 2) See note in Programming Part
5/28
TDA7400D
ELECTRICAL CHARACTERISTICS (continued)
Symbol RIN GMAX AMAX ASTEP AMUTE EE VDC VCLIP RL CL ROUT VDC Parameter Input Impedance Max Gain Max Attenuation Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps Clipping Level Output Load Resistance Output Load Capacitance Output Impedance DC Voltage Level Output Noise Test Condition Min. 35 13 -70 0.5 80 Adjacent Attenuation Steps d = 0.3% 2.2 2 Typ. 50 15 -79 1 90 0.1 2.6 10 120 4.7 15 15 Max. 65 17 1.5 2 5 Unit K dB dB dB dB dB mV VRMS K nF V V V dB dB 0.1 0.1 1 2 0.8 2.5 -5 5 0.4 % % dB dB dB V V A V
SPEAKER ATTENUATORS
AUDIO OUTPUTS
4.3 BW = 20 Hz to 20 KHz output muted BW = 20 Hz to 20 KHz all gain = 0dB all gain = 0dB flat; VO = 2VRMS bass treble at 12dB; a-weighted; VO = 2.6VRMS VIN = 1VRMS; all stages 0dB VIN = 1VRMS; Bass & Treble = 12dB AV = 0 to -20dB AV = -20 to -60dB d = 0.3% VIN = 0.4V IO = 1.6mA
30 4.5 3 6.5
GENERAL
eNO
S/N
Signal to Noise Ratio
102 96
110 100 0.002 0.05 100 0 0
d SC ET
Distortion Channel separation Left/Right Total Tracking Error
80 -1 -2
BUS INPUTS
VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge
6/28
TDA7400D
Stereodecoder Part ELECTRICAL CHARACTERISTICS (VS = 9V; deemphasis time constant = 50s, VMPX = 500mV(75KHz deviation), fm= 1KHz, Gv = 6dB, Tamb = 27C; unless otherwise specified).
Symbol Vi n Ri n GMIN GMAX GSTEP SVRR THD S+ N N Parameter MPX Input Level Input Resistance Min. Input Gain Max. Input Gain Step Resolution Supply Voltage Ripple Rejection Max. channel Separation Total Harmonic Distortion Signal plus Noise to Noise Ratio A-weighted, S = 2Vrms 80 Vripple = 100mV; f = 1KHz Test Condition Gv = 3.5dB 70 1.5 8.5 1.75 35 30 Min. Typ. 0.5 100 3.5 11 2.5 60 50 0.02 91 0.3 Max. 1.25 130 4.5 12.5 3.25 Unit VRMS K dB dB dB dB dB % dB
MONO/STEREO-SWITCH
VPTHST1 VPTHST0 VPTHMO1 VPTHMO0 Pilot Threshold Voltage Pilot Threshold Voltage Pilot Threshold Voltage Pilot Threshold Voltage for Stereo, PTH = 1 for Stereo, PTH = 0 for Mono, PTH = 1 for Mono, PTH = 1 10 15 7 10 15 25 12 19 25 35 17 25 mV mV mV mV
PLL
f/f HC50 HC75 HC50 HC75 Capture Range 0.5 % s s s s
DEEMPHASIS and HIGHCUT
Deemphasis Time Constant Deemphasis Time Constant Highcut Time Constant Highcut Time Constant Bit 7, Subadr, 10 = 0, VLEVEL >> VHCH Bit 7, Subadr, 10 = 1, VLEVEL >> VHCH Bit 7, Subadr, 10 = 0, VLEVEL >> VHCL Bit 7, Subadr, 10 = 1, VLEVEL >> VHCL 25 50 100 150 50 75 150 225 75 100 200 300
STEREOBLEND-and HIGHCUT-CONTROL
REF5V TCREF5V LGmin LGmax LGstep VSBLmin VSBLmax VSBLstep VHCHmin VHCHmax VHCHstep VHCLmin VHCLmax VHCLstep Internal Reference Voltage Temperature Coefficient Min. LEVEL Gain Max. LEVEL Gain LEVEL Gain Step Resolution Min. Voltage for Mono Min. Voltage for Mono Step Resolution Min. Voltage for NO Highcut Min. Voltage for NO Highcut Step Resolution Min. Voltage for FULL Highcut Max. Voltage for FULL Highcut Step Resolution 4.7 -1 8 0.3 25 54 2.2 38 62 5 12 28 2.2 5 3300 0 10 0.67 29 58 4.2 42 66 8.4 17 33 4.2 5.3 1 12 1 33 62 6.2 46 70 12 22 38 6.2 V ppm dB dB dB %REF5V %REF5V %REF5V %REF5V %REF5V %REF5V %VHCH %VHCH %VHCH
7/28
TDA7400D
ELECTRICAL CHARACTERISTICS (continued)
Symbol 19 38 57 76 2 3 57 67 114 190 Parameter Pilot Signal f = 19KHz Subcarrier f = 38KHz Subcarrier f = 57KHz Subcarrier f = 76KHz fmod = 10KHz, fspur = 1KHz fmod = 13KHz, fspur = 1KHz Signal f = 57KHz Signal f = 67KHz Signal f = 114KHz Signal f = 190KHz Test Condition Min. 40 Typ. 50 75 62 90 65 75 70 75 95 84 Max. Unit dB dB dB dB dB dB dB dB dB dB
Carrier and harmonic suppression at the output
Intermodulation (Note 1)
Traffic Ratio (Note 2) SCA - Subsidiary Communications Authoorization (Note 3) ACI - Adjacent Channel Interference (Note 4)
Notes to the characteristics: 1. Intermodulation Suppression: 2 = 3 = VO(si gn al)(at1KHz) ; fs = (2 x 10KHz) - 19KHz VO(spurious)(at1KHz) VO(s ig nal)(at1KHz) ; fs = (3 x 13KHz) - 38KHz VO(spurious)(at1KHz)
measured with: 91% pilot signal; fm = 10kHz or 13kHz.
2. Traffic Radio (V.F.) Suppression: measured with: 91% stereo signal; 9% pilot signal; fm=1kHz; 5% subcarrier (f = 57kHz, fm = 23Hz AM, m = 60%) 57 (V.W>F.) =
VO(signal)(at1KHz) VO(spurious(at1KHz +/- 23KHz) )
3. SCA ( Subsidiary Communications Authorization ) measured with: 81% mono signal; 9% pilot signal; fm = 1kHz; 10%SCA - subcarrier ( fs = 67kHz, unmodulated ). 67 =
VO(signa)(at1KHz) l ; FS = (2 x 38KHz) -67KHz VO(spurious(at9KHz) )
4. ACI ( Adjacent Channel Interference ):
114 = 190 =
VO(signal)(at1KHz) ; FS = 110KHz - (3 x 38KHz) VO(spurious)(at4KHz) VO(signal)(at1KHz) ; FS = 186KHz - (5 x 38KHz) VO(spurious)(at4KHz)
measured with: 90% mono signal; 9% pilot signal; fm =1kHz; 1% spurious signal ( fs = 110kHz or 186kHz, unmodulated).
8/28
TDA7400D
NOISE BLANKER PART internal 2nd order 140kHz high pass filter programmable trigger threshold trigger threshold dependent on high frequency noise with programmable gain additional circuits for deviation and fieldstrength dependent trigger adjustment ELECTRICAL CHARACTERISTICS (continued)
Symbol VTR Parameter Trigger Threshold 0) 1) Test Condition meas. with VPEAK = 0.9V NBT = 111 NBT = 110 NBT = 101 NBT = 100 NBT = 011 NBT = 010 NBT = 001 NBT = 000 NCT = 00 NCT = 01 NCT = 10 NCT = 11 NRD 6) = 00 Min. (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) 0.5 1.5 2.2 0.5 0.9 1.7 2.5 0.5 0.9 1.7 2.1 TBD TBD TBD TBD (c) (c) (c) (c) (c) (c) Typ. 30 35 40 45 50 55 60 65 260 220 180 140 0.9 1.7 2.5 0.9(off) 1.2 2.0 2.8 0.9(off) 1.4 1.9 2.4 38 32 25.5 22 0.3 0.8 1.3 2.0 10 20 Max. (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) 1.3 2.1 2.9 1.3 1.5 2.3 3.1 1.3 1.5 2.3 3.1 TBD TBD TBD TBD (c) (c) (c) (c) (c) (c) Unit mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP V V V VOP VOP VOP VOP V V V V s s s s V/ms V/ms V/ms V/ms mV/s mV/s
very low offset current during hold time due to opamps wMOS inputs four selectable pulse suppression times programmable noise rectifier charge/discharge current
VTRNOISE
Noise Controlled Trigger Threshold 2)
meas. with VPEAK = 1.5V
VRECT
Rectifier Voltage
VRECT DEV
deviation dependent rectifier Voltage 3)
VRECT FS
Fieldstrength Controlled Rectifier Voltage 4)
TS
Suppression Pulse Duration 5)
VRECTADJ
Noise Rectifier discharge adjustment 6)
SRPEAK
Noise Rectifier Charge
VMPX = 0mV VMPX = 50mV; f = 150KHz VMPX = 200mV; f = 150KHz means. with OVD = 11 VMPX = 800mV OVD = 10 (75KHz dev.) OVD = 01 OVD = 00 means. with FSC = 11 VMPX = 0mV FSC = 10 VLEVEL << VSBL FSC = 01 (fully mono) FSC = 00 Signal HOLDN BLT = 00 in Testmode BLT = 10 BLT = 01 BLT = 00 Signal PEAK in NRD = 00 6) Testmode NRD = 01 6) NRD = 10 6) NRD = 11 6) Signal PEAK in PCH = 0 7) Testmode PCH = 1 7)
(c) = by design/characterization functionally guaranteed through dedicated test mode structure
9/28
TDA7400D
ELECTRICAL CHARACTERISTICS (continued)
Symbol VADJMP Parameter Noise Rectifier adjustment through Multipath 8) Test Condition Signal PEAK in MPNB = 00 8) Testmode MPNB = 01 8) MPNB = 10 8) MPNB = 11 8) Min. (c) (c) (c) (c) Typ. 0.3 0.5 0.7 0.9 Max. (c) (c) (c) (c) Unit V/ms V/ms V/ms V/ms
0) All Thresholds are measured using a pulse with TR =2s, THIGH = 2s and TF = 10s. The repetition rate must not increase the PEAK voltage. 1) NBT represents the Noiseblanker Byte bits D2, D0 for the noise blanker trigger threshold 2) NAT represents the Noiseblanker Byte bit pair D4, D3 for the noise controlled triggeradjustment 3) OVD represents the Noiseblanker Byte bit pair D7, D6 for the over deviation detector 4) FSC represents the Fieldstrength Byte bit pair D1, D0 for the fieldstrength control 5) BLT represents the Speaker RR Byte bit pair D7, D6 for the blanktime adjustment 6) NRD represents the Configuration-Byte bit pair D1, D0 for the noise rectifier discharge-adjustment 7) PCH represents the Stereodecoder-Byte bit D5 for the noise rectifier charge-current adjustment 8) MPNB represents the HighCut-Byte bit D7 and the Fieldstrength-Byte D7 for the noise rectifier multipath adjustment
VIN VOP
DC
D97AU636
TR
THIGH
TF
Time
Figure 1. Trigger Threshold vs.VPEAK
Figure 2. Deviation Controlled Trigger Adjustment
VTH
VPEAK (VOP) 00
260mV(00) 220mV(01) 180mV(10) 140mV(11)
2.8 2.0
01
MIN. TRIG. THRESHOLD NOISE CONTROLLED TRIG. THRESHOLD 65mV 8 STEPS 30mV VPEAK(V)
D97AU649
10 1.2 0.9 DETECTOR OFF (11)
20
32.5
45
75
DEVIATION(KHz)
0.9V
D97AU648
1.5V
10/28
TDA7400D
Figure 3. Fieldstrength Controlled Trigger Adjustment
VPEAK MONO STEREO
»3V
2.4V(00) 1.9V(01) 1.4V(10) NOISE ATC_SB OFF (11)
0.9V
noisy signal
D97AU650
good signal
E'
Multipath Detector Internal 19kHz band pass filter Programmable band pass and rectifier gain
two pin solution fully independent usable for external programming selectable internal influence on Stereoblend
ELECTRICAL CHARACTERISTICS (continued)
Symbol fCMP GBPMP Parameter Center Frequency of MultipathBandpass Bandpass Gain Test Condition stereodecoder locked on Pilottono bits D2, D1 configuration byte = 00 bits D2, D1 configuration byte = 10 bits D2, D1 configuration byte = 01 bits D2, D1 configuration byte = 11 GRECTMP Rectifier Gain bits D7, D6 configuration byte = 00 bits D7, D6 configuration byte = 01 bits D7, D6 configuration byte = 10 bits D7, D6 configuration byte = 11 bit D5 configuration byte = 0 bit D5 configuration byte = 1 0.5 Min. Typ. 19 6 12 16 18 7.6 4.6 0 off 0.5 1.0 1 Max. Unit KHz dB dB dB dB dB dB dB dB A A mA
ICHMP IDISMP
Rectifier Charge Current Rectifier Discharge Current
1.5
Quality Detector
Symbol A Parameter Multipath Influence Factor Test Condition bit D7 High-Cut byte + bit D7 Fieldstrength byte + 00 01 10 11 Min. Typ. 0.7 0.85 1.00 1.15 Max. Unit
11/28
TDA7400D
DESCRIPTION OF THE AUDIOPROCESSOR PART Input Multiplexer CD quasi differential Cassette stereo Phone differential AM mono Stereodecoder input. Input stages Most of the input stages have remained the same as in preceeding ST audioprocessors with exception of the CD inputs (see figure 4). In the meantime there are some CD players in the market having a significant high source impedance which affects strongly the commonmode rejection of the normal differential input stage. The additional buffer of the CD input avoids this drawback and offers the full commonmode rejection even with those CD players. The output of the Cd stage is permanently available of the Cd out-pins coder, the Input Stage and the In-Gain (Please notice that externally generated offsets, e.g. generated through the leakage current of the coupling capacitors, are not cancelled). The auto-zeroing is started every time the DATABYTE 0 is selected and takes a time of max. 0.3ms. To avoid audible clicks the audioprocessor is muted before the volume stage during this time. AutoZero Remain In some cases, for example if the P is executing a refresh cycle of the I2C bus programming, it is not useful to start a new AutoZero action because no new source is selected and an undesired mute would appear at the outputs. For such applications the TDA7400D could be switched in the "Auto Zero Remain mode" (Bit 6 of the subaddress byte). If this bit is set to high, the DATABYTE 0 could be loaded without invoking the AutoZero and the old adjustment value remains. Multiplexer Output The output signal of the Input Multiplexer is available at separate pins (please see the Blockdiagram). This signal represents the input signal amplifier by the In Gain stage and is also going into the Mixer stage. Softmute The digitally controlled softmute stage allows muting/demuting the signal with a I2C bus programmable slope. The mute process can either be activated by the softmute pin or by the I2C bus. The slope is realized in a special S shaped curve to mute slow in the critical regions (see figure 5).
AutoZero In order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage, so that any offset generated by or before the In-Gain stage would be transferred or even amplified to the output. To avoid that effect a special offset cancellation stage called AutoZero is implemented. This stage is located before the volume-block to eliminate all offsets generated by the StereodeFigure 4. Input stages
15K CD+ 100K 1 + 15K CD100K 15K PHONE+ + 15K PHONECASSETTE 100K 1
15K
CD OUT
15K
15K
15K
IN GAIN
AM 100K STEREODECODER 100K
D98AU854A
MPX
12/28
TDA7400D
cies 60,70,80 and 100Hz. Quality Factors Figure 8 shows the four possible quality factors 1, 1.25, 1.5 and 2. DC Mode In this mode the DC gain is increased by 5.1dB. In addition the programmed center frequency and quality factor is decreased by 25% which can be used to reach alternative center frequencies or quality factors.
Figure 5. Softmute Timing
EXT. MUTE
1
+SIGNAL
REF
-SIGNAL
1 I2C BUS OUT
D97AU634
Time
TREBLE There are two parameters programmable in the treble stage (see figs 10, 11): Attenuation Figure 10 shows the attenuation as a function of frequency at a center frequency of 17.5KHz. Center Frequency Figure 11 shows the four possible Center Frequency (10, 12.5, 15 and 17.5kHz). Speaker Attenuator The speaker attenuators have exactely the same structure and range like the Volume stage.
Note: Please notice that a started Mute action is always terminated and could not be interrupted by a change of the mute signal.
For timing purposes the Bit 3 of the I2C bus output register is set to 1 from the start of muting until the end of demuting. Bass There are four parameters programmable in the bass stage: (see figs 6, 7, 8, 9): Attenuation Figure 6 shows the attenuation as a function of frequency at a center frequency at a center frequency of 80Hz. Central Frequency Figure 7 shows the four possible center frequenFigure 6. Bass Control @ fc = 80Hz, Q = 1
15.0 10.0 5.0 0.0 -5.0 -10.0 -15.0 10.0 100.0 1.0K 10.0K
Figure 7. Bass Center @ Gain = 14dB, Q = 1
15.0 12.5 10.0 7.5 5.0 2.5 0.0 10.0 100.0 1.0K 10.0K
13/28
TDA7400D
Figure 8. Bass Quality factors @ Gain = 14dB, fc = 80Hz
15.0 12.5 10.0 7.5 5.0 2.5
Figure 9. Bass normal and DC Mode @ Gain = 14dB, fc = 80Hz
15.0 12.5 10.0 7.5 5.0 2.5 0.0
0.0
10.0 100.0 1.0K 10.0K
10.0
100.0
1.0K
10.0K
Note: In general the center frequency, Q and DC-mode can be set independently. The exception from this rule is the mode (5/xx1111xx) where the center frequency is set to 150Hz instead of 100Hz.
Figure 10. Treble Control @ fc = 17.5KHz
15.0 10.0
Figure 11. Treble Center Frequencies @ Gain = 14dB
15.0 12.5
5.0
10.0
0.0 -5.0 -10.0 -15.0 10.0
7.5 5.0 2.5 0.0
100.0
1.0K
10.0 K
10.0
100.0
1.0K
10.0K
14/28
TDA7400D
FUNCTIONAL DESCRIPTION OF STEREODECODER The stereodecoder part of the TDA7400D (see Fig. 12) contains all functions necessary to demodulate the MPX signal like pilot tone dependent MONO/STEREO switching as well as "stereoblend" and "highcut" functions. Stereodecoder Mute The TDA7400D has a fast and easy to control RDS mute function which is a combination of the audioprocessor's softmute and the high-ohmic mute of the stereodecoder. If the stereodecoder is selected and a softmute command is sent (or activated through the SM pin) the stereodecoder will be set automatically to the high-ohmic mute condition after the audio signal has been softmuted. Hence a checking of alternate frequencies could be performed. To release the system from the mute condition simply the unmute command must be sent: the stereodecoder is unmuted immediately and the audioprocessor is softly unmuted. Fig. 13 shows the output signal VO as well as the internal stereodecoder mute signal. This influence of Softmute on the stereodecoder mute can Figure 12. Block Diagram of the Stereodecoder be switched off by setting bit 3 of the Softmute byte to "0". A stereodecoder mute command (bit 0, stereodecoder byte set to "1") will set the stereodecoder in any case independently to the high-ohmic mute state. If any other source than the stereodecoder is selected the decoder remains muted and the MPX pin is connected to Vref to avoid any discharge of the coupling capacitor through leakage currents. Ingain + Infilter The Ingain stage allows to adjust the MPX signal to a magnitude of about 1Vrms internally which is the recommended value. The 4th order input filter has a corner frequency of 80KHz and is used to attenuate spikes and nose and acts as an anti allasing filter for the following switch capacitor filters. Demodulator In the demodulator block the left and the right channel are separated from the MPX signal. In this stage also the 19 kHz pilot tone is cancelled. For reaching a high channel separation the TDA7400D offers an I2C bus programmable roll-
INGAIN MPX 100K 3.5 ... 11dB STEP 2.5dB
INFILTER LP 80KHz 4.th ORDER
DEMODULATOR - PLOT CANC - ROLL-OFF COMP. - LP 25KHz
DEEMPHASIS + HIGHCUT t=50 or 75s
FM_L
FM_R
PLL + PILOT-DET. F19 F38 STEREO
SB CONTROL
REF 5V VSBL
HC CONTROL D A
VHCCH VHCCL
MPINFL LEVEL INTERN
LEVEL INPUT LP 2.2KHZ 1.th ORDER GAIN 0..10dB QUALITY DETECTOR LEVEL
NOISE BLANKER HOLDN NOISE
-
MULTIPATH DETECTOR MPLEVELOUT
MP_OUT
MP_IN
+
QUAL
D98AU855
15/28
TDA7400D
Figure 13. Signals During Stereodecoder's Softmute
SOFTMUTE COMMAND t STD MUTE
Figure 14. Internal Stereoblend Characteristics
t
VO
D97AU638
t
off adjustment which is able to compensate the lowpass behaviour of the tuner section. If the tuner attenuation at 38kHz is in a range from 13.8% to 24.6% the TDA7400D needs no external network in front of the MPX pin. Within this range an adjustment to obtain at least 40dB channel separation is possible. The bits for this adjustment are located together with the fieldstrength adjustment in one byte. This gives the possibility to perform an optimization step during the production of the carradio where the channel separation and the fieldstrength control are trimmed. The setup of the Stereoblend characteristics which is programmable in a wide range is described in 2.8. Deemphasis and Highcut. The lowpass filter for the deemphasis allows to choose between a time constant of 50s and 75s (bit D7, Stereodecoder byte). The highcut control range will be in both cases HC = 2 Deemp. Inside the highcut control range (between VHCH and VHCL) the LEVEL signal is converted into a 5 bit word which controls the lowpass time constant between Deemp...3 Deemp. There by the resolution will remain always 5 bits independently of the absolute voltage range between the VHCH and VHCL values. The highcut function can be switched off by I2C bus (bit D7, Fieldstrength byte set to "0"). The setup of the highcut characteristics is described in 2.9. PLL and Pilot Tone Detector The PLL has the task to lock on the 19kHz pilo16/28
tone during a stereo transmission to allow a correct demodulation. The included detector enables the demodulation if the pilot tone reaches the selected pilot tone threshold VPTHST. Two different thresholds are available. The detector output (signal STEREO, see block diagram) can be checked by reading the status byte of the TDA7400D via I2C bus. Fieldstrength Control The fieldstrength input is used to control the high cut and the stereoblend function. In addition the signal can be also used to control the noiseblanker thresholds and as input for the multipath detector. These additional functions are described in sections 3.3 and 4. LEVEL Input and Gain To suppress undesired high frequency modulation on the highcut and stereoblend function the LEVEL signal is lowpass filtered firstly. The filter is a combination of a 1st order RC lowpass at 53kHz (working as anti-aliasing filter) and a 1st-order switched capacitor lowpass at 2.2kHz. The second stage is a programmable gain stage to adapt the LEVEL signal internally to different IF device (see Testmode section 5 LEVELINTERN). The gain is widely programmable in 16 steps from 0dB to 10dB (step = 0.67dB). These 4 bits are located together with the Roll-Off bits in the "Stereodecoder Adjustment" byte to simplify a possible adaptation during the production of the carradio. Stereoblend Control The stereoblend control block converts the inter-
TDA7400D
Figure 15. Relation Between Internal and External LEVEL Voltage and Setup of Stereoblend
INTERNAL VOLTAGES REF 5V
SETUP OF VST LEVEL INTERN
INTERNAL VOLTAGES REF 5V
SETUP OF VMO
LEVEL INTERN
LEVEL VSBL VSBL
58% 50% 42% 33%
VMO
VST
t FIELDSTRENGHT VOLTAGE
D97AU639
VMO
VST
t FIELDSTRENGHT VOLTAGE
Figure 16. Highcut Characteristics
LOWPASS TIME CONSTANT
3·Deemp
Deemp
The MONO voltage VMO (0dB channel separation) can be choosen selecting VSBL All necessary internal reference voltages like REF5V are derived from a bandgap circuit. Therefore they have a temperature coefficient near zero. This is useful if the fieldstrength signal is also temperature compensated. But most IF devices apply a LEVEL voltage with a TC of 3300ppm. The TDA7400D offers this TC for the reference voltages, too. The TC is selectable with bit D7 of the "stereodecoder adjustment" byte. Highcut Control The highcut control setup is similar to the stereoblend control setup : the starting point VHCH can be set with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17, 22, 28 or 33% of VHCH (see fig. 21). FUNCTIONAL DESCRIPTION OF THE NOISEBLANKER In the automotive environment the MPX signal is disturbed by spikes produced by the ignition and for example the wiper motor. The aim of the noiseblanker part is to cancel the audible influence of the spikes. Therefore the output of the stereodecoder is held at the actual voltage for a time between 22 and 38s (programmable). The block diagram of the noiseblanker is given in fig.17. In a first stage the spikes must be detected but to avoid a wrong triggering on high frequency (white) noise a complex trigger control is implemented. Behind the triggerstage a pulse former generates the "blanking" pulse. To avoid any crosstalk to the signalpath the noiseblanker is
17/28
VHCL
D97AU640
VHCH
FIELDSTRENGHT
nal LEVEL voltage (LEVEL INTERN) into an demodulator compatible analog signal which is used to control the channel separation between 0dB and the maximum separation. Internally this control range has a fixed upper limit which is the internal reference voltage REF5V. The lower limit can be programmed between 29.2% and 58%, of REF5V in 4.167% steps (see figs. 11, 12). To adjust the external LEVEL voltage to the internal range two values must be defined: the LEVEL gain LG and VSBL (see fig. 12). To adjust the voltage where the full channel separation is reached (VST) the LEVEL gain LG has to be defined. The following equation can be used to estimate the gain: LG =
REF5V Fi eld strength voltage[STEREO]
The gain can be programmed through 4 bits in the "Stereodecoder-Adjustment" byte.
TDA7400D
supplied by his own biasing circuit. Trigger Path The incoming MPX signal is highpass filtered, amplified and rectified. This second order highpass-filter has a corner frequency of 140kHz. The rectified signal, RECT, is lowpass filtered to generate a signal called PEAK. Also noise with a frequency 140kHz increases the PEAK voltage. The resulting voltage can be adjusted by use of the noise rectifier discharge current. The PEAK voltage is fed to a threshold generator, which adds to the PEAK voltage a DC dependent threshold VTH. Both signals, RECT and PEAK+VTH are fed to a comparator which triggers a re-triggerable monoflop. The monoflop's output activates the sample-and-hold circuits in the signalpath for selected duration. Automatic Noise Controlled Threshold Adjustment (ATC) There are mainly two independent possibilities for programming the trigger threshold: a the low threshold in 8 steps (bits D0 to D2 of the noiseblanker byte) b the noise adjusted threshold in 4 steps (bits D3 and D4 of the noiseblanker byte, see fig. 14). The low threshold is active in combination with a good MPX signal without any noise; the PEAK voltage is less than 1V. The sensitivity in this operation is high. If the MPX signal is noisy the PEAK voltage increases due to the higher noise, which is also Figure 17. Block Diagram of the Noiseblanker rectified. With increasing of the PEAK voltage the trigger threshold increases, too. This particular gain is programmable in 4 steps (see fig. ...). AUTOMATIC THRESHOLD CONTROL MECHANISM Automatic Threshold Control by the Stereoblend Voltage Besides the noise controlled threshold adjustment there is an additional possibility for influencing the trigger threshold. It is depending on the stereoblend control. The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting point of the normal noise-controlled trigger adjustment is fixed (fig. 11). In some cases the behaviour of the noiseblanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes a wrong triggering occures for the MPX signal often shows distortion in this range which can be avoided even if using a low threshold. Because of the overlap of this range and the range of the stereo/mono transition it can be controlled by stereoblend. This threshold increase is programmable in 3 steps or switched off with bits D0 and D1 of the fieldstrength control byte. Over Deviation Detector If the system is tuned to stations with a high deviation the noiseblanker can trigger on the higher frequencies of the modulation. To avoid this wrong behaviour, which causes noise in the output signal, the noiseblanker offers a deviation dependent threshold adjustment.
MPX
RECTIFIER
RECT
+ VTH
MONOFLOP
HOLDN
+
PEAK LOWPASS MPX CONTROL +
THRESHOLD GENERATOR
ADDITIONAL THRESHOLD CONTROL
D98AU856
18/28
TDA7400D
Figure 18. Block Diagram of the Multipath Detector
LEVEL VDD
-
to SB
int. INFLUENCE CHARGE 1 bit
MP_IN
BANDPASS 19KHz
RECTIFIER
MPOUT GAIN 2 BITS GAIN 2 BITS 47nF
D98AU857
By rectifying the MPX signal a further signal representing the actual deviation is obtained. It is used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3 steps with the bits D6 and D7 of the stereodecoder byte (the first step turns off the detector, see fig. 15). FUNCTIONAL DESCRIPTION OF THE MULTIPATH DETECTOR Using the internal multipath detector the audible effects of a multipath condition can be minimized. A multipath condition is detected by rectifying the 19kHz spectrum in the fieldstrength signal. An external capacitor is used to define the attack and decay times (see block diagram fig. 23). the MPOUT pin is used as detector output connected to a capacitor of about 47nF and additionally the MPIN pin is selected to be the fieldstrength input. Using the configuration an external adaptation to the user's requiremet is given in fig.25. Selecting the "internal influence" in the configuration byte, the channel separation is automatically reduced during a multipath condition according to the voltage appearing at the MP_OUT pin. A possible application is shown in fig. 26. Programming To obtain a good multipath performance an adaptation is necessary. Therefore tha gain of the
19kHz bandpass is programmable in four steps as well as the rectifier gain. The attack and decay times can be set by the external capacitor value. QUALITY DETECTOR The TDA7400D offers a quality detector output which gives a voltage representing the FM reception conditions. To calculate this voltage the MPX noise and the multipath detector output are summed according to the following formula: Quality = 1.6 (Vnoise -0.8V)+ a (REF5V- VMPOUT) The noise signal is the PEAK signal without additional influences. The factor "a" can be programmed from 0.7 to 1.15. the output is a low impedance output able to drive external circuitry as well as simply fed to an A/D converter for RDS applications. TEST MODE During the test mode which can be activated by setting bit D0 of the testing byte and bit D5 of the subaddress byte to "1" several internal signals are available at the CASSR pin. During this mode the input resistor of 100kOhm is disconnected from the pin. The internal signals available are shown in the software specification.
19/28
TDA7400D
I2C BUS INTERFACE DESCRIPTION Interface Protocol The interface protocol comprises: -a start condition (S) -a chip address byte (the LSB bit determines read
CHIP ADDRESS MSB S 1 0 0 0 1 1 LSB 0 R/W ACK MSB X AZ T I
/ write transmission) -a subaddress byte -a sequence of data (N-bytes + acknowledge) -a stop condition (P)
SUBADDRESS LSB A3 A2 A1 A0 ACK MSB
DATA 1 to DATA n LSB DATA ACK P
D97AU627
S = Start ACK = Acknowledge AZ = AutoZero-Remain T = Testing I = Autoincrement P = Stop MAX CLOCK SPEED 500kbits/s The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address. SUBADDRESS (receive mode) MSB
I3 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 I2 I1 I0 A3 A2 A1
Auto increment If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled. TRANSMITTED DATA (send mode)
MSB X X X X ST SM X LSB X
SM = 1 Soft mute activated ST = 1 Stereo mode X = Not Used
LSB
A0
FUNCTION
AntiRadiation Filter off on AutoZero Remain off on Testmode off on Auto Increment Mode off on Databyte Addressing Input Selector Volume Treble Bass Speaker attenuator LF Speaker attenuator RF Speaker attenuator LR Speaker attenuator RR SoftMute / Bass Prog. Stereodecoder Noiseblanker High Cut Control Fieldstrength & Quality Configuration Stereodecoder Adjustment Testing
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
20/28
TDA7400D
DATA BYTE SPECIFICATION Input Selector (subaddress 0H) MSB
D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 : 1 1 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 D1 0 0 1 1 0 0 1 1
LSB
D0 0 1 0 1 0 1 0 1
FUNCTION
Source Selector CD Cassette Phone AM Stereo Decoder AC Inputs Front Mute AC inputs Rear In-Gain 15dB 14dB : 1 dB 0 dB must be "1"
Volume and Speaker Attenuation (subaddress 1H, 4H, 5H, 6H, 7H) MSB
D7 1 : 1 1 1 : 1 0 0 0 : 0 0 : 0 0 X D6 0 : 0 0 0 : 0 0 0 0 : 0 0 : 1 1 1 D5 0 : 0 0 0 : 0 0 0 0 : 0 0 : 0 0 1 D4 1 : 1 1 0 : 0 0 0 0 : 0 1 : 0 0 X D3 1 : 0 0 1 : 0 0 0 0 : 1 0 : 1 1 X D2 1 : 0 0 1 : 0 0 0 0 : 1 0 : 1 1 X D1 1 : 0 0 1 : 0 0 0 0 : 1 0 : 1 1 X
LSB
D0 1 : 1 0 1 : 1 0 0 1 : 1 0 : 0 1 X +15dB : +1dB 0dB 0dB -1dB : -15dB -16dB : -78dB -79dB Mute
FUNCTION
not used configurations
21/28
TDA7400D
Treble Filter (subaddress 2H) MSB
D7 D6 D5 D4 0 0 : 0 0 1 1 : 1 1 0 0 1 1 1 0 1 0 1 D3 0 0 : 1 1 1 1 : 0 0 D2 0 0 : 1 1 1 1 : 0 0 D1 0 0 : 1 1 1 1 : 0 0
LSB
D0 0 1 : 0 1 1 0 : 1 0
FUNCTION
Treble Steps -15dB -14dB : -1dB 0dB 0dB +1dB : +14dB +15dB Treble Center Frequency 10.0KHz 12.5KHz 15.0KHz 17.5KHz must be "1"
Bass Filter (subaddress 3H) MSB
D7 D6 D5 D4 0 0 : 0 0 1 1 : 1 1 0 0 1 1 0 1 0 1 0 1 D3 0 0 : 1 1 1 1 : 0 0 D2 0 0 : 1 1 1 1 : 0 0 D1 0 0 : 1 1 1 1 : 0 0
LSB
D0 0 1 : 0 1 1 0 : 1 0 Bass Steps -15dB -14dB : -1dB 0dB 0dB +1dB : +14dB +15dB Bass Q-Factor 1.0 1.25 1.50 2.0 Bass DC Mode off on
FUNCTION
22/28
TDA7400D
Soft Mute and Bass Programming (subaddress 8H) MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0 0 1 0 0 1 1 0 1 0 0 1 1 1 0 1 0 1 1 0 1 0 1
FUNCTION
Mute Enable Soft Mute Disable Soft Mute Mutetime = 0.48ms Mutetime = 0.96ms Mutetime = 40.4ms Mutetime = 324ms Stereodecoder Soft Mute Influence = on Stereodecoder Soft Mute Influence = off Bass Center Frequency Center Frequency = 60 Hz Center Frequency = 70 Hz Center Frequency = 80 Hz Center Frequency = 100Hz Center Frequency = 150Hz (1) Noise Blanker Time 38s 25.5s 32s 22s
0 0 1 1
0 1 0 1
1 Only for Bass Q- Factor = 2.0
Stereodecoder (subaddress 9H) MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0 0 1
FUNCTION
STD Unmuted STD Muted In Gain 8.5dB In Gain 6dB others combinations not used must be "1" Forced Mono Mono/Stereo switch automatically Noiseblanker PEAK charge current low Noiseblanker PEAK charge current high Pilot Threshold HIGH Pilot Threshold LOW Deemphasis 50s Deemphasis 75s
0 1 1 0 1 0 1 0 1 0 1
1 0
23/28
TDA7400D
Noiseblanker (subaddress AH) MSB
D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1
LSB
D0 0 1 0 1 0 1 0 1
FUNCTION
Low Threshold 65mV Low Threshold 60mV Low Threshold 55mV Low Threshold 50mV Low Threshold 45mV Low Threshold 40mV Low Threshold 35mV Low Threshold 30mV Noise Controlled Threshold 320mV Noise Controlled Threshold 260mV Noise Controlled Threshold 200mV Noise Controlled Threshold 140mV Noise blanker OFF Noise blanker ON Over deviation Adjust 2.8V Over deviation Adjust 2.0V Over deviation Adjust 1.2V Over deviation Detector OFF
High Cut (subaddress BH) MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0 0 1
FUNCTION
High Cut OFF High Cut ON Max. High Cut 2dB Max. High Cut 5dB Max. High Cut 7dB Max. High Cut 10dB VHCH at 42% REF 5V VHCH at 50% REF 5V VHCH at 58% REF 5V VHCH at 66% REF 5V VHCL at 16.7% VHCH VHCL at 22.2% VHCH VHCL at 27.8% VHCH VHCL at 33.3% VHCH Strong Multipath influence on PEAK 18K OFF ON (18K Discharge if VMPOUT <2.5V)
0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1
24/28
TDA7400D
Fieldstrength Control (subaddress CH) MSB
D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1
LSB
D0 0 1 0 1 0 1 0 1
FUNCTION
VSBL at 29% REF 5V VSBL at 33% REF 5V VSBL at 38% REF 5V VSBL at 42% REF 5V VSBL at 46% REF 5V VSBL at 50% REF 5V VSBL at 54% REF 5V VSBL at 58% REF 5V Noiseblanker Field strength Adj 2.3V Noiseblanker Field strength Adj 1.8V Noiseblanker Field strength Adj 1.3V Noiseblanker Field strength Adj OFF Quality Detector Coefficient a = 0.7 Quality Detector Coefficient a = 0.85 Quality Detector Coefficient a = 1.0 Quality Detector Coefficient a = 1.15 Multipath off influence on PEAK discharge -1V/ms (at MPout = 2.5V
Configuration (subaddress DH) MSB
D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1
LSB
D0 0 1 0 1
FUNCTION
Noise Rectifier Discharge Resistor R = infinite R = 56k R = 33k R =18k Multipath Detector Bandpass Gain 6dB 12dB 16dB 18dB Multipath Detector internal influence ON OFF Multipath Detector Charge Current 0.5A Multipath Detector Charge Current 1A Multipath Detector Reflection Gain Gain = 7.6dB Gain = 4.6dB Gain = 0dB disabled
25/28
TDA7400D
Stereodecoder Adjustment (subaddress EH) MSB
D7 D6 D5 D4 D3 D2 0 0 0 : 1 : 1 0 0 0 : 1 1 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1 D1 0 0 1 : 0 : 1
LSB
D0 0 1 0 : 0 : 1
FUNCTION
Roll Off Compensation not allowed 19.6% 21.5% : 25.3% : 31.0% Level Gain 0dB 0.66dB 1.33dB : 10dB must be "1"
Testing (subaddress FH) MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
FUNCTION
Stereodecoder test signals OFF Test signals enabled if bit D5 of the subaddress (test mode bit) is set to "1", too External Clock Internal Clock Testsignals at CASS_R VHCCH Level intern Pilot magnitude VCOCON; VCO Control Voltage Pilot threshold HOLDN NB threshold F228 VHCCL VSBL not used not used PEAK not used REF5V not used VCO OFF ON Audioprocessor test mode enabled if bit D5 of the subaddress (test mode bit) is set to "1" OFF
0 1
Note : This byte is used for testing or evaluation purposes only and must not be set to other values than the default "11111110" in the application!
26/28
TDA7400D
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO28
8 (max.)
27/28
TDA7400D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia Belgium - Brazil - Canada - China Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
28/28
|
