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An 'open secret may sound like a contradiction in terms but it is an accurate description of the ST100 embedded processor core, which was publicly unveiled at the Embedded Processor Forum, held in May in San Jose, California. Rumors that ST would be announcing a major new architecture had been circulating in the industry for many months but details of this innovative core had necessarily been restricted to a few key customers that had played an important role in its development.  As a result, the presentation by Didier Fuin, the ST100's chief architect, was an eagerly awaited event at the Forum and the audience was not disappointed. Handling both DSP and microcontroller tasks, the ST100 is designed to offer 'future-proof' state-of-the-art performance thanks to a scaleable architecture with multiple instruction sets. Although there are many different DSP and MCU architectures on the market, the great majority are derivatives of architectures that were designed several years ago. This was before the age of real system-on-chip integration and when market segments were more clearly differentiated and time-to-market did not have the crucial significance that it has today. At present, designers of many different kinds of end product, from hard disk drives and cellular phones to engine management systems and multimedia products, all face the same challenge - combining unprecedented levels of performance with aggressive price targets and the shortest possible product development time. According to Jean-Claude Michalina, General Manager of ST's DSP and Micro Division, the goal of the ST100 program was not only to deliver industry-leading performance but also to make it easy for customers to exploit this performance in times compatible with the short product cycles of the fastest moving markets. To achieve this, ST worked closely with a number of key customers in different fields such as telecommunication, computer peripherals and automotive. The result is a new architecture tailored to the real needs of customers. MULTIPLE INSTRUCTION SETS Historically, DSPs were developed to accelerate complex arithmetical calculations and their architectural evolution was driven by this specific goal rather than overall system control functions. As a result, many applications need both a DSP engine and a microcontroller, whether the MCU is embedded on the same chip as the DSP core or is provided externally. In a cellular phone, for example, the DSP performs baseband processing while the MCU handles the user interface and overall system control. By simultaneously supporting both MCU and DSP code, the ST100 removes the need for a combination of DSP and micro cores in many applications, reducing cost and simplifying design. In addition, the first ST100 will be based on a 32-bit Load/Store architecture for both MCU and vector DSP code. The fully scaleable architecture enables a wide range of implementaons to be based on the same basic architecture and tools: from low power versions for portable products to very high performance devices with a high degree of internal parallelism. The world-wide market for cellular/PCS telephone handsets is forecast to be 308 million units by 2002 with handset production forecasted to grow at 20.7% CAGR over the same period. Additionally, the semiconductor market for cellular/PCS telephone handsets is forecasted to grow to $11.76 billion by 2002." Source: Dataquest In fact, the ST100 offers three selectable fixed length instruction sets, with dynamic switching between tham. Two MCU instruction sets are provided: a 16-bit set for routines where code compactness is essential and a separate set of 32-bit MCU instructions for routines needing maximum performance. For signal processing, a 4x32 SLIW instruction set is provided and switching between instruction sets is easily performed by software instructions or by an external event so that the ST100 core can be interrupt driven in different modes. Another key benefit of the ST100 is that it has been designed to achieve maximum code efficiency for both serial MCU code and vector DSP code even when programmed in C. Its sixteen 40-bit data registers correspond directly to C data types and allow high precision results. There are also seventeen 32-bit pointer/index registers that provide easy data access and three hardware loop controllers that automate repetitive loops, all managed using C code. Nearly all of the instructions in the ST100 are predicated i.e. the instruction is conditionally executed depending on the state of a specified guard bit. This provides a high degree of code compactness and eliminates the need for conditional branches. These compiler-friendly instruction sets mean that most performance-critical DSP routines can be compiled directly from C without resorting to manual coding or optimization.   HOW MANY PROCESSING UNITS DO YOU WANT? An important characteristic of the ST100 is the scaleable core parallelism, which means that the computation resources, including the number of processing units, the number of working/control registers and the bandwidth, are scaled at the time of implementation. The first implementation, called the ST100-4W, will include 5 processing units, 32 working registers and 16 control resistors. Target performance of this core is to deliver performance of 2400 MIPs, 600 Mega MAC/s and 7.2Gbytes/s internal memory bandwidth in a 300MHz static design with a 1.8V supply and using 0.18 micron CMOS technology. A 100MHz/1V version of the ST100-4W is expected to achieve 800 MOPs/s and 200 Mega MACs/s with a 2.4Gbytes/s internal memory bandwidth. The interrupt response time will be 14 CPU cycles for standard interrupts and 7 CPU cycles for fast interrupts. To support the ST100 architecture ST will provide a comprehensive package of tools, including efficient C compiler, state-of-the-art multi-core emulation, a real-time operating system and integrated co-development tools that allow fast time to market and design reuse. The C compiler includes a powerful optimizing capability for signal processing loops, a very efficient back end for optimizing hand written code, profiling feedback and power debug features. The ST100 software toolset is scheduled for introduction in the third quarter of 1999, with the first core silicon following in Q4. The first commercial product - a custom system-on-chip device - is expected to be delivered at the end of 1999. Although ST does not participate in the stand-alone, general purpose DSP market, the Company has more than ten years experience in developing and applying state-of-the-art DSP techniques internally for custom, semi-custom and standard products. This expertise has been combined with the applications know-how of several strategic partners, with the result that the ST100 represents a major step forward in DSP integration.  |
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