 Embedded systems have invaded our lives. From the dishwasher to the anti-lock breaking system of our cars, from cell phones to DVD players, they are everywhere. While there was a time where hand-written assembly code was the only option to program a processor, the complexity of today's application makes this reasonable only for the critical parts. Compilers and software tools play an increasingly important role. This is especially true for VLIW processors: they have minimal hardware in order to reduce the cost, and they rely on the compiler to squeeze performance out of an application.
This issue of the ST Journal of Research is representative of the wide spectrum of activities in embedded systems that spans from pure hardware to pure software. Their tight interaction is an inescapable trend. Systems no longer consist of a single microcontroller. They are now full computing systems containing several processors, hardware accelerators, buses, memories, and peripherals. A system-level approach is necessary to design such systems and address simultaneously the challenges of the hardware, the operating system and the applications. In the first paper, Karim et al. present a new multi-core architecture called the "multi-level computing architecture". It is the equivalent of a superscalar architecture, but one degree of parallelism higher, with a controller issuing tasks in parallel on several processors. Development and analysis tools are the key to time-to-market. This means that tools need to be quickly adapted while the architecture is being developed, so that the designers can get meaningful feedback. In the second paper, De Paoli et al. present FlexPerf, a profiling tool generator. From the description of a system to analyze, a targeted profiling tool can be obtained, along with a software development kit. But performance is not all. In embedded systems, code size is also a major issue, that directly relates to cost. The next two papers address different aspects of it. Piccinelli and Sannino explore a code software-based compression technique with a hardware-based mechanism for decompression. Leair gives a detailed overview of the compiler optimization techniques available for the ST100 processor that trade performance for code size. The following three papers present innovative compiler technologies being developed in STMicroelectronics. First, because the likely consequence of larger code size is the degradation of the cache behavior, Garatti considers optimizing the layout of the functions in a binary file in order to reduce the number of conflicts. Then, Daveau et al. present their retargetable register allocation framework. Finally, Rastello et al. explain how they deal with the "static single assignment" form, a modern internal representation used in compilers. In the eighth paper, Costa et al. study the relationship between compiler optimizations and the processor they target. They show how the effectiveness of some code optimizations depend on the target processor, but also on the accuracy of the analyses performed. Finally, Dupont de Dinechin shows in his Special Report how techniques borrowed from another fields, e.g. machine scheduling, can be successfully applied to compilation. As illustrated in this issue of the journal, the complexity of embedded systems keeps increasing. More and more competences are needed to design and build such systems. Only the companies that master this broad spectrum of activities have a chance to be successful in designing the next generation of embedded systems.
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