| Vol. 1, No. 2, September 2004 - Art. 3 |
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| Code Compression for VLIW Embedded Processors |
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by
Emiliano Piccinelli, Roberto Sannino (STMicroelectronics)
Copyright
Copyright 2004 © Society of Photo-Optical Instrumentation Engineers - Reprinted, with permission, from the proceedings of the IS&T/SPIE Symposium on Electronic Imaging 2004. |
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Abstract
The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area size. On the other side, the functions to be performed by new terminals require more computational flexibility and effort. Longer code streams must be loaded into memories: this might represent a real issue for DSPs or CPU applications, because memories are power consuming and cost expensive. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) is able to reduce the dimensions of the program memory. It can run offline and work directly on the binary code generated by the compiler, compressing it and generating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core.
Comparisons versus the state-of-the-art IBM Codepack algorithm are presented, together with its architectural implementation into the ST200 VLIW core. |
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