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ST Journal of Research
Wireless Sensor Networks
Vol. 4, No. 1, May 2007 - Art. 10
 
An ultra-low energy asynchronous processor for Wireless Sensor Networks
image: processor workflow

by
L. Necchi, L. Lavagno , Politecnico di Torino; D. Pandini, Laura Vanzago, STMicroelectronics

Copyright
Copyright © IEEE, 2006.Reprinted, with permission, from: "An ultra-low energy asynchronous processor for Wireless Sensor Networks", by L. Necchi, L. Lavagno, D. Pandini, L. Vanzago, Proceedings of ASYNC 2006 - 12th IEEE International Symposium on Asynchronous Circuits and Systems, March 13-15, 2006, Grenoble, France
 
Abstract
This paper describes the design flow used for an asynchronous 8-bit processor implementing the Atmel AVR instruction set architecture. The goal is to show dramatic reductions in power and energy with respect to the synchronous case by exploiting aggressive dynamic voltage scaling, while achieving almost the same area, delay, and power at the same voltage as normal synchronous operation, and while retaining a traditional design flow. The processor was implemented in a 130nm technology using desynchronization, starting from an initial design downloaded from OpenCores.org. It consumes 14pJ per instruction to deliver 170 MIPS at 1.2 V and 2.7 pJ per instruction to deliver 48 MIPS at 0.54 V.
It thus dramatically improves the energy consumed per instruction with respect to previous results from the literature.
 
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