SGS-THOMSON, the world's number one supplier of EEPROM memories, has
announced the availability of the M39432, a product that combines a 4Mbit FLASH
memory and a 256Kbit parallel EEPROM memory on the same chip. Designed for use
in cellular phones and other hand-held portable equipment where designers have
up till now been forced to use separate FLASH and EEPROM memories, the M39432 is
the first of a series of FLASH+ memories built with a proprietary technology
that combines the functionality of EEPROM with the cost-effectiveness of a
single-transistor FLASH process.
Housed in a 40-pin TSOP package, the M39432 allows the two separate devices
currently required to be replaced by a single device without any loss of
functionality; the flash memory is a 4Mbit array with sector protection and
erase suspend/resume features while the EEPROM is a full featured 256Kbit memory
with software data protection, 64 byte page mode and enhanced end-of-write
detection. Because both memory functions are implemented in the same technology,
much of the support circuitry that would be duplicated in discrete flash and
EEPROM devices, including charge pumps for on-chip generation of the programming
voltage, address logic, state machine and I/O buffers, is shared.
The M39432 offers substantial benefits compared with the alternative
technique of emulating the EEPROM function in a flash memory. The emulation
method involves storing “EEPROM” data as linked lists in a sector of
the flash memory, with a second sector reserved to take over when the first
sector becomes full. To access an “EEPROM” location, the host
processor performs a series of reads from the bottom of the linked list until it
locates the final value. Every time the data is changed, the time taken to
access it again increases. In addition, simulation requires about 16Kbyte of
software that must run on the host processor and around 4Kbyte of code that must
be copied to external RAM.
The M39432 eliminates this cumbersome procedure by offering concurrent
operation of the FLASH and EEPROM functions. Because the EEPROM block manages
its write cycle internally once the host controller has issued the Program
command, the host controller can read the flash memory while an EEPROM write
cycle is in progress. Other immediate benefits include lower component and
inventory management costs, reduced PCB area, greater reliability (thanks to the
reduction in the number of solder joints) and lower power consumption.
FLASH+ technology is based on a standard 0.6 micron FLASH memory process
with proprietary enhancements to yield a double poly/double metal process that
is a little more complex than the industry standard double poly/single metal
EEPROM process but provides significantly greater memory densities. The process
is also being used to build high density parallel EEPROMs.
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