All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity from transient excess voltages. The STCCP27 is characterized for operation over the commercial temperature range of -40°C to + 85°C.
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Innovative Package µTFBGA25 |
The device packaging is especially designed with minimum dimensions to suit the space-constrained implementations in mobile phones.
It is packaged in an innovative µTFBGA25 package with a pitch of 500µm. The STCCP27TBR is now available in a 3mm x 3mm, 25 pin, µTFBGA lead-free package (RoHS Compliant – Restriction on Hazardous Substances). It will be shipped in standard 7” reels with 3000pcs per reel. |
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Sub-Low Voltage Differential Signaling (subLVDS) Inputs: V
ID = ±150mV;
V
IC = 900mV;

High data rate: DR=208Mbps, Compliant with
SMIA CCP1; DR
MAX=416Mbps with fIN-MAX=416MHz;

Operating voltage and I/O reference voltage:
V
DD=2.65V to 3.60V;

Bidirectional I
2C level Shifter between VDD and
V
L: V
L=1.65V to 1.95V;

Low power consumption: I
DD+I
L=10µA (disabled);

Lead-free µTFBGA package.
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Functionality Application Details |
The device supports two different modes of functioning; formatted (ENABLED_SYNC) and unformatted (DISABLED_SYNC) transmission of data on the data lines based on the selection of the SYNC_SEL control pin by the Baseband processor. The two modes differ in the way the Baseband processor recognises the Image/Video byte positioning.
In the ENABLED_SYNC mode (SYNC_SEL = VL), the Horizontal Sync and Vertical Sync signals are extracted from the serial input data stream before transmitting the 8-bit video/pixel data on the parallel output, D1-D8 in STCCP27. Instead the extracted Horizontal and Vertical sync signals are then transmitted separately. This mode is meant for simpler baseband/multimedia image processors to make their image processing easier.
Application block diagram |
In the DISABLED_SYNC mode (SYNC_SEL = Gnd), the timing signals (HSYNC and VSYNC) are not extracted from the input data stream, baseband processor recovers the timing information from the embedded sync words (SOF, EOF, SOL, EOL) in the 8-bit parallel data output.
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P / N |
Datarate |
I/O signals |
SMIA LEVEL |
Package |
STCCP27TBR |
208Mbps |
2.65V - 3.6V |
Class 0 CCP1 |
µTFBGA25 |
STSMIA832* |
650Mbps |
1.65V - 1.95V |
Class 0,1,2 CCP1/2 |
*Under Development