Products
ST Home | Application Specific for Communication & Connectivity | Wireline Communication ICs | Ethernet | FAQ

Frequently Asked Questions on STE10/100A
STE10/100A - Drivers
1 Are there drivers available for the STE10/100A and where can they be found?
2 Is the source code for the Windows CE driver for the STE10/100A available? Where can we obtain the Win CE development environment?
3 Are the drivers DEC/Intel compatible?
4 Can the Linux driver be recompiled in order to use it for another version of the Linux kernel? What is the command needed to do so?
5 With regards to the VxWorks driver: Are st_config.c, steEnd.h and SteEnd.c BSD4.4 compatible? Can it be used with Tornado 1.0 / 2.0 and where do you store the driver files?
 
STE10/100A - Reference Design NIC card/Board
1 The STE10/100 PCI card does not completely power up and refuses to boot up. Why?
2 What is the list of vendors for the transformers that are tested by ST while using the STE10/100A?
3 Could you explain in more detail about the ferrite beads used on the board design?
4 PCI tests run successfully, but the transmitter lines coming directly from the chip are both always at low level. Why?
5 Is there a formula in programming EEPROM of the STE10/100A? Where can this info be found?
 
STE10/100A - Reference Design NIC Schematic
1 Do you have the ORCAD files for the reference design for this device?
2 On the STE10/100A reference design NIC schematics, there are two optional connections for the PME pin. One is a straightforward connection the other uses an NPN transistor and a couple of resistors. Explain when to use what.
3 On the STE10/100A reference design NIC schematics, what are resistors R28, R30 and R34 for?
4 What is the purpose of the resistors R32/R33?
 
STE10/100A - Miscellaneous
1 What is the meaning of the "heartbeat fail" bit in the transmitter descriptor TDESO?
2 What parts of the MAC frame must be loaded in the transmit buffer?
3 Does the STE10/100A have an interface to the IDE/ATA bus used by hard disk drives?
4 Does the PCI interface operate below 20MHz? Is the PCI clock asynchronous to the Ethernet clock or some relation thereof?
5 Does the STE10/100A support Perfect Address capability?
6 Is loopback capability supported on the MAC and on the PHY in the STE10/100A?
7 Is VLAN supported? If not, then will the chip allow pass the VLAN packets to pass without generating an error?
8 The STE10/100A datasheet mentions the TL bit in the Receive Buffer?
9 Does the chip support the Ethernet MIB counters on the MAC side?
10 Does the chip support Pause Frame generation?
11 Does it support both the IEEE 802.3 and Ethernet 2 DIX frames?
12 Does it support bridging tables? Can it construct bridging tables on it's own?
13 Does the STE10/100A support multicast address filtering? How can we setup multicast address table on STE 10/100A?
14 Is there any performance advantage to having TX and RX FIFO size of greater than the 2K bytes, which is what is used by the current STE10/100A?
15 Is there a JTAG port in the STE10/100A? Is there any scan in the PHY?
16 Where can I find info on how to program the Boot ROM pins as MII interface pins?
17 Can the STE10/100A be interfaced to a HPNA PHY?
18 Do you have Ethernet test conformance available?
19 What kind of EEPROM does the STE10/100A use? Can the application use current MLC flash and EEprom as bootprom/flash or is there a need for a separate flash/eeprom?
20 Is it possible to configure the devices, so that they are able the get their info via the PCI bus?
21 What can be done if an application has unused pinning of the ROM interfaces?
22 Can interrupts be generated for the LinkUp - cable plugged using Auto Negotiation?
23 When the transmit jabber timeout occurs and the transmit underflow and the receive descriptor unavailable are set, is the Tx and Rx activity stopped? What is the way to restart the Rx and Tx?
24 What is the purpose of the receive watchdog?
25 What is the purpose of the transmit threshold count in csr6 and store forward functionality?
26 What is the purpose of the back off counter in csr6?
27 What is the purpose of the receive threshold enable in csr18?
28 What is the relation between PB and PR bits of csr6? Could I disable PR and still enable PB?
29 What is the difference between a longword as opposed to a double word as it is interchangeable used in the STE10/100A technical documentation while referring to the TX and RX descriptors?
30 What is the purpose and function of pins 88 - VCC-DETECT and 89 - VAUX-DETECT , and how should they be connected if the Wake On LAN feature is not used, such that there is no power available to the device when the application is turned off?
 

Related Topics
Product Selector & Datasheets
Application Specific for Communication & Connectivity
Support
Contact Technical Support
FAQ
Lead Free/RoHS