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Application Specific for Computer & Peripherals | Customizable Processors for Computer & Peripherals | Customizable Application Processors | SPEAr Family Customization Process

SPEAr® Family Customization Process

The customization process is divided in 2 steps:
 
Project creation
Starting from the user defined logic (RTL), two customization ways are given to the customer: through behavioral model and through external FPGA.
 
Customization through behavioral model
- ST provides behavioral model of the fixed architecture allowing the final user to verify custom logic
- Verification procedure is the same as a standard ASIC flow
Customization through external FPGA
- SPEAr is predefined to allow an easy link to an external FPGA
- Custom logic is mapped in FPGA to allow emulation
- eASIC® / Lightspeed® block is programmated using user RTL
 

Sample release and Mass-Production

Once the user project is completed, the RTL (or the FPGA database) is released to ST who will start the customization flow.

In details, it implicates:

1. SYNTHESIS and PLACE & ROUTE (2 weeks)
2. Sign-Off and SIMULATION (2 weeks). Only after the sign off by the customer, ST proceeds in the customization flow
3. After 4 weeks the customer gets samples.
If the customer is satisfied with his project, a mask making database is released for the last steep: MANUFACTURING ASSY and TEST; it takes other 3 weeks. Otherwise, if he wants to modify something, the customer can buy a further customization.


eASIC®
is a registred trademark of eASIC Corporation in the United States.
Lightspeed®
is a registred trademark of Lightspeed Logic, Inc. in the United States and other countries.