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SPEAR-09-H022

SPEAr Head - ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC
 
Datasheet
Reference Filesize Pages Last Updated
SPEAR-09-H022 1056KB

71

30/03/2006
 
Orderable Products
Device Status RoHS Package Purchase
SPEAR-09-H022 Preview Converted PBGA420
Features and Description
ARM926EJ-S @ 266 MHz with MMU
200K equivalent customizable ASIC gates (16K Lut equivalent) with 8 channels DMA and 112 dedicated GP I/Os
Multilayer AMBA 2.0 compliant Bus @ 133 MHz
Programmable internal clock generator with enhanced PLL function, specially optimized for E.M.I. reduction
16 KB single port SRAM embedded
16 bit DDR and 32 / 16 bit SDRAM interfaces
SPI interface connecting serial ROM and Flash
Ethernet 10/100 with MII management interface
USB 2.0 Device + PHY interface
Two independent USB 2.0 Host ports with their PHY interface
Three UARTs
I²C
6 General Purpose I/Os
Real Time Clock
Watchdog
4 General Purpose Timers
ADC 8 bits, 230 Ksps, 16 analog input channels
Operating temperature: - 40 to 85 °C
Package: PBGA 384+36 6R 23x23x1.81 mm
SPEAr™ Head is a powerful SoC based on 110 nm HCMOS technology and consists of two main parts: an ARM9 architecture and an embedded customizable logic block. The ARM architecture relieves users from developing a complete RISC platform; it includes a high performance ARM926EJ-S processor, which makes SPEAr™ Head compliant with Linux and WindowsCE OSs, a fast AMBA 2.0 bus structure and a large IP portfolio that provides both high and low speed connectivity, static and dynamic memory controllers (supporting also DDR) and 16 KB of single port SRAM.

The embedded customizable logic block allows users to design custom projects. It consists of an embedded macro where it is possible to map up to 200K equivalent ASIC gates, with 2 dedicated DMA blocks to speed up the data flow with the main memories, 8 interrupt lines and 112 dedicated general purpose I/Os.

In order to allow an easy and quick implementation of the custom project, a rich development kit is available, composed by a development board, software supports and detailed documentation.

SPEAr™ Head is a high performance digital engine optimized for embedded applications. Thanks to its features and the available development support, it can be use for a wide range of different purposes and allows a time to market of few weeks with an unprecedented cost saving.
Technical Documents (PDF Files)
Datasheet
Reference Filesize Pages Last Updated
SPEAR-09-H022 1056KB

71

30/03/2006
Data Brief
Reference Filesize Pages Last Updated
SPEAR-09-H022 246KB 7 13/12/2005
Development Tool Products
Development Kit SPEAr Head SPEAr Head Development Kit
Product Page

Downloads
Type Reference Description Last Update Filesize
Linux Support Package SPEAr Head200 Linux Kernel Source Tree for SPEAr Head Development Board 11/21/2006 38MB
Boot loader SPEAr Head200 Uboot for SPEAr Head Development Board 11/21/2006 6MB