SPEAR-07-NC03

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Reference	Filesize	Pages	Last Updated
SPEAR-07-NC03	1541KB	193	01/03/2006

Device	Status	RoHS	Package	Purchase
SPEAR-07-NC03	Active	Converted	LBGA180

	ARM720T with MMU
	AMBA 2.0 compliant Bus
	Clock Generator
	8 KB SRAM on-chip memory
	DRAM controller SDRAM / EDO
	Static memory controller for ROM, Flash, SRAM up to 2 banks – 16 MB each
	Ethernet 10/100
	Full-Speed USB Host + PHY
	UART
	I²C
	IEEE 1284 host controller
	12 General Purpose I/Os (IEEE 1284 included)
	Real Time Clock
	Watchdog
	General Purpose Timer
	Operating temperature range: -40 to 105 °C
	Package: LBGA180 (12x12x1.7 mm)

SPEAr™ Net is a SoC based on ARM720T, riches of the most common connectivity IP’s and with 8 KB of SRAM on-chip available to manage data flow between the internal AMBA Bus and the external static memory cuts.

As general purpose member of the family, it provides a SMART bridge between different interfaces and is ideal foe entry-level consumer applications, industrial control and networking products, medicals equipments and any other applications that require a proven ARM-based architecture and a full range operating temperature.

SPEAr™ Net is delivered with a full-features starter kit, including SW libraries, reference design PCB board and detailed documentation, in order to enable a fast and easy development.

Reference	Filesize	Pages	Last Updated
SPEAR-07-NC03	1541KB	193	01/03/2006

Type	Reference	Description
Starter Kit	SPEAr Net	SPEAr Net Starter Kit Product Page