| 64-bit superscalar MIPS based microprocessor |
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| Datasheet |
| Reference |
Description |
| STLS2F01 |
900 MHz 64-bit superscalar MIPS based microprocessor |
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| Orderable Products |
| Device |
Package |
Packing Type |
| STLS2F01 |
PBGA452 (35 x 35 x 2.33 mm) |
Tray |
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| Features and Description |
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Up to 1 GHz clock frequency (typical conditions) |
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CMOS 90 nm process |
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27 x 27 flip chip BGA package |
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Power consumption: 4 W @ 1.0 GHz, 1.2 V |
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New Streaming Multimedia instruction set support (SIMD) |
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64 KB instruction cache, 64 KB data cache, onchip |
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Integrated 64-bit DDR2-667 memory controller |
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Integrated PCI 66 MHz/PCI-X 133 MHz |
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Integrated Limited Video Accelerator : YUV->RGB, Out Video resizing, Overlay |
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MIPS based, MIPS III compatible instruction set |
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SIMD Multimedia extensions (SSE & SSE2 like) |
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The STLS2F is a MIPS® III compatible 64-bit superscalar microprocessor, able to issue four instructions per clock cycle among six functional units: two integer, two single/double-precision floating-point, one 64-bit SIMD and one load/store unit.
The microarchitecture is organized with nine pipeline stages and support for dynamic branch prediction. The memory hierarchy consists of a first level 64KB 4-way set associative cache for instructions and data, a second level 512KB unified 4-ways set associative cache and the memory management unit with table lookside buffer.
The STLS2F evolved from the STLS2E, and contains enhanced I/O and memory accessing bandwidth, as well as a software-managed frequency changing scheme. The STLS2F has a standard 32-bit PCI/PCI-X interface, a standard 64-bit DDR2 interface, an 8-/16-bit local IO interface and a 4-bit GPIO interface. The STLS2F achieves higher memory accessing bandwidth by utilizing a 64-bit DDR2 memory controller.
Compared to its predecessor, the STLS2F provides better power management by using a software-managed working frequency changing scheme. The operating system utilizes this feature to change the processor frequency according to the workload. The STLS2F integrates a video acceleration module in its write data path to the PCI/PCI-X controller.
Coupled with software drivers, the video acceleration module can transfer YUV format video data to RGB format and zoom automatically. This capability greatly reduces the processor's workload when the system utilizes a simple VGA controller.
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| Loongson CPU |
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| Technical Documents (PDF Files) |
| Data Brief |
| Reference |
Description |
| STLS2F01 |
900 MHz 64-bit superscalar MIPS based microprocessor |
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