With the size of DC-DC converters continuing to shrink, it has become a challenge to dissipate the heat generated by various components on the PCB.
Advances in packaging need to be developed in tandem with silicon technology improvements. The PolarPAK package, with its superior thermal handling capability,represents a remarkable evolution in assembly technology allowing designers to increase efficiency and power density.
This package technology complements ST’s range of STripFET MOSFETs optimized for power conversion in computer, datacom, and telecom applications. |
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PolarPAK is a registered trademark of Vishay/Siliconix |
| Excellent heat dissipation |
ST’s latest low voltage STripFET™ technology brings unbeatable value with silicon-inherent on-resistance and total gate charge. Both of these parameters are very important factors for achieving the highest efficiency, but without the appropriate packaging solution the overall design is simply not complete.
More power in the same sized or smaller package can be obtained by reducing the thermal resistance, and adding more exposed metal to the device design, in order to enhance its thermal dissipation.
ST has offered various solutions comparable in size to the SO-8 package. For example the PowerFLAT5x6 provides a low thermal resistance path from the die to the PCB via a metal pad placed at the bottom of the package. |
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| Effective manufacturing |
The new package’s leadframe and plastic encapsulation are similar to those used for most standard power MOSFET packages, ensuring good die protection and easy handling in manufacturing. Yet compared with the standard SO-8, the metal-topped PolarPAK package dissipates heat so efficiently from both the top and the bottom of the package that it can handle twice the current within the same footprint dimensions.
With a footprint no larger than a standard SO-8 or PowerFLAT5x6, this new package allows increased power handling with just a simple forced-air cooling system. Further improvement is also possible with a low-cost heat sink placed on the top of the package.
The power handling capability of the PolarPAK is 30% higher than the PowerFLAT5x6, and 73% higher than the SO-8. |
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Package |
PD
[W] |
Rthi-pcb
[°C/W] |
Rthj-c
(bottom)
[°C/W]
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Rthj-c
(top)
[°C/W] |
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PolarPAK |
5.2 |
24 |
2.7 |
0.8 |
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PowerFLAT5x6 |
4 |
31.2 |
1.56 |
12 |
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SO-8 |
2.5 |
50 |
- |
- |
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| Top View |
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| PolarPAK benefits |
| Power handling and performance features yield the following benefits: |
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Double current density (>60A) resulting in space and cost reduction; |
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Low operating temperature, which will have an affect on the efficiency and reliability. The lower junction temperature means lower RDS ON, which in turn means higher efficiency and increased lifetime reliability; |
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Better die protection and reliability, easy handling manufacturability, and fixed footprint and pad layout; |
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Low parasitic inductance; |
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Multi-source design which gives customers flexibility; |
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Compatible with existing SMD manufacturing equipment. |
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| Applications |
PolarPAK package technology complements ST’s extensive selection of STripFET MOSFETs which are optimized for power conversion in computer, datacom, and advanced telecommunications applications. Specifically, these new products are designed for high frequency DC-DC converters used to power the next Intel® and AMD processors designed into high-end notebooks and servers.
With the introduction of ST’s PolarPAK, there is now a broad range of products available to fulfil any kind of customer requirements, from the standard SO-8 to the new double-sided cooling package. This flexibility is a great advantage for the customer who really has to have the suitable, comprehensive solution. |
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| PolarPAK datasheets and product selector |
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Features |
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50% thinner than SO-8 package |
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Fully encapsulated silicon |
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Same footprint as a standard SO-8 package |
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Low profile (0.8 mm) |
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Top and bottom heat dissipation paths |
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Superior thermal performance |
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Higher power density |
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Multiple sourcing |
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Low parasitic inductance |
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Overall reduced system size |
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Absence of wires connecting the silicon to the fame reduces noise on the circuit |
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Maximum design flexibility due to fixed footprint and pad layout |
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| Design resources |
PolarPAK PSpice models |
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| Related Information |
| Promotional documents |
| Title |
Reference |
Power MOSFETs selection guide
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SGMOS0209 Download (Oct. 2007, 893 Kb)
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N-Channel (12V to 40V)