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ST has introduced a new state-of-the-art technology tailored to the high-side function in DC-DC converters. This new STripFET III process, (internally known as “SP3”), utilizes the latest generation of ST’s planar technology and is optimized for high switching frequency applications, even up to 700kHz and 1MHz.
This technology shows excellent dynamic performance in conjunction with optimized packages. It is possible to reach very good static behaviour, obtaining a figure of merit, RDS(on) * Qg, below 100mOhm * nC in an SO-8 package. |
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STripFET III (SP3) technology allows manufacturers to increase the efficiency in their DC-DC converters thanks to:
 minimal gate charge;
low input capacitance;
low intrinsic gate resistance.
The low gate charge is obtained through a layout optimization, with a different contact opening for the P and N-zones. The reduction of the Rg parameter is realized with the introduction of cobalt silicide inside the poly of gate electrode.
| Figure of merit,
RDS(on) * Qg |
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Wide Package Range For Low Gate Charge STripFET III Products |
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The effective improvement in the technology has been combined with new package and bonding techniques. SO-8, PowerSO-8 (exposed pad) and the new PowerFLAT 3.3x3.3 are optimal solutions for portable computer applications, improving thermal performance and saving space. The same silicon is also available in standard packages such as DPAK and IPAK for motherboard applications.
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ST's StripFET III devices are in line with the best products present in the market in terms of static and dynamic behaviour. STS12NH3LL shows a lower gate charge than the competition, contributing to a further reduction in switching losses. Moreover STSJ50NH3LL, thanks to the improved package has a better thermal performance than any competing device.
P / N
in SO-8 |
BVDSS
[V] |
RDS(on) max
[mOhm]
|
Qg typ
[nC]
@ 4.5V |
@ 10V |
@ 4.5V |
|
|
30 |
13 |
10 |
9 |
Trench 1 |
30 |
12.5 |
9.1 |
9.3 |
|
Trench 2 |
30 |
13.5 |
9.1 |
10 |
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