AN2340 Application note
ST10 RPD pin: Functionality during Reset and Power Down mode
Introduction
RPD is a dedicated timing pin for the return from Power Down circuit. Additionally, when this pin is recognized low, a reset event is taken as asynchronous. This note gives advice on configuring the external circuitry connected to the RPD in order to make it work properly. The information contained in this document is valid for ST10F27x, ST10R27x, ST10F25x and ST10F296.
March 2006
Rev 1
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RPD functionality
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1
RPD functionality
RPD is a dual purpose dedicated pin. This section covers its functionality.
1.1
System reset and startup
Several ST10 reset events that may occur are summarized in the following table: Table 1. Reset event definition
Flag(1) PONR RPD Status Low Low LHWR Synchronous long hardware reset Synchronous short hardware reset Watchdog timer reset Software reset SHWR WDTR SWR High High
(2) (2)
Reset Source Power-on reset Asynchronous hardware reset
Conditions Power-on tRSTIN > 500ns tRSTIN > (1032 + 12) TCL + max (4 TCL, 500ns) tRSTIN > max (4 TCL, 500ns) tRSTIN (1032 + 12) TCL + max (4 TCL, 500ns) WDT overflow SRST instruction execution
1. Flags can be read in the WDTCON register 2. The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated.
Therefore, roughly, the RPD pin level distinguishes between an asynchronous (low level) and a synchronous reset (high level). The main difference between these two kinds of reset is that the first immediately cancels pending internal hold states and if any, it aborts all internal/external bus cycles whereas in the synchronous reset, after RSTIN level is detected, a short duration of a maximum of 12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are cancelled and the current internal access cycle, if any, is completed. For this reason, if an asynchronous reset occurs during a read or write phase in internal memories, the content of the memory itself could be corrupted. To avoid this, synchronous reset usage is strongly recommended. However, the asynchronous reset must be used during the power-on of the device. Depending on crystal or resonator frequency, the on-chip oscillator needs about 1ms to 10ms to stabilize with an already stable VDD. The logic of the ST10 does not need a stabilized clock signal to detect an asynchronous reset and is therefore suitable for poweron conditions. On the contrary, the reset state machine needs a stabilized clock to operate correctly. According to the length of pulse on RSTIN, the synchronous reset may be recognized as
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RPD functionality long or short. Long and Short synchronous reset differs by the start-up configuration bits latched: Long synchronous reset latches the entire Port0 configuration, including clock frequency selection (P0[15:13]) Shor t synchronous reset ignores the bits P0[15:13] and the same clock frequency is applied.
Refer to the product documentation for a full description of the reset mechanism. The RSTIN pin is an input of the device that can be configured as output that shows a low level during the internal reset condition. This is called the bidirectional reset and is enabled by setting the BDRSTEN bit in the SYSCON register. When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal for the duration of the internal reset sequence (synchronous/asynchronous hardware, synchronous software and synchronous watchdog timer resets). At the end of the internal reset sequence (1024 TCL) the pull-down is released. The figure below shows a simplified reset circuitry scheme. Please refer to the product user manual for more details and timings related to system reset. Figure 1. Internal (simplified) reset circuitry
EINIT instruction Clr Q Set RSTOUT
Reset state machine Clock
VDD
Internal reset signal
Trigger Clr
SRST instruction watchdog overflow
RSTIN
BDRSTEN Reset sequence (512 CPU Clock Cycles)
VDD Asynchronous reset
RPD From/to exit powerdown circuit Weak pull-down (~200A)
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RPD functionality
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1.2
Power down
To reduce power consumption, the microcontroller can be switched to Power Down mode. Clocking of all internal blocks is stopped, the contents of the internal RAM, however, are preserved through the voltage supplied via the VDD pins (and on-chip voltage regulator). The ST10 provides two different operating Power Down modes:
Protected Power Down mode Interruptible Power Down mode
The Power Down operating mode is selected by the bit PWDCFG in the SYSCON register. In the first case, the Power Down mode can only be entered if the NMI (Non Maskable Interrupt) pin is externally pulled low while the PWRDN instruction is executed and the only way to exit the Power Down mode is with an external hardware reset. In the second case, the Power Down mode can be entered if enabled Fast External Interrupt pins (EXxIN pins, alternate functions of Port 2 pins, with x = 7...0) are in their inactive level. This inactive level is configured with the EXIxES bit field in the EXICON register, as follows:
EXICON (F1C0H / E0H) 15 14 13 12 11 10 9 8 ESFR 7 6 5 4 3 Reset value: 0000H 2 1 0
EXI7ES RW
EXI6ES RW
EXI5ES RW
EXI4ES RW
EXI3ES RW
EXI2ES RW
EXI1ES RW
EXI0ES RW
Bit
Function External Interrupt x Edge Selection Field (x=7...0) `00': Fast external interrupts disabled: Standard mode. EXxIN pin not taken into account for entering/exiting Power Down mode. `01': Interrupt on positive edge (rising). Enter Power Down mode if EXiIN = `0', exit if EXxIN = `1' (referred to as `high' active level) `10': Interrupt on negative edge (falling). Enter Power Down mode if EXiIN = `1', exit if EXxIN = `0' (referred to as `low' active level) `11': Interrupt on any edge (rising or falling). Always enter Power Down mode, exit if EXxIN level changed.
EXIxES (x=7...0)
Interruptible Power Down mode can be exited by asserting either RSTIN or one of the enabled EXxIN pins (Fast External Interrupt).
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AN2340 Figure 2. Simplified power down exit circuitry
VDD D Q1 Enter Power Down cd Q exit_pwrd Pull-Up Q stop PLL stop oscillator VD D
RPD functionality
RPD Weak pull-down (~ 200 A) External interrupt Reset VDD D Q2 cd Q system clock Q en_clk_n CPU and peripherals clocks
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External RPD circuitry examples
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External RPD circuitry examples
To ensure that both functions explained in the previous chapter work correctly, external circuitry must be connected to the RPD.
2.1
RC network
A simple RC network can be connected to the RPD pin leading to correct behavior both during system reset and return from power down. The cases will be analyzed separately considering that the resistance R and the capacitor C are connected as in Figure 3.
2.1.1
System reset
On power-up, the logical low level on the RPD pin forces an asynchronous hardware reset when RSTIN is asserted low (see Figure 1). The external pull-up R will then charge the capacitor C. Note that an internal pull-down device on the RPD pin is turned on when the RSTIN pin is low, and causes the external capacitor (C) to begin discharging at a typical rate of 100 to 200A. With this mechanism, after a power-up reset, short low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted longer than the time needed for C to be discharged by the internal pull-down device, then the device is forced into an asynchronous reset.
2.1.2
Return from power down
To exit Power Down mode with external interrupt, an EXxIN pin must be asserted for at least 40ns (x = 7...0). This signal enables the internal main oscillator (if not already running) and PLL circuitry, and also turns on the internal weak pull-down on RPD pin. The discharging of the external capacitor C provides a delay that allows the oscillator and PLL circuits to stabilize before the internal CPU and Peripheral clocks are enabled. When the voltage on the RPD pin drops below the threshold voltage, the CPU and Peripheral clocks are enabled and the device resumes code execution (see Figure 2 on page 5). Figure 3. RPD pin: Internal (simplified) and external circuitry
VD D
VD D
Pull-Up Driven by internal reset/pwrnd circuitr y RPD + Weak Pull-Down (~ 200 A)
R
C
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External RPD circuitry examples
2.1.3
RC network sizing
To calculate the external C value, we will suppose that a time T is required to stabilize the oscillator and PLL circuit. Regarding a generic inverter I/O characteristic, the output level Vo of that inverter can be considered high as long as the input level Vi is higher than its VIHmin (see Figure 4: Generic inverter I/O characteristics). Figure 4. Generic inverter I/O characteristics
Vo
VOHmin
VOLmax VILmax VIHmin Vi
In the same way, as long as RPD voltage is higher than VIH1, CPU and peripherals are not fed with any clock (Figure 2: Simplified power down exit circuitry). Therefore, the capacitor value must be chosen to maintain the voltage above VIH1 for at least the time Trestar t required by PLL and the oscillator (also input hysteresis on RPD pin VHYS4 must be considered). Using the simple formula that controls the discharge of capacitor C, we obtain:
Ipulldown Trestart C = ----------------------------------------------------------------VDD ( VIH1 VHYS4)
where Ipulldown is the current that flows internally through the weak pull-down. Supposing VDD = 5V, since (see product datasheet) VIH1 = 3.5V, VHYS4min = 500 mV, VHYS4max = 1500 mV, Ipulldown = 200A and Trestar t = 10.2ms (crystal oscillator + PLL), it follows:
I pull down Trestar t 200 10 10, 2 10 C = --------------------------------------------------------------------------- = --------------------------------------------------------------------- 1 F 2 VDD (VIH1 VHYS4min )
6 3
As during reset a pull-down is activated on the RPD pin, the capacitor C will be discharged. Subsequently the voltage will drop, causing the RPD pin to be seen at a low level. Therefore, an asynchronous reset will be detected.
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External RPD circuitry examples Table 2.
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RSTIN pulse length and reset events in presence of an RC network
Pulse length Event No effect (filtered) Shor t synchronous reset Long synchronous reset Asynchronous reset
tRSTIN <= 500ns 500ns < tRSTIN < 512 CPU clock cycles 512 CPU clock cycles < tRSTIN < 10ms tRSTIN > 10ms
The value of the resistance R, instead, is linked to the time needed to charge the capacitor C. Normally 220K < R < 1M.
2.2
Alternate configuration
If both synchronous reset and interruptible power down modes are not required, it is possible to connect the RPD pin to ground, directly or through a resistance. Figure 5. RPD pin connected to ground
VDD
Pull-Up driven by internal reset/pwrnd circuitry RPD
Weak Pull-Down (~ 200 A)
The internal pull-up is sized to allow a direct connection to ground without any problem to the internal circuitry. As already explained, with this kind of connection, any pulse longer than 500ns on the RSTIN pin leads to an asynchronous reset. Moreover, it is not advised to use an interruptible power-down.
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Revision history
3
Revision history
Table 3.
Date 30-Mar-2006
Document revision history
Revision 1 Initial release. Changes
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