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Designing an application with the ST10F27x devices

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AN2353 Application note
Designing an application with the ST10F27x devices
Introduction
This note gives advice on designing applications based on devices of the ST10F27x family which includes the ST10F276, ST10F275, ST10F273, ST10F272 and ST10F271. Six topics are covered:

Information and recommendations on using an external resonator with the on-chip oscillator Details on start-up configuration and necessary precautions Filtering, decoupling and use of special pins Recommendations to reduce ADC conversion errors Memory interface Interfacing with the L4969 CAN interface

April 2006

Rev 1

1/18
www.st.com

Contents

AN2353

Contents
1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1. 1 1. 2 1.3 1. 4 1. 5 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Star t-up time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PCB layout for SST10F27x oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Oscillator and EMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 32 kHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2

Port0 start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. 1 2. 2 Por t0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Por t0 start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3

Filtering / decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3. 3 3.4 Decoupling on V18 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Decoupling on +5V supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Filtering / EMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Unused general purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4

Special pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 External access enable/stand-by voltage supply pin (EA/VSTBY) . . . . . . 12 RPD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 6

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Analog Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1 6.2 6.3 6.4 6.5 Voltage drop in the source resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Poor charging of the ADC internal resistance . . . . . . . . . . . . . . . . . . . . . 13 Errors due to high frequencies from input signal . . . . . . . . . . . . . . . . . . . 14 Reducing ADC errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Varef power-up and power-down sequence . . . . . . . . . . . . . . . . . . . . . . . 14

7 8

External memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Connecting to L4969 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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AN2353

Contents

9

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3/18

Oscillator

AN2353

1

Oscillator
The ST10F27x can run with an external clock connected to the XTAL1 input pin of the oscillator inverter or with a clock signal generated by a resonator connected to the XTAL1 / XTAL2 pins. According to the device, two kinds of oscillators have been implemented:

ST10F276E, ST10F275E and ST10F273E: Wide-swing oscillator ST10F272E/B and ST10F271E/B: Low-power oscillator

Moreover, the ST10F27x provides a new feature when the Real Time Clock module is used and a reference clock is needed in Power Down mode. In this case, two possible configurations may be selected by the user application according to the desired level of power reduction:

A 32 kHz crystal is connected to the on-chip 32 kHz oscillator (pins XTAL3 / XTAL4) and running. In this case, the main oscillator is stopped when Power Down mode is entered, while the Real Time Clock continues counting using the 32 kHz clock signal as reference. Only the main oscillator is running (XTAL1 / XTAL2 pins). In this case, the main oscillator is not stopped when Power Down is entered and the Real Time Clock continues counting using the main oscillator clock signal as reference.

Refer to the ST10F27x datasheet for the possible combinations. This chapter provides detailed information on the use of the on-chip oscillator in conjunction with an external resonator.

1.1

Oscillator characteristics
Although simple to implement, using an external resonator (crystal or ceramic resonator) requires a few basic precautions. Referring to the schematic of the on-chip oscillator (Figure 1), the key items are described in the following section. Figure 1. Oscillator characteristics
On-chip Oscillator circuit Equivalent circuit

CL gm

RL

Ls
XTAL1 Resonator XTAL2

Cs
Resonator

Rs

C1

C2

The resonator component can be a crystal or a ceramic resonator. It is represented as a series resonant branch Rs, Ls, Cs. The amplification ability of the oscillator inverter is replaced by a negative resistance RL and the capacitance CL contains the C1 and C2 load capacitances and the stray capacitance of the resonator.

4/18

AN2353

Oscillator The load capacitors C1 and C2 transform the gain of the amplifier (gm) into a negative series resistance RL to compensate for the losses of the crystal. The best frequency stability is obtained when C1 = C2. The oscillation occurs when the sum of RL and Rs (the series resistance of the crystal) is negative. By choosing C1 = C2 = C, the minimal gain of the amplifier (gm) is expressed as follows:
g mm i n = R s × C × = R s × C × ( 2 × × f )
2 2 2 2

The minimal gain of the amplifier also implicitly sets the on-chip oscillator start-up time. Table 1.
Symbol

gm values for different types of oscillators
Value Parameter Version Wide-swing Low-power Conditions Min 8 0.7 Star t-up 32 kHz Normal run 8 17 30 20 Typ 17 2.5 31 Max 35 mA/V 6 50
A/V

Unit

gm

Oscillator transconductance

The oscillation stability mainly depends on external parameters so only the transconductance (gm) can be guaranteed and the start-up time value is defined by measurement at the application level.

1.2

Start-up time
Ceramic resonators have a much shorter start-up time than crystals (about 100 times faster) but have a lower accuracy on the frequency (initial tolerance, temperature variations and drift). Depending on applications requirements and possibilities, users can choose between short oscillator start-up time and frequency accuracy. From an ST10 perspective, the worst case condition / environment for the oscillator start-up time is high temperature and low voltage.

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Oscillator

AN2353

1.3

PCB layout for ST10F27x oscillator
The following Figure 2 shows the proposed layout for the ST10F27x oscillator. Figure 2. Example of layout for external crystal

ST10F27x
XTAL2

Decoupling capacitor CD VDD XTAL1 VSS

Vias to VDD C2 C1

Crystal Vias to GND Crystal package soldered to GND Ground plate Vias to GND

1.4

Oscillator and EMC
The ST10F27x oscillator has an integrated gain control to minimize EMC and power consumption. However, this does not prevent users from observing / respecting the following rules / recommendations:

Avoid other high frequency signals near the oscillator circuitry. These can influence the oscillator. Lay out/configure the ground supply on the basis of low impedance. Shield the crystal with an additional ground plane underneath the crystal. Do not lay out sensitive signals near the oscillator. Analyze cross-talk between different layers. The VSS pin close to the XTAL pins must be connected to the ground plane and decoupled to the closest VDD pin. Capacitors are placed at both ends of the crystal, directly connected to the ground plane while keeping the overall loop as small as possible. The crystal package, when metallic, is directly connected to the ground.

1.5

32 kHz oscillator
The same recommendations are valid for the 32 kHz oscillator. In any case, when the 32 kHz oscillator amplifier is not used, to avoid spurious consumption, XTAL3 must be tied to ground while XTAL4 is left open. Moreover, bit OFF32 in the RTCCON register should be set. The 32 kHz oscillator can only be driven by an external crystal and not by a different clock source.

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AN2353

Port0 start-up configuration

2

Port0 start-up configuration
A reset sequence may be triggered for the following reasons:

Hardware reset signal on pin RSTIN (hardware reset input) Execution of the software reset instruction SRST Overflow of the Watchdog Timer Complete internal RAM write operation before the internal reset procedure begins Cancel pending internal hold states Abor t external memory access cycles Star t program execution from memory location 0000h in code segment 0

After recognition of a reset, the ST10F27x proceeds with the actions listed below:

Note:

Please refer to the datasheet and user's manual for reset event definitions.

2.1

Port0
Pull-down resistors
Pull-down resistors should be low enough so that the input voltage in P0.x is within the circuit specification when taking into account the circuit pull-up current (see PORT0 configuration current for Vin = VILmax) and other leakage currents from external circuits connected to PORT0 pins. Rpd < (VILmax) / (I POl + I other circuits) Recommended maximum value: Rpd = 8K; commonly used values, although larger than the calculated result, are 10K .

Pull-up resistors
PORT0 supplies internal pull-up resistors that are active during Reset. Pull-up resistors should be low enough so that the input voltage in P0.x is within the circuit specification when taking into account the circuit pull-up current (see PORT0 configuration current for Vin = VIHmin) and other leakage currents from external circuits connected to PORT0 pins. For worst case evaluation, leakage current from other external circuits should always be added to circuit leakage current. Rpu < (Vddmin - VIHmin)/ (I other circuits - IPOh) No external pull-up resistor is necessary if Iother circuits < IPOH.

Table 2 presents the clock options on PORT0 P0H.5 - P0H.7 for devices with low power oscillator. Table 3 presents the clock options on PORT0 P0H.5 - P0H.7 for devices with wide-swing oscillator.

7/18

Port0 start-up configuration Table 2.
P0H.7 1 1 1 1 0 0 0 0

AN2353

Clock options on PORT0 P0H.5/.7 for devices with low-power oscillator
P0H.6 1 1 0 0 1 1 0 0 P0H.5 1 0 1 0 1 0 1 0 CPU frequency fCPU = fXTAL x F fXTAL x 4 fXTAL x 3 fXTAL x 8 fXTAL x 5 fXTAL x 1 fXTAL x 10 fXTAL x 0.5 fXTAL x 16 External clock input range(1) 4 to 8 MHz 5.3 to 8 MHz 4 to 8 MHz 6.4 to 8 MHz 1 to 64 MHz 4 to 6.4 MHz 4 to 8 MHz 4 MHz CPU clock via prescaler(3) Direct drive(2) Notes Default configuration

1. The external clock input range refers to a CPU clock range of 1...64 MHz. 2. The maximum input frequency depends on the duty cycle of the external clock signal (refer to the latest datasheet). 3. The limit on input frequency is 4 to 8 MHz since the usage of the internal oscillator amplifier is required. Also, when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or resonator should be used: It is not possible to force any clock with an external clock source.

Table 3.
P0H.7 1 1 1 1 0 0 0 0

Clock options on PORT0 P0H.5 /.7 for devices with wide-swing oscillator
P0H.6 1 1 0 0 1 1 0 0 P0H.5 1 0 1 0 1 0 1 0 CPU frequency fCPU = fXTAL x F fXTAL x 4 fXTAL x 3 fXTAL x 8 fXTAL x 5 fXTAL x 1 fXTAL x 10 fXTAL x 0.5 fXTAL x 16 External clock input range(1) 4 to 8 MHz 5.3 to 10.6 MHz 4 to 8 MHz 6.4 to 12 MHz 1 to 64 MHz 4 to 6.4 MHz 4 to 12 MHz 4 MHz CPU clock via prescaler(3) Direct drive(2) Notes Default configuration

1. The external clock input range refers to a CPU clock range of 1...64 MHz. 2. The maximum input frequency depends on the duty cycle of the external clock signal (refer to the latest datasheet). 3. The limit on input frequency is 4 to 12 MHz since the usage of the internal oscillator amplifier is required. Also when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or resonator shall be should be used: It is not possible to force any clock withan external clock source.

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AN2353

Port0 start-up configuration

2.2

Port0 start-up configuration
Figure 3 illustrates the usage of PORT0 pins to configure ST10F27x. All pins are sampled at power-on reset but some of them are not sampled for specific reset conditions. For details, please refer to the product datasheet and application note.
Figure 3. Port0 pin assignment for power-on configuration

VDD P0H7 P0H6 P0H5 P0H4 P0H P0H3 P0H2 Chip Selects P0H1 P0H0 PORT0 P0L7 P0L6 P0L5 P0L4 P0L P0L3 P0L2 P0L1 P0L0 Reserved Reserved Adapt Mode Emulation Mode WR Configuration Port0 during reset Segment Address Lines External Pull-Down Clock Options (Refer to datasheet / user's manual for PLL factor) Internal Pull-Up

P0L pin

Bustype (BTYP) Startup Configuration

Bootstrap Loader Modes

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Filtering / decoupling

AN2353

3
3.1

Filtering / decoupling
Decoupling on V18 pins
V18 is the output of the ST10F27x internal voltage regulator. It is available on the package to connect external decoupling capacitors. A capacitor, X7R dielectric or equivalent, with a minimum value of 10nF (and maximum 100nF) must be connected between this pin and its nearest VSS pin. This is done to decouple the output of the internal regulator from the ground.

3.2

Decoupling on +5V supply
Decoupling capacitors are placed as close as possible to the chip VSS/VDD pins:

Connected to both VDD and VSS pins (adjacent pins) Connected to each VDD/VSS pair

For EMC reasons, decoupling capacitors are connected to the VDD and VSS of adjacent pins. This is illustrated by Figure 4 below: Figure 4. Implementation of decoupling capacitors
Via to VSS Via to VDD
Cap. Cap.

Via to VSS

Via to VSS
VDD VSS ST10F27x VDD VSS ST10F27x

Good implementation Implementation to be avoided

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AN2353

Filtering / decoupling

3.3

Filtering / EMC
As ST10F27x has an internal voltage regulator, +5V pins are not differentiated between output-buffers and internal logic. This means that when EMC filters are used to isolate the CPU from the supply, all ST10F27x supply pins should be isolated with the filter(s).

Example of filter
Filter placed on supply line of the CPU to remove the conducted noise from the supply line of the module (as illustrated in Figure 5). Figure 5. Filter based on discrete components
ST10F269 L +5V plane C L VSS pins GND plane C VDD pins

Filter connected to supply line of the CPU

3.4

Unused general purpose pins
Unused pins may be an additional source of noise if not properly connected. Used pins must NOT be left floating. Two configurations are possible: 1. 2. Unused pins configured as input (default after reset) Connect the unused pin to VSS (directly or via a pull-down resistor) Unused pin configured as output (by user software) The software sets the corresponding bit of the Direction Port Registers (DPPx) to configure an unused pin as an output (set direction bit to 1) with level to VSS (data bit to 0, default after reset). In this condition, the pad can be left unconnected on the board.

Note:

Avoiding floating pins in an application also ensures a good control on power consumption. Special handling for pins of Port 0 and Port 6
On the pins of Port 0 and Port 6, internal pull-ups are present (under Reset only). Our recommendation is: to keep them open and configured by software as output (set direction bit to 1) with output = 0 (data = 0).

Special handling for pin P3.12 and BHE functionality

The pin P3.12 can be used as the BHE (Byte High Enable) signal for the external memory interface. The BHE alternate function is automatically enabled when the start-up configuration under Reset selects a 16-bit data bus.

11/18

Special pins There are two ways of disabling the BHE alternate function on P3.12: Select an 8-bit data bus size on Port0 during reset (pin P0L7 to VSS). Disable it via bit BYTDIS of the SYSCON register.

AN2353

4
4.1

Special pins
External access enable/stand-by voltage supply pin (EA/VSTBY)
A low level applied to this pin during and after reset forces the ST10F27x to start the program execution from the external memory space. A high level will start the program execution from internal memory. If only internal memory is used, this pin can be tied directly to VDD. The EA/VSTBY pin is also used (when Stand-by mode is entered, that is, ST10F27x under reset and main VDD turned off) to bias the 32 kHz oscillator amplifier circuit, to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8V supply for the XRTC module (when not disabled) and to retain data inside the Stand-by portion of the XRAM (16 Kbyte). It can range from 4.5 to 5.5V.

4.2

RPD Pin
The RPD pin (Return from Power-Down) generates the proper internal timing sequence when interruptible power-down mode is used. If the interruptible power-down mode is not used, the RPD pin can be connected to the ground (directly or via a resistor of 1M maximum). In this configuration, the device always performs asynchronous resets. For more details, please refer to application note AN2340, ST10 RPD pin: Functionality during Reset and Power-down mode.

5

Reset
For information on ST10F27x reset, please refer to the product user manual.

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AN2353

Analog Digital Converter (ADC)

6

Analog Digital Converter (ADC)
Analog input signal error can be created by poor matching of the source internal resistance with the ADC input parameters, which can be caused by the following occurences:

Voltage drop in the voltage source resistance due to input leakage current Poor charging of the ADC internal capacitance (Cin)

Analog input error can also be caused by noise from the analog input signal. This section describes each of these causes. Figure 6. Source internal resistance errors
Sample RSOURCE P5.x R1

VS

V IN

CI O

IOZ1 Leakage Current

CI N

AG ND

AGND

IOZ1 (Input leakage current Port5): maximum 200nA (test condition: 0.45V < VIN < VDD) CIO (Pin capacitance Port5): maximum 10pF (test condition: f = 1 MHz, TA = 25C, guaranteed by design characterization) CIN (ADC internal capacitance): maximum 5pF (guaranteed by design characterization) R1 (Series input resistance): maximum 1.5k (guaranteed by design characterization)

6.1

Voltage drop in the source resistance
The error generated by the voltage source internal resistance is:
RS OU R C E × I( 0Z 1) e r r o r ( L S B ) = ---------------------------------------------- × 1024 V A R E F VA G N D

I(OZ1) = specified leakage current. Refer to the latest product datasheet for the value of I(OZ1). Note: Input leakage current is caused by parasitic current into the on-chip protection of the input pin; this protection is necessary to protect the device against ESD (Electrical Static Discharge) and against overload.

6.2

Poor charging of the ADC internal resistance
During the sample time, the input capacitance (CIO and CIN) must be charged/discharged by the external source. The internal resistance of the source must allow the capacitance to reach its final value before the end of sample time. If this does not happen, that is, if the source resistance is mismatched to the sample time, a voltage loss occurs at the sample and hold stage. This voltage loss causes an accuracy loss

13/18

Analog Digital Converter (ADC)

AN2 353

when increasing or decreasing the input voltage from Varef/2 (hold capacitor is precharged to Varef/2 before sampling to reduce charge/discharge time). Refer to the product data sheet for details.

6.3

Errors due to high frequencies from input signal
Small but high frequency signal variations can result in increased conversion error: During sampling time, the analog signal is fed to an internal auto-zero circuitry. Signal variations (at least two opposite transitions) during this time can generate auto-zero error. Signal variations during sampling time generate excessively high or low conversion results; big variations (Example: 150mV peak to peak variations at 1.5 MHz, with a 2.5V offset for 1s sampling time) can generates clamped results (0x000 or 0x3FFh). Although the sample and hold internal circuitry is integrating signal variations, other internal analog circuitry can be affected by signal transitions during sampling time. The input analog signal should always be low pass filtered to ensure that high frequencies are rejected.

6.4

Reducing ADC errors
There are four possible optimizations:

Minimize the total source impedance seen by the ST10 This means choosing sensors with low output impedance (not always easy for some types of sensor) and minimizing the serial resistance of any protection devices between the analog source and the input pin (while still providing a voltage protection level compatible with the circuit specification).

Match the sample time to the analog source impedance Match the sample time to the analog filter cut-off frequency to remove high frequencies The ST10F27x sampling time (ADC silicon configuration) shall be should be / must be / is 5 to 10 times shorter than the period of the cut-off frequency of the low-pass filter on ADC input signal.

Reduce noise at the input pin Add an external RC filter (with attention to the source internal resistance). Compute the average value of different samples in the software routine.

6.5

Varef power-up and power-down sequence
Varef should always be lower than the 5V supply (maximum = VDD + 0.1V). This is especially true for the power-up and power-down sequence when external devices are used to generate Varef.

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AN2353

External memory interface

7

External memory interface
The ST10F27x external memory bus can easily interface with the STMicroelectronics external Flash (M29Fxx series). Please refer to application note AN1155 Connecting the ST10 Microcontroller to M29 Series Flash Memories.

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Connecting to L4969

AN2353

8

Connecting to L4969
L4969 is a combined voltage regulator and low-speed CAN interface from STMicroelectronics. The following figure shows how to connect the L4969 CAN interface to the ST10F27x microcontroller when working on an SPI bus with multiple peripherals.

Note:

For further information on the L4969, please refer to the L4969 datasheet and the available application notes for this device.
When no other peripherals are connected to the SPI bus, the L4969 can be directly connected to the ST10 SPI lines without any further constraints. Figure 7. ST10F27x connected to L4969 and other SPI devices

RESET Px.y

NRES NINT L4969 Device x Device y

EN

CSL4969 CSx CS y SCLK MTSR MRST

16/18

SIN

CL K

SOUT

EN

AN2353

Revision history

9

Revision history
Table 4.
Date 24-Apr-2006

Document revision history
Revision 1 Initial release Changes

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AN2353

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Document Number: 12301



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