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AN2462 Application note
STw8009 PCB design guidelines
Introduction
STw8009 performs digital to analog video signal conversion. It handles 27 MHz clock and data (4:2:2 format of CCIR 601) on one side, and analog video bandwidth on 75R cable on the other side. Register access is performed with I2C link. Three supply lines are needed for core, I/Os and converters.
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PCB guidelines
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PCB guidelines
The main PCB guidelines are for digital routing. As the digital processor is supposed to provide 27 MHz of data with a very fast transition time, reflection between STw8009 YCbCr inputs and source can be important. To minimize this phenomenon, the application must include a series resistor close to the digital source on each data and clock line, typically 56R. The direct effect is a better signal integrity for correct clocking by the STw8009. Secondly, for same fast transition time reason, 8 bits of data bus must be routed with a ground line between two adjacent data lines if possible. Otherwise, avoiding adjacent coupling on several centimeters with a minimum of two tracks width between two adjacent data lines, if no ground insulation is possible. This is not suitable for small distances, that is, less than one centimeter. The 27 MHz clock also requires a serial resistor on its source side, and at least this signal must be laterally shielded with ground tracks. On the analog side, a biasing resistor (2K4) must be placed as close as possible to the STw8009 Rext ball (A4). A video output on-board 75R termination resistor is required. This is to have enough dissipation power behavior to avoid linearity problems (0603 size is sufficient). As an example, the STw8009-M01 module is a typical application, which has been routed using four layers and one side component, as shown below in Figure 1 (4x4mm device). Figure 1. STw8009-M01 module
The schematic of this typical application module is shown in Figure 2.
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AN2462 Figure 2. Schematic diagram
PCB guidelines
Regarding ground plane, the rule is to have one layer dedicated for both digital and analog ground references. The lower the impedance (that is, the area) this ground plane has, the better the current returns.
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Figure 3 shows part of the routing of the module, for the data bus and clock; the first internal layer and top side of the PCB, respectively.
Figure 3. Data bus and clock part of the routing module 8 data lines clock
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Revision history
2
Revision history
Table 1.
Date 10-Apr-2007
Document revision history
Revision 1 Initial release. Changes
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