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STM32F10xxx SPI application examples
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Last Updated: 05/07/2007
Pages: 11
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AN2576 Application note
STM32F10xxx SPI application examples
Introduction
This application note is intended to provide practical application examples of the STM32F10xxx SPI peripheral use. This document, its associated firmware, and other such application notes are written to accompany the STM32F10xxx firmware library. These are available for download from the STMicroelectronics website: www.st.com.
June 2007
Rev 1
1/11
www.st.com
Contents
AN2576
Contents
1 STM32F10xxx full-duplex SPI-SPI communication with software NSS management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 1.3 1.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 C onclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
STM32F10xxx simplex SPI-SPI communication using interrupts . . . . 5
2.1 2.2 2.3 2.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 C onclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
STM32F10xxx full-duplex SPI-SPI communication with CRC transfer . 6
3.1 3.2 3.3 3.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 C onclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Simplex SPI-SPI communication with DMA and hardware NSS management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 4.2 4.3 4.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 C onclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
STM32F10xxx SPI and M25P64 Flash memory communication . . . . . . 8
5.1 5.2 5.3 5.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 C onclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
2/11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AN2576
STM32F10xxx full-duplex SPI-SPI communication with software NSS management
1
STM32F10xxx full-duplex SPI-SPI communication with software NSS management
Overview
This section describes how to set an SPI-SPI full-duplex communication. The NSS pin software management allows master-to-slave and slave-to-master permutation without any hardware modification.
1.1
1.2
Hardware description
Figure 1 shows a typical connection in full-duplex mode between the STM32F10xxx SPI1 and SPI2. The SPI1 and SPI2 data inputs (MISO) are connected together. The SPI1 and SPI2 data outputs (MOSI) are connected together. And the SPI1 and SPI2 clock inputs (SCK) are also connected together. The SPI1 and SPI2 NSS pins are kept unconnected thanks to the software NSS management. Figure 1. STM32F10xxx full-duplex SPI-SPI communication
SPI1_MOSI SPI1_MISO SPI1_SCK SPI2_SCK SPI2_MISO SPI2_MOSI
STM32F10xxx
ai14327
1.3
Firmware description
The provided firmware includes the SPI driver that supports all SPI communications through a set of functions. The NSS pins are configured by software to set SPI1 as the master and, SPI2 as the slave. First, a data buffer is sent from the master (SPI1) to the slave (SPI2) and at the same time, the salve sends another data buffer to the master. In the second part of the example, using software and without any hardware modification, SPI1 is re-configured as the slave and SPI2, as the master. A new full-duplex communication is established and two data buffers are exchanged between the master and the slave. All the transmitted and received buffers are then compared to check that all the data have been correctly exchanged. This firmware is provided as SPI example 1 in the STM32F10xxx firmware library, available from the STMicroelectronics microcontrollers website.
3/11
STM32F10xxx full-duplex SPI-SPI communication with software NSS management
AN2576
1.4
Conclusion
The NSS software management is given to remove the need for any hardware modification in a given application where a switch from master to slave or slave to master is required. Owing to the software management of the NSS pins, the user has no hardware constraint in this type of application.
4/11
AN2576
STM32F10xxx simplex SPI-SPI communication using interrupts
2
STM32F10xxx simplex SPI-SPI communication using interrupts
Overview
This section describes how to set an SPI-SPI simplex communication using TxE and RxNE interrupts.
2.1
2.2
Hardware description
Figure 2 shows a typical connection in simplex mode between the STM32F10xxx SPI1 and SPI2. The SPI1 data output (MOSI) is connected to the SPI2 data input (MISO) and the SPI1 and SPI2 clock (SCK) lines are connected together. The SPI1 and SPI2 NSS pins are kept unconnected thanks to the software NSS management. Figure 2. STM32F10xxx simplex SPI-SPI communication
SPI1_MOSI SPI1_SCK
SPI2_SCK SPI2_MISO
STM32F10xxx
ai14344
2.3
Firmware description
The provided firmware includes the SPI driver that supports all SPI communications through a set of functions. The NSS pins are configured by software to set SPI1 as the master and, SPI2 as the slave. A data buffer is sent from the master (SPI1) using the TxE interrupt, to the slave (SPI2) that receives the data using the RxNE interrupt. The transmitted buffer and the received buffer are compared to check that all data have been correctly exchanged. This firmware is provided as SPI example 2 in the STM32F10xxx firmware library, available from the STMicroelectronics microcontrollers website.
2.4
Conclusion
The use of the TxE and RxNE interrupts within a communication reduces the code density and makes it easy for the user to transmit and receive data. In simplex communication mode, the user only needs to use the master MOSI pin and the slave MISO pin with the CLK pins. In this way, the other SPI pins can be used for other purposes.
5/11
STM32F10xxx full-duplex SPI-SPI communication with CRC transfer
AN2576
3
STM32F10xxx full-duplex SPI-SPI communication with CRC transfer
Overview
This section describes how to set an SPI-SPI full-duplex communication followed by a CRC transmission.
3.1
3.2
Hardware description
Figure 3 shows a typical connection between the STM32F10xxx SPI1 and SPI2. The SPI1 and SPI2 data inputs (MISO) are connected together. The SPI1 and SPI2 data outputs (MOSI) are connected together. And the SPI1 and SPI2 clock inputs (SCK) are also connected together. The SPI1 and SPI2 NSS pins are kept unconnected thanks to software NSS management. Figure 3. STM32F10xxx full-duplex SPI-SPI communication
SPI1_MOSI SPI1_MISO SPI1_SCK SPI2_SCK SPI2_MISO SPI2_MOSI
STM32F10xxx
ai14327
3.3
Firmware description
The provided firmware includes the SPI driver that supports all SPI communications through a set of functions. The NSS pins are configured by software to set SPI1 as the master and, SPI2 as the slave. First, a data buffer is sent from the master (SPI1) to the slave (SPI2) and at the same time, the salve sends another data buffer to the master. The CRC calculation is already enabled. At the end of both buffer transmission, CRC transfer is enabled for both master and slave. The CRC values received by SPI1 and SPI2 are stored into two variables and the user may use them to check whether the communications completed successfully. The transmitted buffer and the received buffer are compared to check that all data have been correctly exchanged. If the received CRC value is erroneous, the CRCERR flag is set in the SPI_SR; if the received CRC value is correct, the CRCERR flag remains cleared. This firmware is provided as SPI example 3 in the STM32F10xxx firmware library, available from the STMicroelectronics microcontrollers website.
3.4
Conclusion
By making it possible to check the transmitted or received data using CRC, the STM32F10xxx brings a greater reliability to SPI communications than most peripherals.
6/11
AN2576
Simplex SPI-SPI communication with DMA and hardware NSS management
4
Simplex SPI-SPI communication with DMA and hardware NSS management
Overview
This section describes how to set an SPI-SPI simplex communication using DMA. The NSS pin is managed by hardware.
4.1
4.2
Hardware description
Figure 4 shows a typical connection in simplex mode, between the STM32F10xxx SPI1 and SPI2. SPI2 data output (MOSI) is connected to SPI1 data input (MISO) and the SPI1 and SPI2 clock (SCK) lines are connected together. The SPI1 and SPI2 NSS pins are also connected together. Figure 4. STM32F10xxx simplex SPI-SPI communication
SPI1_NSS SPI1_MOSI SPI1_SCK SPI2_SCK SPI2_MISO SPI2_NSS
STM32F10xxx
ai14343
4.3
Firmware description
The provided firmware includes the SPI driver that supports all SPI communications through a set of functions. The NSS pins are configured by hardware to set SPI2 as the master and SPI1 as the slave: by enabling SS output (that is by setting the SPI_CR2 SSOE bit), the SPI2 NSS pin resets the SPI1 NSS pin and configures SPI1 as the slave. The master (SPI2) sends a data buffer to the slave (SPI1) by polling the TxE flag. SPI1 receives the data through DMA channel2. At the end of the data transfer, the transmitted and the received buffers are compared to check whether all data have been correctly exchanged. This firmware is provided as SPI example 4 in the STM32F10xxx firmware library, available from the STMicroelectronics microcontrollers website.
4.4
Conclusion
The use of DMA within a communication further reduces the code density and execution time. It is an easy way of transmitting and receiving data. The SSOE bit makes it possible to choose a unique master when all devices on the bus have their NSS pins connected together.
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STM32F10xxx SPI and M25P64 Flash memory communication
AN2576
5
STM32F10xxx SPI and M25P64 Flash memory communication
Overview
This section describes how to use the SPI firmware library with an associated SPI Flash memory driver to communicate with an M25P64 Flash memory. An example is given that uses most of the SPI Flash memory driver functionality: Write, Read, Erase, Get Flash ID, etc.
5.1
5.2
Hardware description
Figure 5 shows a typical interface between the STM32F10xxx and an M25P64 SPI Flash memory. The STM32F10xxx data input (MISO), data output (MOSI) and clock (SCK) input connected to the M25P64 data input (Q), data output (D) and clock (C) input, respectively. Another STM32F10xxx output pin (PA4) is connected to the M25P64 Chip Select (S) input so that the STM32F10xxx can identify a unique SPI Flash memory out of all the ones being used on the basis of the incoming operation itself. Figure 5. STM32F10xxx and M25P64 SPI Flash memory interface
3.3 V
10 k PA4 MOSI MISO SCK S D Q C
VCC
HOLD W VSS
M25P64 STM32F10xxx
ai14345
5.3
Firmware description
The provided firmware includes the SPI Flash memory driver that supports all erase, write and read operations through a set of functions. An example of use for most of these functions is provided. First, the SPI Flash memory device identification (ID) is read. This ID is then compared with the expected value. The sector to be accessed is then erased and the buffer write and read operations are performed. The written and the read buffers are then compared. When this is done, a new Sector Erase operation is performed to clear the data already written in the selected SPI Flash memory sector. Finally, a read operation is carried out to check that all data have been correctly erased. This firmware is provided as SPI example 5 in the STM32F10xxx firmware library, available from the STMicroelectronics microcontrollers website.
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AN2576
STM32F10xxx SPI and M25P64 Flash memory communication
5.4
Conclusion
With a simple hardware connection and this SPI Flash memory driver example, the user is able to develop greater and more complex communication applications between the STM32F10xxx and any interfaced SPI Flash memory.
9/11
Revision history
AN2576
6
Revision history
Table 1.
Date 28-Jun-2007
Document revision history
Revision 1 Initial release. Changes
10/11
AN2576
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