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STM32F10xxx hardware development: getting started

Application Note

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Last Updated: 23/05/2008

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High-density access line, ARM-based 32-bit MCU with 256 to 512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces

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Medium-density access line, ARM-based 32-bit MCU with 32 to 128 KB Flash, six timers, ADC and 7 communication interfaces

Medium-density performance line ARM-based 32-bit MCU with 32 to 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces

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AN2586 Application note
STM32F10xxx hardware development: getting started
Introduction
This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the High-density and Medium-density STM32F10xxx product families and describes the minimum hardware resources required to develop an STM32F10xxx application. Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes.

May 2008

Rev 2

1/29
www.st.com

Contents

AN2586

Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 1.1.2 1.1.3 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 6 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 1.3

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 1.3.2 1.3.3 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 8 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 2.1.2 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 13

2.2

LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 2.2.2 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 14

2.3 2.4

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3

Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Embedded Boot Loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4

Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 4.2 4.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 4.3.2 4.3.3 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Internal pull-up and pull-down resistors on JTAG pins . . . . . . . . . . . . . . 19

2/29

AN2586 4.3.4

Contents SWJ debug port connection with standard JTAG connector . . . . . . . . . 20

5

Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 5.2 5.3 5.4 5.5 5.6 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6

Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2

Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3/29

List of tables

AN2586

List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SWJ I/O pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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AN2586

List of figures

List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32F103ZE(T6) microcontroller reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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Power supplies

AN2586

1
1.1

Power supplies
Introduction
The device requires a 2.0 V to 3.6 V operating voltage supply (VDD). An embedded regulator is used to supply the internal 1.8 V digital power. The real-time clock (RTC) and backup registers can be powered from the VBAT voltage when the main VDD supply is powered off. Figure 1. Power supply overview
VDDA domain A/D converter Temp. sensor Reset block PLL

(VSSA) VREF (from 2.4 V up to VDDA) VREF+ (VDD) VDDA (VSS) VSSA

VDD domain I/O Ring V SS VD D Standby circuitry (Wakeup logic, IWD G) Voltage regulator Low voltage detector Backup domain (VDD) VBAT

1.8 V domain Core memories' digital peripherals

LSE crystal 32 KHz oscillator BKP registers RCC BDCR register RTC

ai14863

Note:

VDDA and VSSA must be connected to VDD and VSS, respectively.

1.1.1

Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB.

the ADC voltage supply input is available on a separate VDDA pin an isolated supply ground connection is provided on the VSSA pin

When available (depending on package), VREF must be tied to VSSA.

On 100-pin and 144-pin packages packages
To ensure a better accuracy on low-voltage inputs, the user can connect a separate external reference voltage ADC input on VREF+. The voltage on VREF+ may range from 2.4 V to VDDA.

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AN2586

Power supplies

On packages with 64 pins or less
The VREF+ and VREF- pins are not available, they are internally connected to the ADC voltage supply (VDDA) and ground (VSSA).

1.1.2

Battery backup
To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be connected to an optional standby voltage supplied by a battery or another source. The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the power down reset (PDR) circuitry embedded in the Reset block. If no external battery is used in the application, VBAT must be connected externally to VDD.

1.1.3

Voltage regulator
The voltage regulator is always enabled after reset. It works in three different modes depending on the application modes.

in Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals) in Stop mode, the regulator supplies low power to the 1.8 V domain, preserving the contents of the registers and SRAM in Standby mode, the regulator is powered off. The contents of the registers and SRAM are lost except for those concerned with the Standby circuitry and the Backup domain.

1.2

Power supply schemes
The circuit is powered by a stabilized power supply, VDD.

Caution: If the ADC is used, the VDD range is limited to 2.4 V to 3.6 V If the ADC is not used, the VDD range is 2.0 V to 3.6 V

The VDD pins must be connected to VDD with external stabilization capacitors (eleven 100 nF ceramic capacitor + one Tantalum capacitor (min. 4.7 F typ.10 F). The VBAT pin must be connected to the external battery (1.8 V < VBAT < 3.6 V). if no external battery is used, this pin must be connected to VDD with a 100 nF external ceramic stabilization capacitor. The VDDA pin must be connected to two external stabilization capacitors (10 nF ceramic + 1 F Tantalum). The VREF+ pin can be connected to the VDDA external power supply. If a separate, external reference voltage is applied on VREF+, two 10 nF and 1 F capacitors must be connected on this pin. In all cases, VREF+ must be kept between 2.4 V and VDDA.

7/29

Power supplies Figure 2.
Power supply scheme
STM32F10xxx VBAT Battery VDD 11 × 100 nF + 1 × 10 F VDD 1/2/3/.../11 VSS 1/2/3/.../11 VBAT VREF VREF+ VDD VDDA 10 nF + 1 F VSSA VREF
ai14865

AN2586

10 nF + 1 F (note 1)

1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (10 nF and 1 F) must be connected. 2. VREF+ is either connected to VDDA or to VREF.

1.3
1.3.1

Reset & power supply supervisor
Power on reset (POR) / power down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting from 2 V. The device remains in the Reset mode as long as VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics in the STM32F101xx and STM32F103xx datasheets. Figure 3. Power on reset/power down reset waveform
VDD

POR 40 mV hysteresis PDR

Temporization tRSTTEMPO

RESET
ai14364

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AN2586

Power supplies

1.3.2

Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate whether VDD is higher or lower than the PVD threshold. This event is internally connected to EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge configuration. As an example the service routine can perform emergency shutdown tasks. Figure 4. PVD thresholds
VDD

PVD threshold

100 mV hysteresis

PVD output

ai14365

1.3.3

System reset
A system reset sets all registers to their reset values except for the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 1). A system reset is generated when one of the following events occurs: 1. 2. 3. 4. 5. A low level on the NRST pin (external reset) window watchdog end-of-count condition (WWDG reset) Independent watchdog end-of-count condition (IWDG reset) A software reset (SW reset) Low-power management reset

The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR.

9/29

Power supplies Figure 5. Reset circuit
V DD External reset circuit NRST RON Filter 0.1 F Pulse generator (min 20 s)

AN2586

System nreset

WWDG reset IWDG reset POR/PDR reset Software reset Low-power management reset

ai14366

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AN2586

Clocks

2

Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):

HSI oscillator clock (high-speed internal clock signal) HSE oscillator clock (high-speed external clock signal) PLL clock 40 kHz low-speed internal RC (LSI RC) that drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby modes. 32.768 kHz low-speed external crystal (LSE crystal) that optionally drives the real-time clock (RTCCLK)

The devices have two secondary clock sources:

Each clock source can be switched on or off independently when it is not used, to optimize the power consumption.

11/29

Clocks Figure 6. Clock overview
USB Prescaler /1, 1.5 USBCLK to USB interface

AN2586

48 MHz

I2S3CLK Peripheral clock enable

to I2S3

I2S2CLK

to I2S2 SDIOCLK FSMCCLK to SDIO to FSMC

8 MHz HSI RC

HSI

Peripheral clock enable Peripheral clock enable

/2

Peripheral clock enable 72 MHz max Clock Enable (4 bits)

HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock
Enable (20 bits)

PLLSRC

PLLMUL ..., x16 x2, x3, x4 PLL
HSI PLLCLK HSE

SW
SYSCLK

/8

72 MHz /1, 2..512 max

AHB Prescaler

APB1 Prescaler /1, 2, 4, 8, 16

36 MHz max

CSS

TIM2,3,4,5,6,7 x1, 2 Multiplier
Peripheral Clock Enable (6 bits)

to TIM2,3,4,5,6 and 7 TIMXCLK

PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2

APB2 Prescaler /1, 2, 4, 8, 16

72 MHz max Peripheral Clock Enable (15 bits)

PCLK2 peripherals to APB2

TIM1 & 8 timers x1, 2 Multiplier

to TIM1 and TIM8 TIMxCLK
Peripheral Clock Enable (2 bit) to ADC1, 2 or 3

/128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz
LSE to RTC

RTCCLK RTCSEL[1:0]

ADC Prescaler /2, 4, 6, 8
/2

ADCCLK
HCLK/2

LSI RC 40 kHz

LSI

to Independent Watchdog (IWDG)

To SDIO AHB interface Peripheral clock enable

IWDGCLK

Main Clock Output

/2

PLLCLK HSI HSE SYSCLK

Legend: HSE = h igh-sp eed e xternal clock signal HSI = h igh-sp eed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal ai14752b

MCO

MCO

1. HSE = high-speed external clock signal; HSI = high-speed internal clock signal; LSI = low-speed internal clock signal; LSE = low-speed external clock signal. 2. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz.

2.1

HSE OSC clock
The high-speed external clock signal (HSE) can be generated from two possible clock sources:

HSE external crystal/ceramic resonator (see Figure 8) HSE user external clock (see Figure 7)

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AN2586

Clocks

Figure 7.

External clock

Figure 8.

Crystal/ceramic resonators
Hardware configuration STM32F10xxx

Hardware configuration
OSC_IN OSC_OUT

OSC_IN

OSC_OUT
REXT(1)

(Hi-Z) External source
ai14369

CL1

CL2

ai14370

1. The value of REXT depends on the crystal characteristics. Typical value is in the range of 5 to 6 RS (resonator series resistance). 2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where: Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Please refer to Section 5: Recommendations on page 21 to minimize its value.

2.1.1

External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 25 MHz. The external clock signal (square, sine or triangle) with a duty cycle of about 50%, has to drive the OSC_IN pin while the OSC_OUT pin must be left in the high impedance state (see Figure 8 and Figure 7).

2.1.2

External crystal/ceramic resonator (HSE crystal)
The 4-to-16 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 8. The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF-to25 pF range (typ.), designed for high-frequency applications and selected to meet the requirements of the crystal or resonator. CL1 and CL2, are usually the same value. The crystal manufacturer typically specifies a load capacitance that is the series combination of CL1 and CL2. The PCB and MCU pin capacitances must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance). Refer to the electrical characteristics sections in the STM32F101xx and STM32F103xx datasheets for more details.

2.2

LSE OSC clock
The low-speed external clock signal (LSE) can be generated from two possible clock sources:

LSE external crystal/ceramic resonator (see Figure 10) LSE user external clock (see Figure 9)

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Clocks

AN2586

Figure 9.

External clock

Figure 10. Crystal/ceramic resonators
Hardware configuration

Hardware configuration

STM32F10xxx OSC32_IN OSC32_OUT

OSC32_IN OSC32_OUT

REXT(1)
(Hi-Z) External source
ai14371

CL1

CL2
ai14372

1. The value of REXT depends on the crystal characteristics. 2. OSC32_IN and OSC_OUT pins can be used also as GPIO, but it is recommended not to use them as both RTC and GPIO pins in the same appication.

2.2.1

External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency of 32.768 kHz. The external clock signal (square, sine or triangle) with a duty cycle of about 50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance (see Figure 10 and Figure 9).

2.2.2

External crystal/ceramic resonator (LSE crystal)
The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It has the advantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The load capacitance values must be adjusted according to the selected oscillator.

2.3

Clock-out capability
The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One out of four clock signals can be selected as the MCO clock:

SYSC LK HSI HSE PLL clock divided by 2

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AN2586

Clocks

2.4

Clock security system (CSS)
The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE oscillator clock, the oscillator is automatically disabled. A clock failure event is sent to the break input of the TIM1 advanced control timer and an interrupt is generated to inform the software about the failure (clock security system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the CortexTM-M3 NMI (non-maskable interrupt) exception vector. If the HSE oscillator is used directly or indirectly as the system clock (indirectly means that it is used as the PLL input clock, and the PLL clock is used as the system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.

For details, see the STM32F10xxx reference manual available from the STMicroelectronics website www.st.com.

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Boot configuration

AN2586

3
3.1

Boot configuration
Boot mode selection
In the STM32F10xxx, three different boot modes can be selected by means of the BOOT[1:0] pins as shown in Table 1. Table 1.
BOOT1 x 0 1

Boot modes
BOOT0 0 1 1 Boot mode Aliasing Main Flash memory is selected as boot space System memory is selected as boot space Embedded SRAM is selected as boot space

BOOT mode selection pins

Main Flash memory System memory Embedded SRAM

This selection aliases the physical memory associated with each boot mode to Block 000 (boot memory). The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode. The BOOT pins are also resampled when exiting the Standby mode. Consequently, they must be kept in the required Boot mode configuration in the Standby mode. Even when aliased in the boot memory space, the related memory (Flash memory or SRAM) is still accessible at its original memory space. After this startup delay has elapsed, the CPU starts code execution from the boot memory, located at the bottom of the memory address space starting from 0x0000_0000.

3.2

Boot pin connection
Figure 11 shows the external connection required to select the boot memory of the STM32F10xxx. Figure 11. Boot mode selection implementation example
STM32F10xxx VDD 10 k VDD 10 k BOOT1 BOOT0

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1. Resistor values are given only as a typical example.

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Boot configuration

3.3

Embedded Boot Loader mode
The Embedded Boot Loader mode is used to reprogram the Flash memory using one of the serial interfaces (typically a UART). This program is located in the system memory and is programmed by ST during production. For further details, please refer to Application note AN2606 available from the STMicroelectronics website, www.st.com.

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Debug management

AN2586

4
4.1

Debug management
Introduction
The Host/Target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, a JTAG or SW connector and a cable connecting the host to the debug tool. Figure 12 shows the connection of the host to the evaluation board (STM3210B-EVAL board or STM3210E-EVAL board). Figure 12. Host-to-board connection

Debug tool

JTAG/SW connector

Host PC STM3210B-EVAL or STM3210E-EVAL

Power supply
ai14866

4.2

SWJ debug port (serial wire and JTAG)
The STM32F10xxx core integrates the serial wire / JTAG debug port (SWJ-DP). It is an ARM standard CoreSightTM debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-pin) interface.

The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHPAP port The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP port

In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP.

4.3

Pinout and debug port pins
The STM32F10xxx MCU is offered in various packages with different numbers of available pins. As a result, some functionality related to the pin availability may differ from one package to another.

4.3.1

SWJ debug port pins
Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose I/Os (GPIOs). These pins, shown in Table 2, are available on all packages.

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AN2586 Table 2. Debug port pin assignment
JTAG debug port SWJ-DP pin name Type JTMS/SWDIO JTCK/SWCLK JTDI I I I Description JTAG Test Mode Selection JTAG Test Clock JTAG Test Data Input SW debug port

Debug management

Type Debug assignment I/O I Serial Wire Data Input/Output Serial Wire Clock -

Pin assignment PA13 PA14 PA15

JTDO/TRACESWO O JNTRST I

JTAG Test Data Output JTAG Test nReset -

TRACESWO if async trace PB3 is enabled PB4

4.3.2

Flexible SWJ-DP pin assignment
After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host). However, the STM32F10xxx MCU implements a register to disable some part or all of the SWJ-DP port, and so releases the associated pins for general-purpose I/Os usage. This register is mapped on an APB bridge connected to the CortexTM-M3 system bus. This register is programmed by the user software program and not by the debugger host. Table 3. SWJ I/O pin availability
SWJ I/O pin assigned Available Debug ports PA13 / JTMS/ SWDIO X X X PA14 / JTCK/ SWCLK X X X Released PA15 / JTDI X X PB3 / JTDO X X PB4/ JNTRST X

Full SWJ (JTAG-DP + SW-DP) - reset state Full SWJ (JTAG-DP + SW-DP) but without JNTRST JTAG-DP disabled and SW-DP enabled JTAG-DP disabled and SW-DP disabled

Table 3 shows the different possibilities to release some pins. For more details, see the STM32F10xxx reference manual, available from the STMicroelectronics website www.st.com.

4.3.3

Internal pull-up and pull-down resistors on JTAG pins
The JTAG input pins must not be floating since they are directly connected to flip-flops to control the debug mode features. Special care must be taken with the SWCLK/TCK pin that is directly connected to the clock of some of these flip-flops.

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Debug management

AN2586

To avoid any uncontrolled I/O levels, the STM32F10xxx embeds internal pull-up and pulldown resistors on JTAG input pins:

JNTRST: Internal pull-up JTDI: Internal pull-up JTMS/SWDIO: Internal pull-up TCK/SWCLK: Internal pull-down

Once a JTAG I/O is released by the user software, the GPIO controller takes control again. The reset states of the GPIO control registers put the I/Os in the equivalent state:

JNTRST: Input pull-up JTDI: Input pull-up JTMS/SWDIO: Input pull-up JTCK/SWCLK: Input pull-down JTDO: Input floating

The software can then use these I/Os as standard GPIOs. Note: The JTAG IEEE standard recommends to add pull-up resistors on TDI, TMS and nTRST but there is no special recommendation for TCK. However, for the STM32F10xxx, an integrated pull-down resistor is used for JTCK. Having embedded pull-up and pull-down resistors removes the need to add external resistors.

4.3.4

SWJ debug port connection with standard JTAG connector
Figure 13 shows the connection between the STM32F10xxx and a standard JTAG connector. Figure 13. JTAG connector implementation
JTAG connector CN9 VDD STM32F10xxx (1) VTREF (3) nTRST (5) TDI (7) TMS (9) TCK (11) RTCK (13)TDO (15) nSRST (17) DBGRQ (19) DBGACK 10 k 10 k VSS (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) Connector 2 × 10 VDD

nJTRST JTDI JSTM/SWDIO JTCK/SWCLK JTDO nRSTIN 10 k

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AN2586

Recommendations

5
5.1

Recommendations
Printed circuit board
For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (VSS) and another dedicated to the VDD supply. This provides good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board. In this case, the major requirement is to ensure a good structure for ground and for the power supply.

5.2

Component position
A preliminary layout of the PCB must separate the different circuits according to their EMI contribution in order to reduce cross-coupling on the PCB, that is noisy, high-current circuits, low-voltage circuits, and digital components.

5.3

Ground and power supply (VSS, VDD)
Every block (noisy, low-level sensitive, digital, etc.) should be grounded individually and all ground returns should be to a single point. Loops must be avoided or have a minimum area. The power supply should be implemented close to the ground line to minimize the area of the supply loop. This is due to the fact that the supply loop acts as an antenna, and is therefore the main transmitter and receiver of EMI. All component-free PCB areas must be filled with additional grounding to create a kind of shielding (especially when using singlelayer PCBs).

5.4

Decoupling
All pins need to be properly connected to the power supplies. These connections, including pads, tracks and vias should have as low an impedance as possible. This is typically achieved with thick track widths and, preferably, the use of dedicated power supply planes in multilayer PCBs. In addition, each power supply pair should be decoupled with filtering ceramic capacitors C (100 nF) and a chemical capacitor C of about 10 F connected in parallel on the STM32F10xxx device. These capacitors need to be placed as close as possible to, or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but exact values depend on the application needs. Figure 14 shows the typical layout of such a VDD/VSS pair.

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Recommendations Figure 14. Typical layout for VDD/VSS pair Via to VDD Cap. Via to VSS

AN2586

VDD VSS
STM32F10xxx

5.5

Other signals
When designing an application, the EMC performance can be improved by closely studying:

signals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for LED commands). For these signals, a surrounding ground trace, shorter lengths and the absence of noisy and sensitive traces nearby (crosstalk effect) improve EMC performance. For digital signals, the best possible electrical margin must be reached for the two logical states and slow Schmitt triggers are recommended to eliminate parasitic states. noisy signals (clock, etc.) sensitive signals (high impedance, etc.)

5.6

Unused I/Os and features
All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources. To increase EMC performance, unused clocks, counters or I/Os, should not be left free, e.g. I/Os should be set to "0" or "1"(pull-up or pull-down to the unused I/O pins.) and unused features should be "frozen" or disabled.

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AN2586

Reference design

6
6.1

Reference design
Description
The reference design shown in Figure 15, is based on the STM32F103ZE(T6), a highly integrated microcontroller running at 72 MHz, that combines the new CortexTM-M3 32-bit RISC CPU core with 512 Kbytes of embedded Flash memory and up to 64 Kbytes of highspeed SRAM. This reference design can be tailored to any other STM32F10xxx device with different package, using the pins correspondence given in Table 6: Reference connection for all packages.

6.1.1

Clock
Two clock sources are used for the microcontroller:

LSE: X1 32.768 kHz crystal for the embedded RTC HSE: X2 8 MHz crystal for the STM32F10xxx microcontroller

Refer to Section 2: Clocks on page 11.

6.1.2

Reset
The reset signal in Figure 15 is active low. The reset sources include:

Reset button (B1) Debugging tools via the connector CN1

Refer to Section 1.3: Reset & power supply supervisor on page 8.

6.1.3

Boot mode
The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to Section 3: Boot configuration on page 16.

Note:

In low-power mode (more specially in Standby mode) the boot mode is mandatory to be able to connect to tools (the device should boot from the SRAM).

6.1.4

SWJ interface
The reference design shows the connection between the STM32F10xxx and a standard JTAG connector. Refer to Section 4: Debug management on page 18.

Note:

It is recommended to connect the reset pins so as to be able to reset the application from the tools.

6.1.5

Power supply
Refer to Section 1: Power supplies on page 6.

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Reference design

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6.2

Component references
Table 4. Mandatory components
Reference STM32F103ZE(T6) 100 nF 10 F Quantity 1 11 1 Comments 144-pin package Ceramic capacitors (decoupling capacitors) Ceramic capacitor (decoupling capacitor) Id Components name 1 Microcontroller 2 Capacitors 3 Capacitor

Table 5.

Optional components
Reference 10 k Quantity 5 Comments pull-up and pull-down for JTAG and Boot mode. used for HSE: the value depends on the crystal characteristics. This resistor value is given only as a typical example. used for LSE: the value depends on the crystal characteristics. This resistor value is given only as a typical example. Ceramic capacitor used for LSE: the value depends on the crystal characteristics. used for HSE: the value depends on the crystal characteristics. used for HSE used for LSE

Id Components name 1 Resistor

2

Resistor

390

1

3

Resistor

0

1

4 5 6 7 8 9 10 11 12

Capacitor Capacitor Capacitor Quar tz Quar tz JTAG connector Batter y Switch Push-button

100 nF 10 pF 20 pF 8 MHz 32 kHz HE10 3V3 3V3 B1

1 2 2 1 1 1 1 2 1

If no external battery is used in the application, VBAT must be connected externally to VDD Used to select the right boot mode

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AN2586

U1A U1B

VDD

CN1 JTAG VDD

34 35 36 37 40 41 42 43 100 101 102 103 104 105 109 110 71 107 143 38 16 51 61 83 94 120 130 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VREFVSSA VBAT STM32F103ZET6 R1 10K 2 3 R2 R3 10K 10K R4 10K VDD 1 SW1 Vbat VREF+ VDDA 32 33 6 1) 1 2 3 JP1 VDD_11 VDD_10 VDD_9 VDD_8 VDD_7 VDD_6 VDD_5 VDD_4 VDD_3 VDD_2 VDD_1 31 30 PA0-WKUP P A1 P A2 P A3 P A4 P A5 P A6 P A7 P A8 P A9 P A10 P A11 P A12 P A13 P A14 P A15 131 121 95 84 62 52 17 39 144 108 72 P G15 P G14 P G13 P G12 P G11 P G10 P G9 P G8 P G7 P G6 P G5 P G4 P G3 P G2 P G1 P G0

132 129 128 127 126 125 124 93 92 91 90 89 88 87 57 56

CR1220 holder BT1

Boot Mode
Boot 1
46 47 48 133 134 135 136 137 139 140 69 70 73 74 75 76 P B0 P B1 PB2-BOOT1 P B3 P B4 P B5 P B6 P B7 P B8 P B9 P B10 P B11 P B12 P B13 P B14 P B15 PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 55 54 53 50 49 22 21 20 19 18 15 14 13 12 11 10

JTAG connector

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

MCU Supply

VDD Default setting: 2<->3

2) R9 0

C1

LSE
2 1

10pF 32K X1
3 4

C2 R8 390 VDD 2 138 BOOT0 106 NC C3 3 R7 10K 1 SW2 10pF

OSC_IN OSC_OUT

26 27 28 29 44 45 96 97 98 99 111 112 113 7 8 9 P C0 P C1 P C2 P C3 P C4 P C5 P C6 P C7 P C8 P C9 P C10 P C11 P C12 P C13-ANTI_TAMP PC14-OSC32_IN P C15-OSC32_OUT P E15 P E14 P E13 P E12 P E11 P E10 P E9 P E8 P E7 P E6 P E5 P E4 P E3 P E2 P E1 P E0

68 67 66 65 64 63 60 59 58 5 4 3 2 1 142 141 VDD C17 10 F C16 100nF C15 100nF C14 100nF C13 100nF C12 100nF C11 100nF C10 100nF C9 100nF C8 100nF C7 100nF C6 100nF

2

3

1

Reference design

Reset

4

2. To be able to reset the device from the tools this resistor has to be kept.
Boot Mode
Boot 0

MCU
OSC_IN OSC_OUT

HSE
OSC_IN 23 24 OSC_OUT 8MHz X2

Decoupling Capacitor

Figure 15. STM32F103ZE(T6) microcontroller reference schematic

20pF C4 R6 390 RESET# 25 20pF

1. If no external battery is used in the application, VBAT must be connected externally to VDD
NRST P D15 P D14 P D13 P D12 P D11 P D10 P D9 P D8 P D7 P D6 P D5 P D4 P D3 P D2 P D1 P D0 STM32F103ZET6 86 85 82 81 80 79 78 77 123 122 119 118 117 116 115 114 B1 C5 100nF

MCU

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Reference design Table 6.
Pin name 144 pins 100 pins 64 pins OSC_IN OSC_OUT PC15OSC32_OUT PC14OSC32_IN BOOT0 PB2-BOOT1 NRST PA13 PA14 PA15 PB4 PB3 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 23 24 9 8 138 48 25 105 109 110 134 133 71 107 143 38 16 51 61 83 94 120 130 72 108 144 39 17 52 62 84 12 13 9 8 94 37 14 72 76 77 90 89 49 74 99 27 10 50 75 100 28 11 5 6 4 3 60 28 7 46 48 50 56 55 31 47 63 18 32 48 64 19 -

AN2586 Reference connection for all packages
Pin numbers for LQFP packages Pin numbers for BGA packages Pin numbers for VFQFPN package 36 pins 2 3 35 17 4 25 28 29 31 30 18 26 36 F7 19 27 F5 F4 D2 1 -

48 pins 144 pins 100 pins 5 6 4 3 44 20 7 34 37 38 40 39 23 35 47 24 36 48 D1 E1 C1 B1 D5 J5 F1 A12 A11 A10 A6 A7 H7 G9 E5 G4 D2 H5 H6 G8 G10 E7 E6 G7 F9 F5 F4 D3 G5 G6 F8 C1 D1 B1 A1 D5 G5 E1 A10 A9 A8 A6 A7 E7 E6 E5 E4 C2 -

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AN2586 Table 6.
Pin name 144 pins 100 pins 64 pins VDD_9 VDD_10 VDD_11 VREF+ VREFVSSA VDDA VBAT 95 121 131 32 31 30 33 6 21 20 19 22 6 12 13 1

Reference design Reference connection for all packages (continued)
Pin numbers for LQFP packages Pin numbers for BGA packages Pin numbers for VFQFPN package 36 pins -

48 pins 144 pins 100 pins 8 9 1 F10 F7 F6 L1 K1 J1 M1 C2 J1 H1 G1 K1 B2

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Revision history

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7

Revision history
Table 7.
Date 12-Jul-2007

Document revision history
Revision 1 Initial release. Application note also applicable to High-density devices. Figure 1: Power supply overview , Figure 2: Power supply scheme and Figure 6: Clock overview updated. Low-speed internal RC frequency modified in Section 2: Clocks on page 11. VREF+ voltage range modified. Table 6: Reference connection for all packages on page 26 added. Small text changes. Changes

23-May-2008

2

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AN2586

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Document Number: 13675



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