AN2683 Application note
Compact dual output point of load converter based on the PM6680 step-down controller
Introduction
This application note demonstrates the performance of the PM6680 dual step-down controller by implementing a two output point of load converter in a small printed circuit board footprint. Utilizing constant on-time architecture and featuring a no-audio skip mode of operation, a common bus voltage that ranges between 10 to 16 VDC is converted to 1.0 VDC at 10.5 amps and 1.8 VDC at 2.5 amps for a total output power level of 15 watts. The unique no-audio skip feature significantly improves efficiency at light load. Using surface mount components on both the top and bottom of the circuit board and featuring ceramic output capacitors, the area needed for the converter measures only 1.0 by 1.25 inches (25.4 by 37.75 mm). The method for component value dimensioning is described along with the schematic and construction details. Typical efficiencies and functional test data are also presented. Figure 1. PM6680 - top and bottom view
April 2008
Rev 1
1/38
www.st.com
Contents
AN2683
Contents
1 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 1.2 1.3 1.4 Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Output ripple voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Output overload/short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 3 4
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Functional testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 4.2 4.3 4.4 4.5 4.6 Input/output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ripple/noise voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Load transient overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Output current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Output short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Input under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 6
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/38
AN2683
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. PM6680 - top and bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Circuit board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Components of virtual ESR network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Top layer component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Top layer copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Inner layer 1 showing additional power traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power ground layer (inner layer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Signal ground layer (inner layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Bottom layer components placement (mirrored). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bottom layer copper (mirrored) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Inner layer 4 (mirrored) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Efficiency vs. load current in PWM mode (1.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Efficiency vs. load current in NA-skip mode (1.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Efficiency vs. load current in PWM mode (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Efficiency vs. load current in NA-skip mode (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VDC output - 100% to 50% load change (20s/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VDC output - 50% to 100% load change (20s/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VDC output - 20% to 80% step load change (50s/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VDC output - 100% to 50% load change (20s/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VDC output - 50% to 100% load change (20s/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 VDC output - 20% to 80% step load change (50s/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/38
List of tables
AN2683
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Input voltage range 10 - 16 VDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.0 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.8 VDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4/38
AN2683
Main characteristics
1
1.1
Main characteristics
Input voltage range
Table 1.
Output 1 2
Input voltage range 10 - 16 VDC
Nominal voltage VDC 1.8 1.0 Max. current amp 2.5 10.5 Regulation %(1) 0.44 2.6
1. Regulation over entire line and load range
1.2
Output ripple voltage
Output 1: 45 mV p-p at maximum output current Output 2: 30 mV p-p at maximum output current
1.3
Switching frequency
Output 1: 1 - 300 kHz Output 2: 2 - 400 kHz
1.4
Output overload/short circuit
Output 1: nominal trip level 3.37 A (135%) Output 2: nominal trip level 13.65 A (130%)
Protection is latched. Power must be cycled to reset.
5/38
Circuit description
AN2683
2
Circuit description
The PM6680 contains all the control circuitry needed to implement two independent stepdown synchronous buck regulators using the constant on-time method. The constant ontime method, an improved variant of hysteretic control, provides superior transient response to changes of input voltage and load levels. One of the big advantages of this control method is that it can provide this quick response without the use of an error amplifier which in turn eliminates the need for frequency compensation. As shown in the photographs (Figure 1) all the parts used are surface mount type including the inductors. The circuit board is a multiple layer type consisting of six layers. The top two layers are power routing, the middle two are ground layers split as power and signal, and the bottom two are signal routing layers. In this design, in order to have a low inductor value for the higher current 10.5 A output side, the PM6680 runs in its intermediate range with output one running at 300 kHz and output two running at 400 kHz. So as a consequence the 2.5 A output will run at 300 kHz. With the switching frequencies established the dimensions of the other components can be defined.
6/38
AN2683 Figure 2.
P1
1
+
R4 3R92 1/4W 1% R17 110k C8 10 uF C4
Vin 10.2
2 1 2
1/8W C17 100pF R18 30.0k C6 10 uF C7 10 uF
- 16.0 VDC
P2
C5 4.7uF C3 0.22uF 0.1uF R3 47R5 1%
QC
2
K1
C22 4.7uF BAT54A D1 C21 1uF
1
STS12NH3LL
A
1
Q1 R1 10R0
Circuit board schematic
5
4
K2
Vout2
7 2
- 1.0 VDC @ 10.5 A
2 9 31 19
2 8 1
P3
1
R8 5.11k
6 C1 0.1uF
3
R2 C2 10R0 0.1uF
2
2
2
1
1
QC
R10 3.74k 1 2 STS8DNF3LL 57.6k 1 2 R9 L2 5 6 4 1.8nF QC 2 1 P5 C10
LD05
C20 11 Phase2 Lgate2 Csense2 PGnd SGnd1 Out2 Comp2 SGnd2 FB2 Pgood2 Pgood1 FB1 Shdn Comp1 30 26 28 5 Out1 29 U1 PM6680 V5SW 17 Csense1 20 1 R6 750R Lgate1 15 2 Phase1 21 Hgate1 13 1 12 14 750R R5 2 22
C15
C19
0.7uH
Boot2
Boot1
Hgate2
Vcc
10
Vin
C9
1.8nF
7 8
QC
1
18
23
R7 26.1k
Vout
K
MSS1038 2.5 uH C16 47uF
1 - 1.8 VDC @ 2.5 A
1
R15 10.0k
1
L1
MLC1550
47uF
100uF
100uF
R13 1.10k
2
3
K
5 1 6 8 7 2 2 8 16 Q2 7 STS25NH3LL 27 1 3
4
Q3
1
A
D2 Open
R14
P4
D3 Open
10.0k
QC
A
1 C14 22pF C13 330pF
R12 2.55k
2 QC P6
2
1
R16 10.0k
nc
Fsel
Vref
En1
R11
6
3
1.91k C11 330pF C12 22pF
24
C18
Circuit description
0.1uF
32
25
4
1
2
Skip
En2
2
2
7/38
Circuit description
AN2683
As a starting point for the value of the inductors we look at the full load current (Ifl) for each output and let the inductor ripple (Ir) current equal 20 to 30 percent of it. For this design a value of 30 percent is used. Ir = Ifl * 0.3 for
Output 1: Ir = 0.75 A Output 2: Ir = 3.15 A
Then the values of the inductors are calculated using the formula: Equation 1:
Vi n Vo u t Vo u t L = ------------------------ ---------fsw Ir Vin
where Vin is the nominal input voltage, Vout the output voltage and fsw the switching frequency. So for input 1: Equation 2
12 1.8 1.8 L = --------------------------------------- ------- = 6.8 H 300 k H z 0.75 12
and for output 2: Equation 3
12 1 12 L = --------------------------------------- ----- = 0.7 H 400 k H z 3.15 1
The output filter capacitors are roughly approximated so that the change in output voltage (Vout) during a positive load transient (load is reduced) is minimized. For this design an output voltage change of two to three percent of the total output voltage is considered acceptable. The formula used is: Equation 4
L ( Ifl )2 C > --------------------------------------------------------------2 ( Vin Vout ) Vout
8/38
AN2683 For output 1 a Vout of 2.5% of 1.8 VDC or 45 mV is used, thus: Equation 5
Circuit description
6.8 H ( 2.5 ) 2 46.2 F > ---------------------------------------------------------2 ( 12 1.8 ) 0.045
This is a nonstandard value so a 47 F is used. For output 2 a Vout of 2% of 1.0 VDC or 20 mV is used: Equation 6
0.7 H ( 10.5 ) 2 175 F > ---------------------------------------------------------2 ( 12 1.0 ) 0.020
As the formula indicates the capacitor value should be greater than that calculated. Even though the board area is small, this section allows the use of ceramic capacitors that are comprised of two 100 F and one 47 F all in parallel and which still fit in the required footprint. With these values of capacitors the ripple voltage can be checked. This is dominated by the equivalent series resistance (ESR) of the capacitors. The ESR must be equal or less than the value calculated by: Equation 7:
Vr E S R ---Ir
where Vr is the output ripple voltage and Ir is the inductor ripple current. The ESR for the capacitors is given in their datasheets at the frequency they are used at as shown in the graphs. The value is basically the same at both 300 and 400 kHz. For the 47 F the ESR is 2 m and for the 100 F it is 1.5 m With these values we can calculate the ripple voltage . Vr by: Equation 8:
Vr = Ir E S R
9/38
Circuit description for output 1: Equation 9
AN2683
0.75 A 2 m = 1.5 m V
for output 2: Equation 10
3.15 A 545 = 1.9 m V
These values conform to the specification. They are higher in a practical circuit because of parasitic inductance and loop resistance. Good circuit board layout techniques are essential. Additionally, because of the constant on-time control, the system regulates the output voltage by the valley value of the ripple voltage. A minimum amount of ripple voltage of 30 mV should be on the comp pin to accomplish this. Since the calculated ripple voltage is much lower than this, an additional circuit called the virtual ESR network is incorporated to provide the additional voltage. Before addressing this design, the current limit resistor values will be established. In this design the RDS(on) of the lower MOSFETS is used to implement the current limit. For output 1 with its relatively low output current the MOSFET chosen was the STS8DNF3LL with a nominal RDS(on) of 18 m This particular part is a . dual, that is two MOSFETs are contained in the same SO-8 package realizing further circuit board space savings. The current limit is a valley type that operates during the conduction of the low side MOSFET. A 100 A internal current generator connected to the Csense pin along with a resistor establishes a voltage to which the voltage generated by the RDS(on) is compared. If the RDS(on) voltage is greater, then the voltage at the Csense pin the generation of a new conduction cycle is inhibited. The value of Rcsense is determined by: Equation 11:
RDS( o ) Iv lley R c s e n s e = ----------------n--------------a--------100 A
The 18 m value for RDS(on) is a nominal 25 C number. As current is switched through the device and the ambient is raised, the RDS(on) increases. An increase of approximately 140% is used. Targeting the maximum output current (Ioutmax) at 3.375 A and having a Ir of 0.750 A the valley current value is:
10/38
AN2683 Equation 12
Circuit description
I I v a l l e y = I o u t ( m a x ) --r 2
then: Equation 13
0.750 3.375 A -------------- = 3.0 A 2
Rcsense is then: Equation 14
25 m 3.0 A ----------------------------------- = 750 100 A
For output 2 the current levels are substantially higher than output 1 and two discrete MOSFETS must be used. With a nominal input voltage of 12 volts and a one volt output the low side MOSFET is conducting over 90 percent of the time. This means that the RDS(on) of the low side MOSFET must be as low as possible. For this design the STS25NH3LL MOSFET with a nominal 3.2 m on resistance is used. Because of the high current and duty cycle an RDS(on) multiplier of 200% for the Rcsense calculation is used. Again targeting the output 2 maximum current at 13.65 A the valley current is: Equation 15
3.15 A 13.65 A --------------- = 12.075 A 2
Rcsense for output 2 then is: Equation 16
6-----------------------------.----5-----.4 m 12-7---A = 773 100 A
11/38
Circuit description
AN2683
With the maximum output currents established attention can be redirected at designing the virtual ESR network. As mentioned earlier, the ripple voltage should be greater than 30 mV and range between 30 to 50 mV. To derive the necessary minimum value of the virtual ESR (VESR) to produce the ripple voltage the following formula is used: Equation 17
0.05 V V E S R ( m i n ) = --------------- E S R c o u t Ir
for output 1: Equation 18
0------------ 2 m = 64.6 m ---.05 V 0.75 A
for output 2: Equation 19
0------------ 0.545 m = 15.3 m ---.05 V 3.15 A
The total ESR (ESRtot) is the sum of the virtual ESR (VESR) and the ESR (ESRcout) of the output capacitor. for output 1: Equation 20
64.6 m + 2 m = 66.6 m
for output 2: Equation 21
15.3 m + 0.545 m = 15.8 m
12/38
AN2683
Circuit description The first component to be dimensioned in the virtual ESR network is Cint as shown in Figure 3 below. Before this can be done the corner frequency (fz) of the output capacitor must be determined by: Equation 22
1 f Z = -----------------------------------2 Co u t E S Rt o t
Figure 3.
Components of virtual ESR network
for output 1: Equation 23
1 --------------------------------------------------- = 50.56 k H z 2 47 F 67 m
13/38
Circuit description for output 2: Equation 24
AN2683
1 -------------------------------------------------------------- = 41.46 k H z 2 247 F 15.54 m
With fz established the stability of the system needs to be verified. The system is stable if the switching frequency (fsw) is greater than 4 times the corner frequency (fz) of Cout; fsw > fz x 4. for output 1: Equation 25
50.56 k H z 4 = 202.2 k H z
Equation 26
202.2 k H z < 300 k H z
OK
for output 2: Equation 27
41.46 k H z 4 = 165.8 k H z
Equation 28
165.8 k H z < 400 k H z
OK
The value of Cint is actually computed three different ways. The maximum value that results from the computations is the value that should be used. In the formulas for calculating Cint the following constants are used: gm = 50 s (the transconductance of the integrator amplifier); k = 4; Vr = 0.9 V (internal reference voltage).
14/38
AN2683 Equation 29
Vr gm C i n t > -------------------------------- ---------Vo u t fsw 2 -------- f z k Vr -----g---------- ----------- m 2 fz Vo u t
Circuit description
or
or
6 A C o u t -------------------------------Io u t ( m a x ) Ir ---------------------- + -4 2
for output 1: Equation 30
50 s ------------------------------------------------------------------------ 0--9--- = 162.8 p F - ---.---V 00 k H z 3----------------- 50.56 k H z 1.8 V 2 -- 4
or Equation 31
5-- s -----------------0-------------------- 0-------- = 78.7 p F ---.9 V 2 50.56 k H z 1.8 V
or Equation 32
-----6---------------------------F---- = 231.3 p F -- A 47 --3--------------- + 0--------------.375 A ---.75 A 4 2
for output 2 Equation 33
50 s ------------------------------------------------------------------------ 0--9--- = 122.4 p F - ---.---V 00 k H z 4----------------- 41.46 k H z 1.0 V 2 -- 4
or
15/38
Circuit description Equation 34
AN2683
5-- s -----------------0-------------------- 0-------- = 172.8 p F ---.9 V 2 41.46 k H z 1.0 V
or Equation 35
6 ---A - 2---7 F ---------------------4------------- = 297.1 p F 1--------------- + 3--------------3.65 A ---.15 A 4 2
Standard values must be used. In both cases a value rounded up to 330 pF will be used for Cint. The next part of the network to be calculated is the capacitor Cfilt. The formula for this part is straightforward which is: Equation 36
Ci t ( 1 q ) C f i l t = ------n-------------------------q
Where q is an attenuation factor equal to 0.95. Since Cint is the same for both outputs Cfilt is the same for both outputs: Equation 37
3----------------------------------0----------- = 17.3 p F ---30 p F ( 1 --.95 ) 0.95
A standard value of 22 pF is used. Building on the previous calculations the value of Rint is the next part to be established. The formula for Rint is given below: Equation 38
1 R i n t = ----------------------------------------------------------------------Cint Cfilt 2 10 f s w -------------------------Cint + Cfilt
16/38
AN2683 for output 1: Equation 39
Circuit description
1 R i n t = ----------------------------------------------------------------------------------------------- = 2570 330 p F 22 p F 2 10 300 k H z -------------------------------------330 p F + 22 p F
using standard value 2.55 k for output 2: Equation 40
1 R i n t = ----------------------------------------------------------------------------------------------- = 1929 330 p F 22 p F 2 10 400 k H z -------------------------------------330 p F + 22 p F
using standard value 1.91 k Then, the value of the C of the virtual ESR network is calculated. It is simply: Equation 41
C = Cint 5
Since Cint is the same for both outputs: Equation 42
C = 330 p F 5 = 1650 p F
Use standard value 1.8 nF. Next, the R value of the network is established. This is determined by the formula: Equation 43
L R = ----------------------------E S Rtot C
17/38
Circuit description for output 1: Equation 44
AN2683
6-8 H ---------------.---------------------- = 58.12 K 65 m 1.8 n F
for output 2: Equation 45
0-7 H ---------------.---------------------- = 25.92 K 15 m 1.8 n F
The standard value of 57.6 K can be used for output 1 and 26.1 K for output 2. Finally the last component of the virtual ESR network R1 is computed with the formula: Equation 46
1 R ----------- C f z R 1 = ---------------------------1 R ----------C fz
for output 1: Equation 47
1 57.6 K --------------------------------------------- 1.8 n F 50.56 k H z ------------------------------------------------------------------------------ = 3723 1 57.6 K --------------------------------------------1.8 n F 50.56 k H z
for output 2: Equation 48
1 26.1 K --------------------------------------------- 1.8 n F 41.46 k H z ------------------------------------------------------------------------------ = 5098 1 26.1 K --------------------------------------------1.8 n F 41.46 k H z
The standard value of 3.74 K can be used for output 1 and 5.11 K for output 2. With the design of the virtual ESR complete the only other output components to be determined are the resistor dividers that connect to the feedback pins FB1 and FB2. With an internal reference voltage (Vr) of 0.9 volts the determination of the values is straightforward by:
18/38
AN2683 Equation 49
Circuit description
Vout V R 2 = ---------------------r Vr ------R1
where R1 is the resistor connecting the feedback pin to ground (resistors R14 and R16 in the schematic) and R2 is the resistor connecting the output to the feedback pin (resistors R13 and R15 in the schematic). The value for R1 is chosen as 10.0 K for both outputs. The value for R2 is then: for output 1: Equation 50
1.8 V 0.9 V R 2 = ------------------------------ = 10 K 0.9 ------------V10 K
for output 2: Equation 51
1.0 V 0.9 V R 2 = ------------------------------ = 1.11 K 0.9 ------------V10 K
Use standard values 10.0 K ohm for R15 and 1.10 K ohm for R13. With the output component values determined it is important not to overlook the dimensioning of input components critical to proper operation. These are the input capacitors that provide the high frequency input currents needed by the converters. Locate these capacitors as close as possible to the drain of the upper MOSFET and also make sure to minimize the inductance to the other power components on the power ground plane. The ripple current (Ir) ratings should meet or exceed the value as computed below: Equation 52
2 2
Ir =
D1 Iout1 ( 1 D1 ) + D2 Iout2 ( 1 D2 )
where D is the duty cycle of the converter and is given by:
19/38
Circuit description Equation 53
AN2683
Vout D = ---------Vin
and Iout is the maximum output current of the converter. For output 1 D1 is: Equation 54
1-------- = 0.15 ---.8 V 12 V
For output 2 D2 is: Equation 55
1.0 V ----------- = 0.083 12 V
So then we have: Equation 56
2 2
Ir =
0.15 3.375 ( 1 0.15 ) + 0.083 13.65 ( 1 0.083 ) = 3.95 A
20/38
AN2683
Construction
3
Construction
With the components dimensioned the construction of the circuit board can be considered. With this type of high frequency converter separate power and signal grounds are a must. Additionally, the small board area necessitated component placement on both sides and the use of additional layers for routing the signal interconnects and providing lower conductor resistance in the heavy current paths. In Figure 4. below the top layer component placement is shown. The top layer components are comprised of the power handling ones such as the MOSFETS and inductors. Along with the power component placement is Figure 5 that shows the top copper power traces. The first inner layer shown in Figure 6 is a layer that has redundant power traces to lower resistance in the high current paths. The power ground and signal ground layers are shown in Figure 7 and 8 respectively. Care must be taken that they connect at only one point close to pin 14 of the PM6680. The component placement for the bottom layer is shown in Figure 9, these are the parts that do the signal conditioning and connect to the PM6680 controller. Of special note on the bottom layer copper shown in Figure 10, is the square copper island under U1 (the PM6680). This island connects to the thermal sink contact that is on the bottom of the package. A requirement for proper operation is that this pad be connected to signal ground. As shown in Figure 11, which is the fourth inner layer used for additional signal routing, a matrix of nine vias are used to make the connection to the signal ground layer. The board uses 1-ounce copper on all layers. While not necessary for the signal traces, keeping the copper weight even on all the layers reduces the chances of the board warping during the manufacturing process. Figure 4. Top layer component placement
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Construction Figure 5. Top layer copper
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Figure 6.
Inner layer 1 showing additional power traces
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AN2683 Figure 7. Power ground layer (inner layer 2)
Construction
Figure 8.
Signal ground layer (inner layer 3)
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Construction Figure 9. Bottom layer components placement (mirrored)
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Figure 10. Bottom layer copper (mirrored)
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AN2683 Figure 11. Inner layer 4 (mirrored)
Construction
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Functional testing
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4
Functional testing
Using the component values calculated the demonstration board's efficiency was evaluated. Each converter was tested individually with the idle converter disabled by grounding its enable pin so that the power consumed by the idle converter's MOSFET driver section would not be included in the input power calculation. The efficiency of each section was measured in two different modes of operation, normal PWM and no-audible skip mode. In all cases the input voltage was set to 12.0 VDC. Figure 12. Efficiency vs. load current in PWM mode (1.0 V)
1.0V Eff vs Load Current in PWM mode 10 0 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 11 Load Current
% Efficiency
Eff vs Load I
Figure 13. Efficiency vs. load current in NA-skip mode (1.0 V)
1.0V Eff vs Load Current in NA-Skip mode 100 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 11 Load Current
% Efficiency
Eff vs Load I
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Functional testing As can be seen at significant load current the efficiency for the 1.0 V output averages in the lower eighty percent area. Additionally, the graph for no-audible skip mode shows the advantage of running in this mode. By using the current zero-crossing detector the condition of negative current that occurs at light load is sensed. The control circuit then keeps the average current equal to the load current by skipping cycles. The result is higher efficiency at light load. As the load is increased and the inductor current does not go to zero, normal PWM operation is resumed. Figure 14. Efficiency vs. load current in PWM mode (1.8 V)
1.8V Eff vs Load Current in PWM mode 10 0 90 80 70 60 50 40 30 20 10 0 0 1 2 3 Load Current
% Efficiency
Eff vs Load I
Figure 15. Efficiency vs. load current in NA-skip mode (1.8 V)
1.8V Eff vs Load Current in NA-Skip mode 100 90 80 70 60 50 40 30 20 10 0 0 1 2 3 Load Current
% Efficiency
Eff vs Load I
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Functional testing
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The graphs in Figure 14 and 15 show that the 1.8 V output has better efficiency than the 1.0 V output, in the high eighties at high current levels. Along with the efficiency measurements further functional testing was conducted as outlined in the following sections.
4.1
Input/output voltage
The input voltage was swept from 10.2 to 16 VDC at the load levels indicated. The output voltage was recorded at each level and did not vary more than 1 mV over the entire input range. Input/output voltage at different load levels. Table 2. 1.0 VDC output
Load current 50 mA 7.5 A 10.5 A Output voltage 0.998 VDC 1.019 VDC 1.027 VDC
Table 3.
1.8 VDC output
Load current 50 mA 1.8 A 2.5 A Output voltage 1.792 VDC 1.794 VDC 1.794 VDC
4.2
Ripple/noise voltage
The maximum peak to peak ripple voltage was measured at the load level indicated. Table 4. 1.0 VDC output
Load current 10.5 A Ripple voltage p-p 25 mV
Table 5.
1.8 VDC output
Load current 2.5 A Ripple voltage p-p 20 mV
4.3
Load transient overshoot
The output load levels were varied in a stepwise fashion at the percentage and load levels indicated. The maximum change in output voltage was recorded in the following oscilloscope photographs.
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Functional testing
Table 6.
1.0 VDC output
Percent load change 100 to 50% 50 to 100% 20 to 80% Current level change (A) 5.25 to 10.5 5.25 to 10.5 2.0 to 8.5
Figure 16. VDC output - 100% to 50% load change (20s/div)
where:
Top trace - L1 current 2 A/division Bottom trace - output voltage 50 mV/division
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Functional testing Figure 17. VDC output - 50% to 100% load change (20s/div)
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where:
Top trace - L1 current 2 A/division Bottom trace - output voltage 50 mV/division
Figure 18. VDC output - 20% to 80% step load change (50s/div)
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AN2683 where:
Functional testing
Top trace - L1 current 2 A/division Bottom trace - output voltage 50 mV/division 1.8 VDC output
Percent load change 100 to 50% 50 to 100% 20 to 80% Current level change (A) 2.5 to 1.25 1.25 to 2.5 0.5 to 2
Table 7.
Figure 19. VDC output - 100% to 50% load change (20s/div)
where:
Top trace - L1 current 0.5 A/division Bottom trace - output voltage 50 mV/division
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Functional testing Figure 20. VDC output - 50% to 100% load change (20s/div)
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where:
Top trace - L1 current 0.5 A/division Bottom trace - output voltage 50 mV/division
Figure 21. VDC output - 20% to 80% step load change (50s/div)
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Functional testing
Top trace - L1 current 0.5 A/division Bottom trace - output voltage 50 mV/division
4.4
Output current limit
Each output was loaded to its maximum rated load level. The load was increased in 10% increments of the maximum rated load until the overcurrent limiting functioned. The level was recorded. Table 8. 1.0 VDC output
Percent of maximum load (A) 130% (13.65)
Table 9.
1.8 VDC output
Percent of maximum load (A) 130% (3.25)
After the overcurrent limit functioned, the load level was adjusted back the maximum rated level and the input power was shut off and reapplied. The outputs resumed to normal operation.
4.5
Output short circuit
Each output in turn was loaded to its maximum rated load level. A short was then applied to the output at which time the overcurrent protection functioned. The opposite output remained running. The short was then removed and the output remained latched off. The input power was removed and then reapplied. The output resumed normal function. With input power removed, each output in turn was shorted. Then input power was applied. The shorted output's current limiting function operated while the non-shorted output ran normally. The short was then removed and the input power was recycled. The output resumed normal function.
4.6
Input under voltage lockout
With each output loaded to its nominal load level the input voltage was slowly increased from 0 to 6 VDC and the output voltages were recorded. The input voltage was then slowly increased from 6 to 8 VDC and the output voltages were recorded. The voltage at which the device turns on is adjusted by the voltage divider consisting of R17 and R18 connected to the SHDN pin(5). The typical turn-on threshold is 1.35 VDC and the device typically shuts down with 0.85 VDC on the pin.
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Functional testing
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Table 10.
1.0 VDC output
Voltage at Vin 6 VDC 0.0 Voltage at Vin 8 VDC 1.017
Table 11.
1.8 VDC output
Voltage at Vin 6 VDC 0.0 Voltage at Vin 8 VDC 1.795
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Bill of material
5
Table 12.
Bill of material
Part list
Value / type 0.1 F 50 V X5R 0.1 F 50 V X5R 0.1 F 50 V X5R 0.22 F 25 V X5R 4.7 F 25 V X5R 10 F 25 V X5R 10 F 25 V X5R 10 F 25 V X5R 1.8 nF 50 V X5R 1.8 nF 50 V X5R 330 pF 50 V NPO 22 pF 50 V NPO 330 pF 50 V NPO 22 pF 50 V NPO 100 F 6.3 V X5R 47 F 6.3 V X5R 100 pF 50 V NPO 0.1 F 50 V X5R 100 F 6.3 V X5R 47 F 6.3 V X5R 4.7 F 25 V X5R 1 F 16 V X5R PCB footprint SM_0805 SM_0805 SM_0805 SM_0805 SM_1210 SM_1206 SM_1206 SM_1206 SM_0805 SM_0805 SM_0603 SM_0603 SM_0603 SM_0603 SM_1210 SM_1206 SM_0603 SM_0805 SM_1210 SM_1206 SM_1210 SM_0603 SOT-23 DO-214AC DO-214AC Custom Custom SO-8 SO-8 Coilcraft Coilcraft STMicroelectronics STMicroelectronics MLC1265-701MLB MSS1038-702NLB STS12NH3LL STS25NH3LL Manufacturer Any Any Any Any Any Any Any Any Any Any Any Any Any Any TDK or equivalent TDK or equivalent Any Any TDK or equivalent TDK or equivalent Any Any STMicroelectronics BAT54A C3225X5ROJ107K C3216X5ROJ476K C3225X5ROJ107K C3216X5ROJ476K P/N
Part reference C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 L1 L2 Q1 Q2
BAT54A dual
Schottky
Open Open 0.7 H 17 A 7.0 H 4.35 A STS12NH3LL MOSFET STS25NH3LL MOSFET
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Bill of material Table 12. Part list (continued)
Value / type STS8DNF3LL dual MOSFET 10R0 1% 10R0 1% 47R5 1% 3R92 1% 750R 1% 750R 1% 21.6k 1% 5.11k 1% 57.6k 1% 3.74k 1% 1.91k 1% 2.55k 1% 1.10k 1% 10.0k 1% 10.0k 1% 10.0k 1% 110k 1% 30.0k 1% PM6680 Dual Dc-Dc Controller PCB footprint SO-8 SM_0805 SM_0805 SM_0805 SM_1206 SM_0805 SM_0805 SM_0805 SM_0805 SM_0805 SM_0805 SM_0805 SM_0805 SM_0603 SM_0603 SM_0603 SM_0603 SM_0603 SM_0603 VFQFPN-32 5x5 Manufacturer STMicroelectronics Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any STMicroelectronics P/N
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Part reference Q3 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 U1
STS8DNF3LL
PM6680
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Revision history
6
Revision history
Table 13.
Date 15-Apr-2008
Document revision history
Revision 1 Initial release. Changes
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