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2X36 W digital dimmable ballast with L6574 and ST7FDALI
Application Note
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Last Updated: 10/03/2008
Pages: 42
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AN2708 Application note
2X36 W digital dimmable ballast with L6574 and ST7FDALI
Introduction
This document describes a high-efficiency, high power factor, low THD and digital dimming electronic ballast designed to drive 2X36 W T8 tube lamps. The system consists of three main blocks: The high-frequency ballast includes an active power factor correction circuit based on the L6562 for universal input voltage as well as a ballast control circuit based on the L6574. The digital dimming is performed by interfacing the ST7FDALI microcontroller with the analog half-bridge driver. The DALI control unit is dedicated to address the slaves, to display the lamp status and to send the dimming commands. This unit is provided with a keyboard which allows setting different dimming scenes over a wide range (5-100%) as well as putting in standby and restarting the ballast. The DALI communication protocol includes single and group mode, as well as broadcast mode to address the slaves. The AC-DC adapter is based on the VIPer12A-E. This is an offline double-output isolated power supply in DCM flyback configuration. The outputs are set for 20 V to supply the communication bus and for 5 V to supply the MASTER microcontroller. The three blocks are described in detail and their performances are shown. In addition some of DALI basics are explained.
March 2008
Rev 1
1/42
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Contents
AN2708
Contents
1 2 Block diagram and system operating conditions . . . . . . . . . . . . . . . . . 5 High-frequency ballast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 PFC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Half-bridge inverter and ballast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 Lamp dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Lamp turn-on and lamp turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Verification of lamp status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ballast performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3
DALI master unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Master unit schematic and bill of material . . . . . . . . . . . . . . . . . . . . . . . . 26
4 5
Basics of DALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DALI master AC-DC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 5.2 5.3 Adapter description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Adapter bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Adapter performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 Steady state tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Star tup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Dynamic load tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Efficiency variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Conducted emissions test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6 7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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AN2708
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. System operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ballast-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ballast bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PFC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power stage design equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 L6562 biasing circuitry design equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Lamp parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 L6574 biasing circuitry design equations for operating conditions . . . . . . . . . . . . . . . . . . . 16 Ballast performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Master unit bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SMPS operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Adapter bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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List of figures
AN2708
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2X36 W digital dimmable ballast with L6574 and ST7FDALI . . . . . . . . . . . . . . . . . . . . . . . . 6 Ballast schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PFC performances at 230 Vac-50 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Lamp ballast model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ballast transfer functions (magnitude) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DALI protocol brightness values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Ballast controls timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Turn-on procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Turn-off procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Forward frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Backward frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ballast startup at 230 Vac-full power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Lamps turn-on at 230 Vac-full power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Lamps running at 230 Vac - full power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Polling keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pressed button event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Master unit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Cable wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Master flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Slave flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Adapter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Adapter PCB layout - top side -silkscreen (to scale). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Adapter PCB layout - bottom side - copper tracks (to scale) . . . . . . . . . . . . . . . . . . . . . . . 34 Flyback transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VIPer12A-E steady state behavior at full load at 110 Vac - 60 Hz . . . . . . . . . . . . . . . . . . 36 VIPer12A-E steady state behavior at full load at 230 Vac - 50 Hz . . . . . . . . . . . . . . . . . . . 36 VIPer12A-E steady state behavior at minimum load at 110 Vac - 60 Hz . . . . . . . . . . . . . . 36 VIPer12A-E steady state behavior at minimum load at 230 Vac - 50 Hz . . . . . . . . . . . . . . 36 Startup waveforms at full load at 110 Vac - 60 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Startup waveforms at full load at 230 Vac - 50 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Startup waveforms at minimum load at 110 Vac - 60 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Startup waveforms at minimum load at 230 Vac - 50 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Dynamic load waveforms at 110 Vac - 60 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Dynamic load waveforms at 230 Vac - 50 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Efficiency variations vs. input voltage at full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Conducted emissions at 110 Vac 60 Hz - full load - line 1 peak detector . . . . . . . . . . . . . . 40 Conducted emissions at 110 Vac 60 Hz - full load - line 2 peak detector . . . . . . . . . . . . . 40 Conducted emissions at 230 Vac 50 Hz - full load - line 1 peak detector . . . . . . . . . . . . . . 41 Conducted emissions at 230 Vac 50 Hz - full load - line 2 peak detector . . . . . . . . . . . . . 41
4/42
AN2708
Block diagram and system operating conditions
1
Block diagram and system operating conditions
Figure 1 shows the block diagram of the system. Figure 1. System block diagram
HIGH FREQUENCY BALLAST
AC DC ADAPTER
MASTER UNIT
SCI Communication Option
SCI communication is considered as an option.
5/42
Block diagram and system operating conditions The present system has been designed according to the following specifications: Table 1. System operating conditions
Parameter Input voltage range Lamp type Circuit power (max) Lamp power (max) Dimming range Power factor Current THD Warm start Standby mode power Value
AN2708
176-265 Vac/50 Hz; 90-140 Vac/60 Hz 2X36 W T8 tube lamps 80 W 72 W 5% to 100% > 0.99 < 10% < 1.5 sec < 0. 6 W
In addition to the previous specs, the DALI communications are optically isolated, the digital dimming is performed with high precision, and the lamp filament preheating time is programmable as well as the ignition time. Figure 2. 2X36 W digital dimmable ballast with L6574 and ST7FDALI
HIGH FREQUENCY BALLAST
MASTER UNIT AC DC ADAPTER
6/42
2
AN2708
Figure 3.
D2 4 1 T1 STTH 1L06 On Air 5 8 R9 750K 1% D3 1N 4148 R 10 750K 1% C 14 100nF L2 1.8mH 8 L1 1.8mH 12 16 I C _GN D VS Q2 STP8N M50 2 R 26_2A 1 3 R 26_2 750K 180K 2 1 2 1 SI GN U2 L6574 OU T 2 Q3 STP8N M50 R 27_2 750K 1 3 4 3 D 11 1N 4148 4 RING CF C PR E GN D EN 2 9 EN 2 R 23 330E D 7 BAT46 3 8 EN 1 D5 BAT46 4 14 6 C9 100nF 5 OPOU T EN 1 R 16 68K R 13 47K R S1 0. 82E 1W R S2 0. 82E 1W R 11 9. 53K 1% D4 1N 4148 LVG 11 OPI N R 22 10E R 27_1 750K Lam p1 T8 36W Lam p2 C 18 8. 2nF 1600V T8 36W R 26_1 750K I C _GN D VBOOT R 12 120K 1 2 R PR E H VG 15 I C _GN D 2 R7 33E + Q1 STP8N M50 3 OPI N + 7 7 1 C6 47uF 400V R 21 10E I C _GN D R 30_1 100K 1W R 30_2 100K 1W C 17 100nF 250V C 21 100nF 250V 1 C 19 100nF + C7 4. 7uF 50V 8 1 DZ1 15V 0. 5W C 10 4. 7nF 1nF R s = max 5 ohm @100kHz 630V On Air C 11 R 14 10E R 17 22E 1W
R1 750K 1% TR AN SF OR MER R6 68K
R4 180K
R2 750K 1%
R5 180K
C5 100n C4 1000n 12K I C _GN D PB2 R8
C1 100nF 5 2 U1 C3 330n INV R 15 10K ZCD
+4
J1 VC C GD GN D CS U1 L6562 C OM P 8 3 MU LT
F U SE 4A/ 250V
BR I D GE W 08G
Line
1
3
3 2 1
N eut ral
Ballast schematic
C ON 3 6 4
High-frequency ballast
15E@25 3A
2-
N TC
R3 10K 1%
C2 10nF
C 20 8. 2nF 1600V
3
1
10
I C _GN D + C 15 330uF 25V R S_1 1E 0. 6W I C _GN D R S_2 1E 0. 6W
R 18 68K C 12 470pF I C _GN D C 13 1000nF 25V I C _GN D I C _GN D
R 20 1K
R 28_1 4. 7K I C _GN D
R 28_2 4. 7K
R 29_1 15K
R 29_2 15K
I C _GN D
T1: Boost Inductor Spec (ITACOIL E2543/E) - E25x13x7 core, 3C85 f errit e - 1.5mm gap f or 0.7mH primary inductance - Primary : 105 turns (20 x 0.1mm) - Secondary : 11 turns (0.1mm) D 14 STTH 1L06 600V 1A PW M0 R low 4. 7K + Cf 4. 7uF 50V I C _GN D J2 U 7 LE50C Z 3 VI N GN D 5VD D VOU T 5VD D C out 2 + + C ON 7 Vs s _STD ALI Vs s _ST7D ALI 1 J4 I C _GN D Viper12A D 13 STTH 1L06 600V 1A 10uF 25V D 12 18V 0.5W C 42 2. 2uF 16V PB2 SI GN 1 EN 1 EN 2 L3 1. 8m H 95m A C 16 10nF 25V R 25 470E D8 1N 4148 C8 100nF DZ2 15V 0.5W + C Vdd 10uF 25V I C _GN D I C _GN D Cf b 22nF 25V S S 1 2 R up 120K Rf 15K R 19 10K
R 24_1 680K D6 BAT46 D 9 BAT46
R 24_2 680K
D 15 Vdd FB 5 6 7 8 D D D D U8 + C in 2 3. 3uF 450V
L4 680uH 240m A 4 3
D 10 BAT46 D 61 BAT46
1N 4007 1A 1000V
I C _GN D
R 100 68K PB1 1% C 73 68pF 50V I C _GN D C 72 33nF 50V I C _GN D
L1&L2: Choke Inductor - E25x13x7 core - 2.62mm gap f or 1.8mH inductance - 267 turns (AWG 40) SI GN
+
C in1 3. 3uF 450V
1 2 3 4 5 6 7
5VD D 5VD D
5VD D
J3 C ON 2 4+ D 16 -3 MB2S DALI Bus 2 5VD D R 60 0 U9 1 1 2 SF H 6156-2 R 65 332R 1% + C 46 22uF 20V R 71 1K21 1% R 72 3K16 1% 1 2 R 66 4R 7 1% 3 Q4 BC 817-25 3 3 4 2 4 11K 1% D 17 BAS16 R 61 1 2 1 2 PW M0 EN 1 EN 2 5VD D PB2 SI GN 5VD D I C _GN D U 10 1 2 SF H 6156-2 PI N 3 SFH6156-2 4 3 4 3
+ C 43 1uF 16V I C _GN D C ON 7 R es et I C _GN D R 62 5VD D 4K7 1% PB1 PB2 EN 1 EN 2 R 67 R 68 0 U 11 I C _GN D C 44 100nF 50V
1 2 3 4 5 6 7
LD 1 R ED H SMS-C 670H E
LD 2 GR EEN H SMG-C 670
R 63 2K49 1%
R 64 2K49 1%
5VD D C 45 100nF 50V I C _GN D PW M0 R es et 10 8 6 4 2 D 18 BZ X284C 2V7 0. 5W R 69 1k 1% I C _GN D 10K 1% PI N 3 SFH6156-2 I C _GN D R 70 1k 1% ST7F D ALI F 2M6 I C _GN D J5 + + + + + + + + + + 9 7 5 3 1 I C P Connector I C _GN D
This section describes the high-frequency ballast board which includes the power factor correction stage, the half-bridge inverter driving circuitry, the output stage and the DALI slave unit. The schematic of the board is shown in Figure 3.
High-frequency ballast
1 2 3 4 5 6 7 8 9 10
VSS OSC 1/ C LKI N VD D OSC 2 R ESET PA0(H S)/ LTI C SS/ AI N 0/ PB0 PA1(H S)/ ATI C SC K/ AI N 1/ PB1 PA2(H S)/ ATPW M0 MI SO/ AI N 2/ PB2 PA3(H S)/ ATPW M1 MOSI / AI N 3/ PB3 PA4(H S)/ ATPW M2 C LKI N / AI N 4/ PB4 A5(H S)/ ATPW M3/ I C C D ATA P AI N 5/ PB5 PA6/ MC 0/ I C C C LK/ BR EAK D ALI I N / AI N 6/ PB6 PA7/ D ALI OU T
20 19 18 17 16 15 14 13 12 11
7/42
High-frequency ballast
AN2708
This block is essentially a "double board" as the DALI slave board and its external circuitry are mounted on a small separated board which is connected to the bottom side by means of a 7-pin connector. Table 2 shows the ballast-slave communication. Table 2.
Pin ref. 1 2 3 4 5 6 7
Ballast-slave communication
Description PWM0 (ref op-amp) Disable L6574 EN1 & disconnected lamp Enable L6574 EN2 & not ignited lamp GND 5 VDD PB2 disable PFC SIGN (lamp failure) Analog stage Microcontroller
Table 3.
Reference Bridge Cout, CVdd C7,Cf Cfb Cin1,Cin2 C1 C2 C3 C4
Ballast bill of material
Value W08G 1.5 A 800 V 10 F 25 V 4.7 F 50 V 22 nF 25 V 3.3 F 450 V 100 nF 400 V 10 nF 50 V 330 nF 50 V 1000 nF 50 V 100 nF 50 V 47 F 450 V 100 nF 100 V 4.7 nF 100 V 1 nF 630 V 470 pF 50 V 1 F 50 V 330 F 25 V 10 nF 25 V 100 nF 250 V 8.2 nF 1600 V 2.2 F16 V Description Bridge rectifier Electrolytic cap Electrolytic cap Ceramic cap Electrolytic cap Polyester cap Ceramic cap Ceramic cap Ceramic cap Ceramic cap Electrolytic cap Ceramic cap Ceramic cap Evox Rifa polypropylene cap Rsmax = 5 at 100 kHz Ceramic cap Ceramic cap Electrolytic cap Ceramic cap Polyester cap Polyester cap Electrolytic cap
C5,C8,C9,C1 9 C6 C14 C10 C11 C12 C13 C15 C16 C17, C21 C18,C20 C42
8/42
AN2708 Table 3.
Reference C43 C44,C45 C46 C72 C73 DZ1,DZ2 D2,D13,D14 D3,D4,D8,D1 1 D5,D6,D7,D9 , D10,D61 D12 D15 D16 D17 D18 FUSE J1 J2 J3 J4 J5 J13 J14 Lamp 1 Lamp 2 LD1 LD2 L1,L2 L3 L4 NTC Q1,Q2,Q3 Lamp connector Lamp connector LS M67K-H2L1-1 LG M67K-G1J2-24 1.8 mH 1.8 mH 95 mA 680 H 240 mA 15 at 25 C 3 A STP8NM50 TO220
High-frequency ballast Ballast bill of material (continued)
Value 1 F 20 V 100 nF 50 V 22 F 20 V 33 nF 50 V 68 pF 50 V 15 V 0.5 W STTH1L06 1N4148 BAT46 DO 35 18 V 0.5 W 1N4007 1 A 1000 V MB2S 0.5 A 200 V BAS16 BZX284C 2V7 4 A 250 V Input 250 V connector Ballast-slave connector Description SMD tantalum cap 0805 SMD cap SMD tantalum cap 0805 SMD cap 0805 SMD cap Zener diode STMicroelectronics ultrafast high voltage rectifier 1 A 600 V Small signal rectifier 200 mA 100 V STMicroelectronics small signal Schottky diode Zener diode General purpose rectifier SMD bridge rectifier Small signal diode 0.5 W Zener diode Radial fuse 3-way PCB screw terminal, 5.08 mm 7-way strip line socket 2-way vertical PCB header, 3.81 mm pitch 7-way strip line connector 10-way 2-row vertical through-hole boxed header 4-way strip line socket 4-way strip line connector 4-way PCB screw terminal, 5.08 mm 4-way PCB screw terminal, 5.08 mm 2 mA red LED SMD 0805 2 mA green LED SMD 0805 Choke inductor 2.62 mm gap, 267 turns (AWG40); E25x13x7 Epcos BC series Axial inductor Epcos LBC series Axial inductor Inrush current suppressor STMicroelectronics N-CHANNEL 550 V 0.7 - 8 A MDmesh MOSFET
Dali Bus Ballast-slave connector ICP connector
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High-frequency ballast Table 3.
Reference Q4 RS_1,RS_2 RS1,RS2 R29_1, R29_2,Rf R28_1, R28_2,Rlow R12,Rup R1,R2,R9, R10, R26_1, R26_2, R27_1, R27_2 R15,R19 R3 R4,R5, R26_2A R6,R16,R18 R7 R8 R11 R13 R14,R21,R22 R17 R20 R23 R25 R60,R68 R61 R62 R63,R64 R65 R66 R67 R69,R70 R71 R72
AN2708 Ballast bill of material (continued)
Value BC817-25 1 0.82 15 k 4.7 k 120 k Description NPN small signal bipolar 0.6 W 1% metal film resistor 1 W resistor Resistor Resistor Resistor
750 k
0.6 W 1% resistor
10 k 10 k 180 k 68 k 33 12 k 9.53 k 47 k 10 22 1 k 330 470 0 11 k 4.7 k 1 k 330 4.7 10 k 1 k 1.2 k 3 k
Resistor 0.6 W 1% resistor Resistor Resistor Resistor Resistor 1% Resistor Resistor Resistor 1 W resistor Resistor Resistor Resistor SMD resistor 0805 1% SMD resistor 0805 1% SMD resistor 0805 1% SMD resistor 0805 1% SMD resistor 0805 1% SMD resistor 0805 1% SMD resistor 0805 1% SMD resistor 0805 1% SMD resistor 0805 1% SMD resistor 0805
10/42
AN2708 Table 3.
Reference R100 R24_1,R24_ 2 R30_1,R30_ 2 T1 U1 U2 U7 U8 U9,U10 U11
High-frequency ballast Ballast bill of material (continued)
Value 68 k 680 k 100 k Transformer L6562N L6574 LE50CZ TO-92 VIPer12A-E DIP8 SFH6156-2 ST7FDALIF2M6 SO20 Description 1% SMD resistor 0805 Resistor 2 W resistor Choke boost inductor (ITACOIL E2543/E) STMicroelectronics transition-mode PFC controller STMicroelectronics ballast driver STMicroelectronics very low drop voltage regulators STMicroelectronics offline SMPS primary IC 730 V 0.4 A 27R Optocoupler STMicroelectronics 8-bit MCU with single voltage Flash memory, data EEPROM, ADC, timers, SPI, DALI
Note:
Resistors are 0.25 W unless specified. Q1, Q2 &Q3 are mounted with 8 C/W heatsink.
2.1
PFC converter
This block allows drawing a quasi-sinusoidal current from the mains, in phase with the line voltage in order to get a PF very close to 1 (more than 0.99). To achieve such high PF the boost topology is implemented because of the advantages it offers:
Minimum number of external components, thus making it a low-cost solution Low input di/dt thus minimizing the noise generated at the input and, therefore, the requirements on the input EMI filter The switch is source-grounded, therefore is easy to drive
However, boost topology requires the DC output voltage (400 Vdc) to be higher than the maximum expected line peak voltage. ST's L6562 has been used as the driver. It implements a transition mode control (fixed ON time, variable frequency), that, for such output power, is preferred to the fixed frequency average current mode being simpler and cheaper. The circuit operates on the boundary between continuous and discontinuous current mode. Besides providing good results in terms of power factor, this IC considerably reduces the Total Harmonic Distortion (THD) as it reduces the conduction dead-angle that occurs to the AC input current near the zero-crossings of the line voltage.
11/42
High-frequency ballast The basic design specifications are listed in Table 4. Table 4. PFC operating conditions
Parameter Mains voltage range: Virms(min) - Virms(max) Regulated DC output voltage: Vo Rated output power: Po Minimum switching frequency: fsw Maximum output voltage ripple: Vo Maximum overvoltage admitted: VOVP Expected efficiency: FC P Value 90 265 Vac 400 Vdc 75 W 35 kHz < 10 V 60 V > 90 V
AN2708
For reference, it is useful to define also the following quantities:
Input power: Pi (= Po / ) 80 W Maximum mains RMS current: Iirms (= Pi/Virms(min)) 1 A Rated output current: Io (= Po/Vo) 0.2 A
The design guidelines are deeply explained in AN966 ("L6561, enhanced transition mode power factor corrector"), AN1757 ("Switching from the L6561 to the L6562) and AN1089 ("control loop model of L6561-based TM PFC"). The main design formulas are summarized as follows inTable 5. Table 5. Power stage design equations
Boost inductor
2 Volume 4K L I irms
Input capacitor (C1)
C 1 = ------------------------------I---------s-----------------------------r m -2 fsw r Vinrmsmin
Power MOSFET (Q1)
Boost diode (D1)
BV
DSS
= Vo + V
OVP
+ V m arg i n
where
r = 0.01 ÷ 0.1 2 V irms (Vo 2 Virms) L = ----------------------------------------------------------------------------2 f Pi Vo sw 2 Pon = I Qrms R DS (on) V RRM = 1.2 V o
Output capacitor (C6)
where
K 14 10 3 Ie -----------Igap
where
I = 2 2 Iirms 2 --- i r m s 1 4------- V-------------- --Vo 6 9 I F = 3 Io
Qrms
Po C 6 ------------------------------------------------4 f Vo Vo
2 4 P c u = -- I i r m s R c u 3
Pcross = Vo Iirms t
fall
f
sw
P
losses
2 =V I + Rd I rms T DC
1.5 2 1 P c a p = 3.3 C o s s V d r a i n + -- C d V d r a i n f sw 2
12/42
AN2708
High-frequency ballast
Table 6.
L6562 biasing circuitry design equations
Pin 2 (COMP) A RC-C network is placed between this pin and pin 1, leading to a low crossover frequency (some tens of hertz) as well as to an adequate phase margin. Pin 6 (GND) IC ground. As a layout hint, this pin has to be kept separated from power ground. All the IC signals have to be referred to this pin. Pin 3 MULT Pin 4 (CS)
Pin 1 (INV)
OVP = R
high
40 10
6
V MULTpkx 2.5 R l o w = ------------------------------- = ----------------------------6 6 250 10 250 10
V inrmsmin 1.65 2.5 -------------------------------- V i n r m s m a x R -----------------------------------------------------------------------sense 2 2 Ii n r m s
V
(R +R ) high low = 2.5 -----------------------------------------out R low
R low ------------------------------------- = --------------------2--5---------------------.--R +R 2 V low high inrmsmax
A small capacitor of 10 nF filters the signal on MULT pin. Pin 7 (GD) Gate driver. A "bleeder" resistor between the gate and the source is used to avoid undesired switch-on, without affecting the power consumption.
2 Pd = Rs I Qrms
Pin 5 (ZCD)
Pin 8 Vcc The supply voltage is provided by a capacitive power supply connected to the half-bridge inverter.
V 2 i n - m -- m i n = ----------r-------s------------------------I startup
( V o u t 2 Vi n r m s m a x ) m = -----------------------------------------------------------------------2.1 1.15
(Vout 2 V ) inrmsmin R 6 ---------------------------------------------------------------------3 m 3 10
R
start
The PFC preregulator performances are shown in the following graphs: Figure 4. PFC performances at 230 Vac-50 Hz
CH1 (yellow): rectified input voltage CH2 (blue): input current
13/42
High-frequency ballast
AN2708
2.2
Half-bridge inverter and ballast
A voltage fed series resonant half-bridge inverter has been implemented to drive the tubes. This topology allows to easily operates in zero-voltage switching (ZVS) resonant mode, heavily reducing the transistor switching losses and the electromagnetic interference. In addition it guarantees design simplicity and low cost. A parallel configuration has been chosen for the output stage. The half-bridge inverter operating conditions and the ballast design have been obtained by assuming, for each lamp, the following basic model: Figure 5. Lamp ballast model
To increase the life time of the lamps a current mode preheat was preferred. The preheating current brings the cathodes to the correct temperature, then a high voltage ignites the lamp and finally the correct current guarantees the running power. These phases are ensured by changing the frequency of the input voltage and properly selecting VIN, L and C. During preheating and ignition, the lamp is not conducting and the circuit is reduced to a series L-C. During running, the lamp is conducting and the circuit is an L in series with a parallel R-C. To determine the optimum values for L and C and to calculate the ballast operating frequencies the transfer functions for each mode of operation have to be inspected. The table below shows the parameters and the values for a T8 36 W tube lamp which need to be known in order to calculate the ballast operating conditions. Table 7. Lamp parameters
Parameter Input DC bus voltage: Vdc Preheat current: Iph Preheat time: Tph Max preheat voltage: Vphmax Ignition voltage: Vign Running lamp power: Prun Running lamp voltage: Vrun Expected efficiency: Value 400 V 0.6 A 1 sec 300 Vpk 800 Vpk 34 W 144 Vpk 95%
14/42
AN2708
High-frequency ballast Once the lamp and its parameters have been chosen, the ballast design will be optimized by selecting the resonant components L and C as follows:
Set Tpre Select frunmin (> 20 kHz) Choose f = fmax-frunmin Select L & C such that fph > frun Select half-bridge switches Select L6574 biasing circuitry
The magnitude of the transfer function (lamp voltage divided by input voltage) for the two circuit configurations (preheating-ignition and running) illustrates the operating frequencies and where they lie with respect to one another. Figure 6. Ballast transfer functions (magnitude)
The currents and voltages corresponding to the resulting operating frequencies determine the maximum current and voltage ratings for the inductor, capacitor, and the switches, which, in turn, directly determine the size and cost of the ballast. Moreover the zero-voltage switching is ensured as shown by the curves above in Figure 6. STP8NM50 (8 A, 550 V) has been selected as power switch according to the current stress and the input DC voltage. The half-bridge inverter driving circuitry is based on the high performance L6574 which is an OFF-LINE half-bridge driver designed in 600 V BCD technology, including all the features needed to drive and properly control the tubes. A dedicated timing section in the L6574 allows setting the necessary parameters for proper preheat and ignition of the lamps. Also, an op-amp is available to implement closed-loop control of the lamp current during normal lamp burning. To avoid cross conduction of the power MOSFETs the internal logic ensures a minimum deadtime. Moreover the L6574 is provided with two lamp status control functions to protect the application against lamp failure as well as lamp disconnection. Finally it is
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High-frequency ballast
AN2708
possible to modulate the output power in order to allow dimming by varying the switching frequency. The ballast operating frequencies determine the L6574 biasing circuitry as explained in AN993 "Electronic Ballast With PFC Using L6574 and L6561" and as summarized below. Table 8. L6574 biasing circuitry design equations for operating conditions
Pin 2 (RPRE) Pin 3 (CF) Pin 4 (RIGN) Pin 5 (OPOUT) A capacitor is connected between this pin and OPINfor the current feedback loop compensation. It set also the turn on delay in a dimming application.
Pin 1 (CPRE)
T
ph
= 1.5 C
PRE 1-4--- f p h f r u n = ----------.----1----R Cf PRE 1.41 f r u n = ------------------RignCf 1.4-- f r u n = -------------1---RignCf
K PRE T s h = ---------------- C P R E 10
2.2.1
Lamp dimming
In this system the lamps are dimmed down to 5% by interfacing the ST7FDALI microcontroller with the analog driver L6574. A PWM output of the ST7FDALI microcontroller is used to generate a 0-5 V PWM at 4 kHz. Its integrated value gives the op amp voltage reference. The dimming level is set by varying the PWM duty cycle from 70% (100% dimming) to 14% (5% dimming). This modification allows changing the L6574 op-amp positive reference voltage from 120 mV to 20 mV which increases the switching frequency and reduces the current in the load. On the slave unit the duty cycle values have been calculated according the DALI protocol brightness values, listed in Figure 7.
16/42
AN2708 Figure 7. DALI protocol brightness values
High-frequency ballast
To avoid the presence of stationary waves along the tubes at minimum dimming level, a resistor of 100 k / 2 W has been placed in parallel to the battery capacitor of each lamp. The resistance value ensures an additional current of 2 mA on the cathodes without affecting the ballast efficiency. Finally, during the startup sequence the frequency always goes from fmax to fmin, independently of the set dimming level. Only after lamp turn-on does the frequency move towards higher values.
2.2.2
Supply section
To supply the DALI slave microcontroller an AC-DC buck converter based on the VIPer12A-E and L78L05 has been implemented on the ballast board. It converts the rectified and filtered mains to a 5 V regulated output voltage dedicated to the microcontroller. The converter works in discontinuous current mode adjusting the duty cycle
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High-frequency ballast
AN2708
of the VIPer12A-E power switch in order to deliver the energy from the input to the output by means of an inductor. PWM driver, power switch, thermal and overcurrent protection are integrated in the same silicon chip ensuring minimum size and good performances at very low cost. Thanks to this implementation strategy the microcontroller is always supplied, allowing the lamps to turn on, even when L6562 and L6574 are in a latched shutdown state. The startup procedure is very important in an application that contains two different sections. The ballast section starts before the PFC, avoiding any extra voltage at the PFC section output, and consequently the L6562 OVP activation. This behavior is guaranteed under all conditions because the VS turn-on threshold of L6574 is lower than that of the L6562. The turn-on threshold is reached by a resistor chosen in order to ensure the startup current of both the L6562 and the L6574. When the ballast section is running, the charge pump (C11, R14, D3 and DZ1) supplies both the devices and the filter R17-C10 allows to reduce the noise at Vcc.
2.2.3
Lamp turn-on and lamp turn-off
To get low-power consumption (less than 0.6 W) during the lamps' turnoff state, both the half-bridge and the PFC have to be disabled, even in the presence of the mains at the ballast input. To manage this standby condition the L6574 control section and the L6562 ZCD pin are interfaced with the DALI slave microcontroller. Shor t pulses (> 200 nsec) at the EN1 and EN2 inputs are recognized by the L6574. In particular, EN1 high (> 0.6 V) stops all the half-bridge functions and puts the L6574 in a latched shutdown state. At the same time, by forcing externally the ZCD pin to a voltage below 150 mV, the L6562 is stopped. To cancel this status, in order to turn on the lamps, a pulse (>0.6 V) is sent by the microcontroller to the L6574 second control pin EN2 and the ZCD pin external pull down is removed. The half-bridge driver restarts the preheating and ignition procedure, and the L6562 performs again its operation. The controls timing diagram is shown in Figure 8.
18/42
AN2708 Figure 8. Ballast controls timing chart
High-frequency ballast
Vsupply
LVG
HVG Latched Disable
EN1 Forced Restart EN2
ZCD
GD
TIME
On the slave unit the turning ON/OFF process is implemented by setting the pins PB3 (EN1) and PB4 (EN2) as output pull-up, while PB2 (ZCD) as output open drain. The three corresponding bits in the port data register are clear by software. To "switch on" the ballast, a pulse must be sent to PB4 (EN2 signal) and the third bit must be set in the port B (ZCD) data register. To "switch off" the ballast, a pulse must be sent to PB3 (EN1 signal) and the third bit must be cleared in the port B (ZCD signal) data register. Figure 9, 10, and 11 show the idle state and the turn-on/off commands.
19/42
High-frequency ballast Figure 9. Idle state
AN2708
CH3 (blue): EN1 low level CH4 (green): EN2 low level Figure 10. Turn-on procedure
CH3 (blue): EN1 low level CH4 (green): EN2 pulse Figure 11. Turn-off procedure
CH3 (blue): EN1 pulse CH4 (green): EN2 low level
20/42
AN2708
High-frequency ballast
2.2.4
Verification of lamp status
This function detects a lamp disconnection or a lamp failure on the slave board. The microcontroller performs a double check: one on the PB1 pin for the lamp hardware status and one on the flag "LAMP_ARC_POWER_ON" for the lamp software status. If the PB1 logical level is low and the flag is true, lamp disconnection happened. The condition is recorded on ST7FDALI, so when the microcontroller receives a "query frame" from the master, it changes the PB3 (EN1) and PB4 (EN2) configuration from input to output, and sends a byte answer as 'STATUS INFORMATION' described below:
bit 0 status of ballast; '1'= NOK bit 1 Lamp failure; '1'= NOK bit 2 Lamp arc power on; '0' = OFF bit 3 Query: Limit Error; '0' = Last requested arc power level is between MIN..MAX LEVEL or OFF bit 4 Fade ready; '0' = fade is ready; '1' = fade is running bit 5 Query: 'RESET STATE'? '0' = 'No' bit 6 Query: Missing short address? '0' = 'No' bit 7 Query: 'POWER FAILURE'? '0' = 'No'; 'RESET' or an arc power control command has been received after last power-on
When the master receives this frame, it displays the lamp status by means of two LEDs (green stands for ok, red for status not ok). Once the failure condition has been detected and solved, an "ON" command has to be sent to the slave, allowing the master's microcontroller to toggle again the LED status from red to green. From the analog side, to detect a disconnection or a failure event for each lamp, two signal Schottky diodes have been used to bias the EN1 or EN2 pin of L6574. The failure condition is detected both at startup and when running. The forward and backward frame timing is shown in Figure 12 and 13: Figure 12. Forward frame timing
21/42
High-frequency ballast Figure 13. Backward frame timing
AN2708
The forward as well as the backward frame duration is the same for all kinds of commands.
2.2.5
Ballast performances
In this section the main ballast waveforms are shown.
Figure 14. Ballast startup at 230 Vac-full power
Figure 15. Lamps turn-on at 230 Vac-full power
CH2 (blue): lamp current CH3 (magenta): VCPRE CH4 (green): supply voltage
CH1 (yellow): lamp1 voltage CH2 (blue): lamp1 current CH3 (magenta): lamp2 voltage CH4 (green): lamp2 current
22/42
AN2708 Figure 16. Lamps running at 230 Vac - full power
High-frequency ballast
CH1 (yellow): lamp1 voltage CH2 (blue): lamp1 current Ch3 (magenta): lamp2 voltage CH4 (green): lamp2 current
Table 9.
Vin (Vac) 90 110 140 176 230 265
Ballast performances
Pin (W) 76.5 75.5 74.2 73.7 73 72.8 PF 0.999 0.999 0.998 0.997 0.997 0.996 THD (%) 3.9 3.6 5.5 7.2 7.3 8.3 Po (W) 66 66 66 66 66 66 (%) 86.2 87.4 89 90 90 91
The efficiency of the system is a little bit lower than a standard HF ballast due to the supply section of the slave and the resistors in series to the lamp's cathode used to ensure a minimum current at low dimming level.
23/42
DALI master unit
AN2708
3
DALI master unit
The ST2C334J4 microcontroller is used as master, implementing the DALI Peripheral via software. The communication master-slave uses a 20 V bus. To adapt the TTL level of the microcontroller to the communication bus level, two opto-couplers and a NPN transistor BC817 have been used. The RS232 interface with ST232C is available on the board to implement the SCI communication as an option. This option expects the use of a PC to address the ballast either with broadcast or group or single mode thanks to a GUI called (DALI Power Control). The DALI master unit has been thought of as a standalone solution. In fact it is provided with a keyboard to manage the DALI commands, to address the slaves and to display the lamps' status. The keyboard is made up of 16 push buttons controlled by means of a matrix representation. In particular the first four pins of PORTD are associated to the rows and the first four pins of PORTB to the columns. The check of the keyboard is implemented as a loop mode by clearing the PDDR register port and setting the PBDR register port sequentially. When a button is pressed, the pin of the port B corresponding to the interested column goes down and this condition is taken over by an interrupt condition. Inside the interrupt routine, a read procedure of the port registers PDDR and PBDR is expected and by this information the pressed button is acknowledged. The "press button" procedure is described by Figure 17 and 18. Figure 17. Polling keyboard
CH1 (yellow): row polling CH2 (purple): column level
24/42
AN2708 Figure 18. Pressed button event
DALI master unit
CH1 (yellow): row polling CH2 (purple): column level
25/42
3.1
Supply Voltage 4+ 3 PE0/ TD 0 PE1/ R D 1 SW 1 32 31 C 54 5VD D PA3 R 80 1K R 81 1K 100nF 50V R 82 4. 7K R es et R ESET I SPSEL 37 38 R 76 10K 1% D 20 MB2S PF 2 TR AN SM. R S232
1
TR AN SM. 5VD D D 21 1 1 2 SF H 6156-2 Y1 2 16MH z D 22 BZ 84C 2V7 1 3 J8 10 8 6 4 2 + + + + + + + + + + 9 7 5 3 1 I C P Connector ST72C 334J 4B6 3 3 OSC 1 OSC 2 35 34 4 BAS16 2 R 84 4R 7 1% 4 R 79 11K 1% U 15 PA7(H S) PA6(H S) PA5(H S) PA4(H S) PA3
R 77 0
2
The schematic of the master unit is shown in Figure 19.
AI N 4 AI N 5 Query status D 26 LG M67K-G1J2-24 Green R ows D 28 LG M67K-G1J2-24 Green SW 18 R 91 1K C olum ns D 27 LG M67K-G1J2-24 Green R 90 1K Port a PD 0 R ow1 Port a PD 1 R ow2 Port a PD 2 R ow3 Port a PD 3 R ow4
5VD D
Query status
1 2 3
26/42
5VD D 5VD D 5VD D 5VD D C 49 220nF 50V C 50 100nF 50V U 12 P1 C 48 100nF 50V R 74 220R 5% 1W R 75 10K 1% 10 11 12 13 14 15 MC O/ PF 0 BEEP/ PF 1 PF 2 OC MP1_A/ PF 4 I C AP1_A/ (H S)/ PF 6 EXTC LK_A/ (H S)/ PF 7 PB0 PB1 PB2 PB3 PB4 C ol4 C ol3 C ol2 C ol1 PB4 16 17 18 19 20 21 22 23 OC MP2_B/ PC 0 OC MP1_B/ PC 1 I C AP2_B/ (H S)/ PC 2 I C AP1_B/ (H S)/ PC 3 I SPD ATA/ MI SO/ PC 4 MOSI / PC 5 SC K/ I SPC LK/ PC 6 SS' / PC 7 30 29 28 27 24 39 40 41 42 1 R ow1 R ow2 R ow3 R ow4 AI N 4 AI N 5 AI N 0/ PD 0 AI N 1/ PD 1 AI N 2/ PD 2 AI N 3/ PD 3 AI N 4/ PD 4 AI N 5/ PD 5 VD D _1 VD D _2 VD D A VSS_1 VSS_2 VSSA 2 3 4 5 6 7 1 6 2 7 3 8 4 9 5 25 36 8 26 33 9 C 47 100nF U 13 1 C 51 50V VD D 2 C 1+ 100nF GN D 50V 3 V+ T1OU T 4 C 1R 1I N 5 C 2+ R 1OU T 6 C 2T1I N 7 V8 T2OU T T2I N R 2I N R 2OU T C 52 C 53 ST232C 100nF 100nF 50V 50V 16 15 14 13 12 11 10 9
DALI master unit
J6
1 2
D ALI Bus
J7
VD
3 2 1
5VD D
R 73 0 5%
D 19 BZ X85C 22
U 14
R 78 1K2 1%
1
1
4
4
2
2
3
3
Figure 19. Master unit schematic
SF H 6156-2
5VD D 5VD D
J9
R 83 330R 1% Q5 BC 817-25 LD 3 LS M67K-H2L1-1 R ed LD 4 LG M67K-G1J2-24 Green
+
13 12 11 10 9 8 7 6 5 4 3 2 1 R 85 3K 1% Slave address
PA3 C ol4 C ol3 C ol2 C ol1 PF 2 AI N 5 AI N 4 R ow4 R ow3 R ow2 R ow1 PB4
C 55 22uF 25V
J 18 Pull-U p Jumper
5VD D
Master unit schematic and bill of material
PB4 D 23 LS M67K-H2L1-1 R ed R 89 1K R ow4 R ow3 R ow2 R ow1 C ol4 C ol3 C ol2 C ol1 SW 22
Port a PB0 C olom n4
SW 19
SW 20
SW 21
R 86 1K
PA3 D 24 LG M67K-G1J2-24 Green D 25 LS M67K-H2L1-1 R ed R 87 R 88 1K 1K
Port a PB1 C olom n3
SW 24
SW 25
SW 23
SW 26
Port a PB2 C olom n2
SW 30
SW 28
SW 27
SW 29
SW 31
SW 32
SW 33 R 102 10k
AN2708
Port a PB3 C olom n1
AN2708
DALI master unit
Table 10.
Master unit bill of material
Value 100 nF 50 V 220 nF 50 V 22 F 25 V BZX85C22 MB2S BAS16 BZ84C 2V7 LS M67K-H2L1-1 LG M67K-G1J2-24 DALI BUS Supply voltage ICP connector Description Ceramic capacitor SMD 0805 Ceramic capacitor SMD 0805 Tantalum capacitor SMD 22 V 0.5 W Zener diode SMD bridge rectifier SMD diode 2.7 V 0.5 W Zener SMD diode Red SMD LED 2 mA, 0805 Green SMD LED 2 mA, 0805 2-way single row, header shrouded 3-way single row header shrouded 10-way 2-row vertical through-hole boxed header, 2.54 mm pitch/grid 13-way strip line connector (not mounted) Pull-up jumper LS M67K-H2L1-1 LG M67K-G1J2-24 Serial connector BC817-25 0 0 220 10 k 1.2 k 11 k 1 k 4.7 k 330 4.7 3 k 1 k 10 k Reset 3-way strip line connector Red SMD LED 2 mA, 0805 Green SMD LED 2 mA, 0805 9-way 90 PCB mount D plug SMD NPN transistor Resistor SMD 1206 Resistor SMD 0805 1 W 5% resistor 1% resistor SMD 0805 1% resistor SMD 0805 1% resistor SMD 0805 Resistor SMD 0805 Resistor SMD 0805 1% Resistor SMD 0805 1% Resistor SMD 0805 1% Resistor SMD 0805 Resistor SMD 0805 Resistor SMD 0805 THT button
Reference C47,C48,C50,C51,C52, C53,C54 C49 C55 D19 D20 D21 D22 D23,D25 D24,D26,D27,D28 J6 J7 J8 J9 J12 LD3 LD4 P1 Q5 R73 R77 R74 R75,R76 R78 R79 R80,R81 R82 R83 R84 R85 R86,R87,R88,R89,R90, R91 R101 SW1
27/42
DALI master unit Table 10. Master unit bill of material (continued)
Value Description
AN2708
Reference SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW12, SW13, SW14, SW15, SW16, SW17 U12
Keyboard
THT button
ST72C334J4B6 PSDIP42 ST232C SOP SFH6156-2 16 MHz
STMicroelectronics 8-bit MCU with single voltage flash memory, Adc, 16-bit timers, SPI, SCI interface STMicroelectronics 5 V powered multi-channel RS-232 drivers and receivers SMD Opto-coupler Oscillator
U13 U14,U15 Y1
Note:
Resistors are 0.25 W unless specified
28/42
AN2708
Basics of DALI
4
Basics of DALI
DALI stands for "Digital Addressable Lighting Interface". It is a standard interface for lighting control solutions, defined by the main lighting manufacturers and standardized as IEC 929. The DALI protocol is implemented on a master-slave architecture. It uses the bi-phase Manchester asynchronous serial data format. All the bits of the frame are bi-phase encoded except the two stop bits. Following are some of the standard features:
Transmission rate at 1.2 kHz. Bi-phase bit period is 833.33 S 10%. 1 start bit (0->1: logical '1') 1 address byte (8-bit address) 1 data byte (8-bit data) 2 high level stop bits (no change of phase) 1 start bit (0->1: logical '1') 1 data byte (8-bit data) 2 high level stop bits (no change of phase)
A forward frame consists of 19 bi-phase encoded bits:
A backward frame consists of 11 bi-phase encoded bits:
Each frame has 2 stop bits which do not contain any change of phase. The setting time between two subsequent forward frames is 9.17 ms (minimum), while the delay between forward and backward frame goes from 2.92 ms to 9.17 ms. If a backward frame has not been started after 9.17 ms, this is interpreted as "no answer". In the event of code violation, the frame is ignored and the system is ready again for data reception. The main advantages of the DALI system can be summarized as follows:
Simple wiring: all of the units in the system are interconnected using a simple five-core cable.
Figure 20. Cable wiring
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Basics of DALI
AN2708
No mains switching required: lamps can be dimmed or switched on and off using control system commands without any need for mains switching. Easy system re-configuration: the configuration of the system can be changed quickly without any modification to the hardware. Easy system modification: if the lighting system needs to be enlarged, new components can be added anywhere on the DALI cable. It is possible to define light scenes. A scene means a particular light level intensity. 16 scenes can be defined at maximum.
Figure 21. Master flowchart
START
POLLING KEYBOARD
PUSH BUTTON Y
N
BUTTON NUMBER 11 N SEND COMMAND
Y
CHANGE SLAVE ADDRESS
QUERY FRAME
Y
WAIT BACKWARD FRAME
N NO ANSWER N FRAME RECEIVED
Y TOGGLE LED
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AN2708 Figure 22. Slave flowchart
Start
Basics of DALI
Main
Failure=1
Y
Pin PB1=low level
N
New Frame Received
Dali Peripheral
Process Command
PWM routine
Pulse on EN1(OFF) or EN2 (ON) change pin configuration
Y
ON/ OFF
N Y
Other indirect arc power control commands
N N
Query command
Y
Send Lamp OK
N
Failure=1
Y
Change configuration of PB3,PB4 pin
Send Lamp Failure
31/42
DALI master AC-DC adapter
A N2708
5
DALI master AC-DC adapter
This is an offline wide-range double-output SMPS based on the VIPer12A-E. The first output, 20 V at 100 mA, is dedicated to the bus communication allowing to address up to 64 slaves, while the second one delivers 5 V at 10 mA to the MASTER DALI microcontroller thanks to a linear post-regulator. The VIPer12A-E combines on the same silicon chip a dedicated current mode PWM controller, a high voltage power MOSFET and the protection features (thermal, overcurrent, and overvoltage) which increases the converter reliability and saves size, parts count and cost. The converter topology is an isolated flyback designed to work in discontinuous current mode according to the following specifications: Table 11. SMPS operating conditions
Parameter Input voltage range Input frequency range Output voltage 1 Output voltage 2 Output current 1 Output current 2 Output power (peak) Line regulation Load regulation EMI Value 90 265 Vac 50/60 Hz V1=20 V V2=5 V I1=100 mA I2=10 mA 2.2 W +/- 1% +/- 1% EN55015
5.1
Adapter description
The schematic of the board is shown in Figure 23. The AC input is rectified by the diodes bridge and then filtered by the bulk capacitor C1, and C2 to generate the high voltage DC. The input EMI filter is a simple CLC PI filter for both differential and common mode noise suppression. An NTC limits the inrush current and ensures a reliable operation of the bridge at startup. The switching frequency is fixed at 60 kHz by the IC internal oscillator allowing optimization of the transformer size and cost. An RCD snubber circuit (R92, C59, D30) reduces the leakage inductance voltage spike and the voltage ringing on the drain pin of VIPer12A-E. As soon as the voltage is applied on the input of the converter the high voltage startup current source connected to the drain pin is activated and starts to charge the Vdd capacitor C8 by a constant current of 1mA. When the voltage across this capacitor reaches the Vddon threshold (about 14 V) the VIPer12AS-E starts to switch. During normal operation the smart
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DALI master AC-DC adapter power IC is powered by the auxiliary winding of the transformer via the diode D31. No spike killer for the auxiliary voltage fluctuations is needed thanks to the wide range of the Vdd pin (9-38 V). The primary current is measured using the integrated current sensing for current mode operation. The output rectifier D29 has been chosen in accordance with the maximum reverse voltage and power dissipation. In particular a 1 A - 150 V power Schottky, type STPS1150, has been selected. The output voltage regulation is performed by secondary feedback on the 20 V output while the 5 V output, is linearly post-regulated from the 20 V output. This operation is performed by a low drop voltage regulator, L78L05CZ, in the TO92 package. The feedback network consists of a programmable voltage reference, TL431, driving an optocoupler which ensures the required insulation between the primary and secondary sections. The optotransistor drives directly the VIPer12A-E feedback pin which controls the operation of the IC. A small LC filter has been added on the 20 V output in order to reduce the high frequency ripple with reasonable output capacitor value. The flyback transformer is a layer type based on the EF13 core and Fi 324 ferrite, manufactured by Vogt, and ensures safety insulation in accordance with the EN60950. Figure 26 shows the main features of the transformer. The power supply has been implemented on a double-sided 35 m PCB in FR-4, sizing 81 x 37 mm. Figure 23. Adapter schematic
L9 1m H 130mA N TC 2 10R @ 25 J 17 2 1 2I nput 250V Con +4 BR I D GE2 D F 06 1 R 92 56K D 29 STPS1150 9 + C 59 150uF 35V + C 60 22uF 35V U 16 L78L05C Z F U SE2 0. 5A R 93 560R 2. 2nF Y 1 T1: SMT - EF12.6/3.7core, Fi324 f errit e - 0.16mm gap f or 2mH primary inductance - Primary : 135 turns (0.14mm-AWG35) - Secondary : 28 turns (0.36mm-AWG27) - Auxiliary : 21 turns (0.05mm-AWG44) R 94 10R 5 SL 060 918 11 01 D 31 1N 4148 R 97 10K 3 2 U 18 4 C 63 10uF 50V Vdd D D D D + 5 6 7 8 U 17 PC 817 4 1 R 95 1K R 96 33K GN D C 61 3 4 VI N VOU T J 10 5V@10mA 1 + C 62 2. 2uF Supply Voltage 1 2 3 L8 100uH 600mA
3
+ C 56 2. 2uF 400V
+ C 57 2. 2uF 400V
C 58 470pF 1 1k V 2
T3
20V@100mA
D 30 STTH 1L06
6
VI Per12A FB S S
R 98 150K
C 64 100nF 50V 3 R 99 4. 7K
3
2 1
10nF 50V
C 65
2
1
U 19 TL431
2
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Figure 24. Adapter PCB layout - top side silkscreen (to scale)
Figure 25. Adapter PCB layout - bottom side copper tracks (to scale)
Figure 26. Flyback transformer
Operating switching frequency: 60 kHz Core geometry: EF 12.6/3.7 Core material: FI 324 or equivalent Primary inductance value: 2 mH Leakage inductance: 75 H Air gap length: 0.16 mm Safety: EN60950
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5.2
Table 12.
Adapter bill of material
Adapter bill of material
Value DF06M 1 A 600 V Description Bridge rectifier Electrolytic cap Ceramic cap Low ESR electrolytic cap Low ESR electrolytic cap Y1 ceramic cap Electrolytic cap Electrolytic cap Ceramic cap Ceramic cap STMicroelectronics power Schottky rectifier 1 A 150 V STMicroelectronics ultrafast high-voltage rectfifier 1 A 600 V Small signal rectifier 200 mA 100 V Radial fuse 3-way single row shrouded header 2-way PCB screw terminal, 5.08 mm Axial inductor Axial inductor Inrush current suppressor Resistor, metal film 0.25 W Resistor, metal film 0.25W Resistor, metal film 0.25 W Resistor, metal film 0.25 W Resistor, metal film 0.25 W Resistor, metal film 0.25 W Resistor, metal film 0.25 W Resistor, metal film 0.25 W VOGT SMT STMicroelectronics positive voltage regulator Shar p Optocoupler 5 kV STMicroelectronics offline SMPS primary IC 730 V 0.4 A 27 STMicroelectronics programmable voltage reference
Reference BRIDGE2 C56,C57 C58 C59 C60 C61 C62 C63 C64 C65 D29 D30 D31 FUSE2 J10 J11 L8 L9 NTC2 R92 R93 R94 R95 R96 R97 R98 R99 T3 U16 U17 U18 U19
2.2 F 400 V 470 pF 1 kV 150 F 35 V 22 F 35 V
2.2 nF Y1 2.2 F 25 V 10 F 50 V
100 nF 50 V 10 nF 50 V
STPS1150 STTH1L06 1N4148 0.5 A Supply voltage Input 250 V connector 100 H 600 mA 1 mH 130 mA 10 @ 25 56 k 560 10 1 k 33 k 10 k 150 k 4.7 k SL 060 918 11 01 L78L05CZ TO92 PC817 VIPer12A-E DIP8 TL431 TO92
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5.3
Adapter performances
Several tests have been performed on the board to evaluate the converter behavior in terms of efficiency, stability, safe operating area of the devices, line & load regulation and EMI performances.
5.3.1
Steady state tests
These tests have been performed at the input voltage of 110 Vac and 230 Vac at full and minimum load condition.
Figure 27. VIPer12A-E steady state behavior at Figure 28. VIPer12A-E steady state behavior at full load at 110 Vac - 60 Hz full load at 230 Vac - 50 Hz
CH1 (blue): drain voltage CH4 (purple): drain current
CH1 (blue): drain voltage CH4 (purple): drain current
As shown by the waveforms the power supply operates in discontinuous current mode. Figure 29. VIPer12A-E steady state behavior at Figure 30. VIPer12A-E steady state behavior at minimum load at 110 Vac - 60 Hz minimum load at 230 Vac - 50 Hz
CH1 (blue): drain voltage CH4 (purple): drain current
CH1 (blue): drain voltage CH4 (purple): drain current
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DALI master AC-DC adapter At minimum load the VIPer12A-E ensures the burst mode operation, saving the input power consumption.
5.3.2
Startup behavior
Figure 31, 32, 33, and 34 show the typical waveforms during the startup of the power supply. In particular, the full load condition is considered since it represents the heaviest case in terms of voltage and current stress, as well as the minimum load condition for loop stability and voltage stress.
Figure 31. Startup waveforms at full load at 110 Vac - 60 Hz
Figure 32. Startup waveforms at full load at 230 Vac - 50 Hz
CH1 (blue): drain voltage CH2 (red): 5 Vout CH3 (green): 20 Vout CH4 (purple): drain current
CH1 (blue): drain voltage CH2 (red): 5 Vout CH3 (green): 20 Vout CH4 (purple): drain current
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Figure 33. Startup waveforms at minimum load at 110 Vac - 60 Hz
Figure 34. Startup waveforms at minimum load at 230 Vac - 50 Hz
CH1 (blue): drain voltage CH2 (red): 5 Vout CH3 (green): 20 Vout CH4 (purple): drain current
CH1 (blue): drain voltage CH2 (red): 5 Vout CH3 (green): 20 Vout CH4 (purple): drain current
There is no overshoot on the output voltages and the measured wakeup time is 180 mS.
5.3.3
Dynamic load tests
These tests show the transient load response at 110 Vac and 230 Vac mains when the 20 V output current is increased from 10% to 90% of the maximum value.
Figure 35. Dynamic load waveforms at 110 Vac - 60 Hz
Figure 36. Dynamic load waveforms at 230 Vac - 50 Hz
CH3 (green): 20 Vout voltage ripple CH4 (purple): 20 Vout current
CH3 (green): 20 Vout voltage ripple CH4 (purple): 20 Vout current
In the worst case the result is 224 mV or 1.12% of dynamic load regulation which indicates a very good dynamic behavior.
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5.3.4
Line regulation
For this test the output power is kept at the peak value (2.2 W) while the line voltage is slowly increased from 85 Vac to 265 Vac. The board has a line regulation of +0.9%. Figure 37. Line regulation
23 21 19 Output Voltage (Vdc) 17 15 13 11 9 7 5 3 1 70 80 90 100 110 120 140 160 170 180 190 200 210 220 230 240 250 260 270 290 310 Input Voltage (Vac) 20V out 5V out
5.3.5
Load regulation
As the 5 V output is obtained by a linear regulator, the load regulation measurements have been performed only on 20 V output by changing its load from 10 mA to full load 100 mA. The input voltage is kept at the nominal value of 230 Vac. The board has a load regulation of +0.9%. Figure 38. Load regulation
24 23 22
20V Output (Vdc)
21 20 19
20V Output
18 17 16 0 10 20 30 40 50 60 70 80 90 10 0 11 0
Output Current (mA)
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5.3.6
Efficiency variation
For this test the efficiency is measured when the line input is varied from 85 Vac to 264 Vac at full load. The average efficiency is 66.5%. A moderate value is typical of low power applications. Figure 39. Efficiency variations vs. input voltage at full load
80 77.5 75 72.5
Effiiciency (%)
70 67.5 65 62.5 60 57.5 55 52.5 50 70 80 90 100 110 120 140 160 170 180 190 200 210 220 230 240 250 260 270 290 310 Effic ienc y
Input Voltage(Vac)
5.3.7
Conducted emissions test
Conducted emissions have been measured in neutral and line wires, using peak detector and considering the limits for lighting applications i.e. EN55015. The measurements have been performed at 110 Vac and 230 Vac line with fully loaded outputs. The results are shown in Figure 40, 41, 42, and 43. Since the emission level is below both the quasi-peak and average limits with acceptable margin, the power supply passes the pre-compliance test.
Figure 40. Conducted emissions at 110 Vac 60 Hz - full load - line 1 peak detector
01:55:30 Apr 10, 2007 Ref 75 dBV Peak Log 10 dB/ #Atten 10 dB
Figure 41. Conducted emissions at 110 Vac 60 Hz - full load - line 2 peak detector
01:55:07 Apr 10, 2007 Ref 75 dBV Peak Log 10 dB/ #Atten 10 dB
W1 S2 S3 FC AA
W1 S2 S3 FC AA
Start 150 kHz Res BW 9 kHz
VBW 30 kHz
Stop 30 MHz Sweep 881.3 ms (2115 pts)
Start 150 kHz Res BW 9 kHz
VBW 30 kHz
Stop 30 MHz Sweep 881.3 ms (2115 pts)
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References
Figure 42. Conducted emissions at 230 Vac 50 Hz - full load - line 1 peak detector
01:53:40 Apr 10, 2007 Ref 75 dBV Peak Log 10 dB/ #Atten 10 dB
Figure 43. Conducted emissions at 230 Vac 50 Hz - full load - line 2 peak detector
01:54:24 Apr 10, 2007 Ref 75 dBV Peak Log 10 dB/ #Atten 10 dB
W1 S2 S3 FC AA
W1 S2 S3 FC AA
Start 150 kHz Res BW 9 kHz
VBW 30 kHz
Stop 30 MHz Sweep 881.3 ms (2115 pts)
Start 150 kHz Res BW 9 kHz
VBW 30 kHz
Stop 30 MHz Sweep 881.3 ms (2115 pts)
6
References
1. 2. 3. 4. 5. 6. "L6561, enhanced transition mode power factor corrector" (AN966) "Switching from the L6561 to the L6562" (AN1757) "Control loop modelling of L6561-based TM PFC" (AN1089) "Electronic Ballast With Pfc Using L6574 And L6561" (AN993) "Choosing A Dali Implementation Strategy With ST7DALI" (AN1756) "Hardware Implementation for ST7DALI-EVAL" (AN1900)
7
Revision history
Table 13.
Date 07-Mar-2008
Document revision history
Revision 1 Initial release Changes
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