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Time update in ST's TIMEKEEPER® devices

Application Note

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Last Updated: 02/01/2008

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Related Datasheets

5.0 or 3.3 V TIMEKEEPER® supervisor

5.0 or 3.3V, 256 Kbit (32 Kbit x 8) TIMEKEEPER® SRAM

5.0V, 16 Kbit (2Kb X 8) TIMEKEEPER SRAM

5.0V, 64 KBIT (8 KB X 8) TIMEKEEPER® SRAM

5V, 256 Kbit (32 Kb x 8) TIMEKEEPER® SRAM

5V, 64 Kbit (8 Kb X 8) TIMEKEEPER SRAM

64 Kbit (8 Kbit X 8) TIMEKEEPER® SRAM

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AN925 APPLICATION NOTE
Time Update in ST's TIMEKEEPER Devices

Figure 1 shows how the non-volatile, static memory array and the quartz controlled clock oscillator, of TIMEKEEPER devices from STMicroelectronics, are interconnected through the clock registers. The clock registers are mapped into the memory array (please see the data sheet for the precise mapping) as 8 or 16 BYTEWIDE BIPORT memory cells. The time data in these memory cells are updated from the clock side (the system side) and are made available to the user side within the user's finest time resolution. However, the user's finest time resolution is one second, so this leaves plenty of scope for variability (of the order of several milliseconds) between one update and the next. Since this variability might be noticeable to some applications (for example, those that poll the time registers regularly, or those that use an alarm function that is triggered once per second), this document sets out to explain the nature of the variability, to make it more predictable to the applications designer. Figure 1. Internal Architecture of an ST TIMEKEEPER Device
WDI

INTEGRATED BATTERY CRYSTAL AND SNAPHAT

OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL

8, 16 x 8 TIMEKEEPER REGISTERS

POWER BATTERY LOW LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY SRAM ARRAY

A0-AX

DQ0-DQ7

E VPFD W G

VCC

IRQ/FT

RST

VSS

AI02482

December 1998

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AN925 - APPLICATION NOTE
A 1 Hz clock signal, from the clock chain, is used to update the seconds register. Each rising edge of the 1 Hz clock signal increments the system side of the seconds register. Having updated the seconds register a ripple carry to other registers might be initiated (for example, incrementing the minutes register from 00 to 01, after the seconds register has been incremented from 59 to 00). The longest possible ripple carry extends through all seven registers: seconds, minutes, hours, day of the week, date of the month, month of the year and year. Figure 2 shows two consecutive updates of the seconds register. The first update only updates the seconds register; the second update, though, ripples through all seven clock registers. When the system-side time registers have finished being updated, they are copied across to the user-side, thereby making the updated time available to the user. Thus, the spacing between successive System-to-User-Update-Pulse is one second plus a delta delay that can vary from 0.5 ms to 3.5 ms (1x0.5 ms to 7x0.5 ms). The M48T58 (revision B), M48T59 (revision B), M48T35 and M48T559 are examples of TIMEKEEPER devices that operate in this way. Figure 2. Time Update Waveform Diagram (variable delay)
1 Hz clock frequency Seconds register update Minutes register update Hours register update Day of week register update Date register update Month register update Year register update Reference update pulse System to user update pulse 12/31/96 23:59:59 1 second + 3.5ms 1/1/97 00:00:00
AI02483

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AN925 - APPLICATION NOTE
An alternative approach, shown in Figure 3, is adopted by the M48T02, M48T12, M48T08, M48T18, M48T58 (revision C), , M48T59 (revision C ), M48T37 and M48T201 devices. The spacing between successive System-to-User-Update-Pulse is always one second. Each pulse is delayed by the same delta time, of 3.5 ms, regardless of the number of registers that need incrementing within that period. Figure 3. Time Update Waveform Diagram (fixed delay)

1 Hz clock frequency Seconds register update Minutes register update Hours register update Day of week register update Date register update Month register update Year register update Reference update pulse System to user update pulse 12/31/96 23:59:59 = 1 second 1/1/97 00:00:00
AI02484

(These examples are each shown with the calibration set to zero.)

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AN925 - APPLICATION NOTE

If you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses:

apps.nvram@ st.com ask.memory@ st.com

(for application support) (for general enquiries)

Please remember to include your name, company, location, telephone number and fax number.

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 1998 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com

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Document Number: 5228



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