AN1089 APPLICATION NOTE
CONTROL LOOP MODELING OF L6561-BASED TM PFC
by Claudio Adragna
This paper provides a model and a tool for evaluating and improving the control loop characteristics of L6561-based PFC preregulators in boost topology and operated in Transition Mode (TM). Such a subject is now becoming topical since TM PFC preregulators are more and more used in systems other than electronic lamp ballast where the input voltage range is limited and the load current is almost constant. The ability to operate under large variations of both input voltage and load current, as well as the use of TM PFC systems as preregulators for switching converters, requires a more accurate design of the control loop. The goal will be not only to ensure a narrow bandwidth in order to achieve a high Power Factor, but also to have enough phase margin so as to make sure the system is stable over a large range of operating conditions.
INTRODUCTION PFC preregulators based on the boost topology working in Transition Mode (TM, see fig. 1) have been widespread in electronic lamp ballast systems. This kind of equipment almost always works under a single mains supply (110 or 220 VAC, with some tolerance) and the use of a PFC preregulator is mainly aimed at optimising the downstream half-bridge lamp driver and improving their inherent extremely poor PF. The PFC preregulator sees the downstream stage as a constant load, so it is requested to work under a limited range of operating conditions. From the control loop standpoint, this means that the frequency compensation of the error amplifier can be very simple, typically just a feedback capacitor. Its capacitance will be high enough to ensure the crossover frequency of the open loop gain is low, so as to achieve a high PF (see Ref. [1]). Figure 1. Typical L6561-based TM PFC preregulator
R7 Vcc
Compensation Network
+ R9 8 Vac 3 5 2 1 7 4 Co Vo
L6561
6
R10 Rs R8
March 2000
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AN1089 APPLICATION NOTE
Things get more complicated when an electronic ballast can supply two lamps and is required to work even if one lamp is not used or is exhausted, so that it is expected to work at half load as well. The L6561, thanks to its highly linear, wide dynamics multiplier, extends the use of TM PFC boost preregulators to applications that experience a wide range of operating conditions, both in terms of input voltage variations and load change. High power (60 to70 W) AC-DC adapters for portable equipment and computer monitor SMPS' are the most noticeable examples. This, however, calls for a more accurate design of the control loop than the one illustrated in Ref.[1]. The control goal will no longer be to achieve only a low crossover frequency but also an adequate phase margin. Besides ensuring stability over a large variety of operating conditions, this is necessary to prevent dangerous oscillations of the output voltage as a result of load changes. PFC Boost Preregulator Control Loop To the aim of finding a compensation network able to achieve the above mentioned control goal, it is necessary to get an insight into the control loop of such systems. This can be synthesised as shown in the block diagram of fig. 2. Figure 2. Control loop of a PFC Preregulator: Block Diagram
Virms
Z CD G3 ERROR AMPLIFIER VCOMP G 1(s) M ULT IPLIER G2 PW M MODULATOR POW ER STAGE G 4(s)
Vref
+ -
Vcspk
+ -
ILpk
Vo
F EEDBACK H
Figure 3. Control loop of a PFC Preregulator: electrical circuit and main quantities
L Vi Q R9 Vcs R1 0 Rs D
G4(s)
Co
H
Vo
R7 VREF
R8
G3
KP · Vi M ULT 3 CS 4 Z CD 5 Z CD S Q 7 PW M R V RE F (2 .5 V) STARTER DRIVER GD
Vcs
+ CO MPARATO R
L6561
M ULTI PLIER
2
G2
COM P
G1(s)
E/A CO MPENSATIO N NETW ORK
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-
VCOMP
E/A
+
1 INV
AN1089 APPLICATION NOTE
Fig. 3 illustrates how the various blocks of fig. 2 relate with the electrical circuit, both external and inside the L6561. For details on the internal circuit and its operation please refer to Ref. [1]. The loop gain of PFC preregulators must have a very low crossover frequency (fc) so as to maintain VCOMP (Error Amplifier output) fairly constant over a given line cycle and ensure a high PF. As a rule of thumb, fc should not exceed 20-25 Hz at maximum mains voltage. This allows to assume that the control action takes place on the peak amplitude (or, which is the same, the RMS value) of the various quantities inside the loop. The first step is to determine the transfer function of the power stage, G4(s), defined as: G4(s) = Figure 4. Power stage model,G4(s) dVo dVo dIo = dILpk dIo dILpk where Vo is the DC output voltage, Io the DC output current and ILpk is the peak value of the inductor current.
Io
Under the above assumption, the power stage can be modeled as illustrated in fig. 4: a controlled current source (with a shunt resistor Re) that drives the output bulk capacitor Co and the load resistance Ro (= Vo / Io). The zero due to the ESR associated with Co is far beyond the crossover frequency thus it is Re Co Ro neglected. Vo The current source can be characterised with the following considerations: the low frequency component of the boost diode current is found by averaging the discharge portion of the inductor current (the white triangles of fig. 5) over a given switching cycle. The low frequency current, averaged over a mains half-cycle yields the DC output current Io: _________________________ _ 1 ________________ 1 2 Virms sin ILpk sin 2 Virms ILpk Io = (1 - D) ILpk sin = = 4 Vo 2 2 Vo where D is the switch duty cycle, is the instantaneous phase angle of the mains voltage and Virms its effective (RMS) value. The AC model illustrated in fig. 4 can be found by calculating the total differential of the above expression of Io. A few algebraic manipulations would show that the shunt resistor Re always equals the DC load resistance Ro, thus it changes depending on the power delivered by the system. Now it is necessary to consider two separate cases. If the load is purely resistive (or equivalent to a resistor, like in the case of a lamp ballast circuit), the AC load resistance equals Ro. The parallel of this resistance with Re, combined with the output bulk capacitor, gives origin to a pole located at: p = 2 Ro Co
Figure 5. Boost PFC currents
Inductor current peak envelope ILpk Switch current Diode current Low frequency Diode current
Io
SWITCH
ON OFF
which is usually in the range of 1 to 5 Hz.
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AN1089 APPLICATION NOTE
In case the PFC preregulator provides a DC bus supplying a downstream switching converter, the load should be regarded as a "constant power" load rather than a resistor. In fact, as long as a switching converter is in regulation, the power it demands of the source is practically independent of the input voltage (converter's efficiency changes very little). In this case, the AC load resistance is equal to -Ro (if the DC bus decreases the current demanded of the PFC increases, whence the negative sign). As a result, the parallel combination with Re tends to infinity and the two resistances cancel. The current source drives only the output capacitor and the pole location tends to zero. In the end, G4(s) will be given by: 2 Virms Ro (resistive load) 8 Vo Ro Co 1+s G4(s) = 2 2 Virms 1. (constant power load) 4 Vo s Co The gain of the PWM modulator, G3, which includes the current loop, is simply: Figure 6. Plot of KM vs. E/A output
KM 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 2.5 3 3.5 4 VCOMP 4.5 5 5.5
G3 =
dILpk 1 = dVcspk Rs
where Rs is the sense resistor connected between the source of the external MOSFET and ground (across which the L6561 reads the inductor current through pin 3). To calculate the transfer function G2 of the multiplier block, one can consider that a variation VCOMP, due to a line and/or load change, modifies the peak amplitude Vcspk of the rectified sinusoid at the output of the multiplier. Therefore: G2 = dVcspk = KM KP 2 Virms dVCOMP
where KM is the gain of the multiplier and KP the partition ratio of the resistor divider that feeds a portion of the input voltage into pin 3. The electrical characteristics of the L6561 specify KM = 0.6 25% (@VCOMP = 4V, including temperature) but actually KM decreases for low values of VCOMP. In fig. 6 the typical value of KM is plotted against VCOMP along with the tolerance limits. Since VCOMP gets lower when the mains voltage is high, this variation of KM partly compensates for the increase of G2 with Virms, thus providing a mild voltage feedforward effect. If one wants to take this non-linearity into account, he or she should linearise the large-signal multiplier gain in the neighborhood of the quiescent point of the error amplifier, so as to get the small-signal gain (km). Please refer to [1] and the Appendix for the relevant calculation technique. Ultimately, the control-to-output transfer function will be: 1 km KP V 2irms Ro 1 (resistive load) 4 VO Rs RO CO 1+s = G2 G3 G4(s) = 2 1 km KP V 2irms 1 (constant power load) s CO Rs VO 2
G(s) =
dVO dVCOMP
where the small-signal multiplier gain km could be assumed equal to KM for simplicity.
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AN1089 APPLICATION NOTE
Figure 7. Typical compensation scheme in PFC preregulators for lamp ballast
Vo C3 R7
1 INV
2 _ E/ A +
TO MULTIPLIER
R8 2.5V
L6561
From the above equations, it is apparent that the gain of the control-to-output function is strongly dependent on the input voltage, despite the slight compensation provided by KM. For design purpose, G(s) will have to be considered at the maximum mains voltage, where the gain is maximum and the loop bandwidth is maximum as well. The feedback block is usually made up of a simple resistor divider (see fig. 7). Only the upper resistor R7 is significant to the loop gain (the lower resistor R8 just sets the value of Vo). It is then convenient to assume H=1 and to consider R7 as a part of the error amplifier block G1(s).
Error Amplifier Compensation In PFC preregulators that supply an electronic lamp ballast the error amplifier is compensated typically as shown in fig. 7 (see also Ref. [2] and [3]). For this kind of load this circuit gives satisfactory results. It may not be acceptable, however, in other systems where stability must be ensured over a wide range of input voltage and load current, and does not work at all when the PFC preregulator supplies a switching converter. Figure 8 shows the suggested compensation schemes for both the cases under consideration. With a resistive load the loop can be stabilised by adding a pole in the origin plus a low frequency zero that compensates the pole of the control-to-output gain (network a). Ideally, this can give the desired bandwidth with 90 phase margin as well as high DC gain for good load regulation. With a constant power load the control-to-output gain has a pole in the origin thus the DC gain of the error amplifier should be externally limited with a feedback resistor. If not, a second pole in the origin would be introduced, which would result in a system whose stability might be critical. Limiting the gain goes to the detriment of preregulator's load regulation but this has not a serious impact on the overall system since the downstream converter will easily compensate for that. The compensation network (b) adds a pole-zero couple that both makes the gain roll off at low frequency (so as to cross the 0 dB axis at low frequency) and boosts the phase in the neighborhood of the crossover frequency (so as to increase phase margin). The transfer functions of the compensation networks of fig. 8 a) and b) are respectively: 1 + s C3 R11 (circuit a - resistive load) dVCOMP s C3 R7 G1(s) = = dVO 1 + s C3 R11 R12 (circuit b - constant power load) R7 1 + s C3 (R11 + R12) Figure 8. Suggested compensation networks for TM boost PFC
Vo C3 R7 COM P 1 INV 2 _ E/A + INV TO MULTIPLIER R8 2.5V R11 R7 C3 1 R11 2 _ E/A + COMP Vo R12
TO MULTIPLIER
R8
L6561
2.5V
L6561
a) resistive load
b) constant power load
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AN1089 APPLICATION NOTE
As a tool to ease the design of L6561's E/A compensation networks in TM boost PFC preregulators, the Appendix contains a Mathcad file gathering the theory above illustrated and performing all the necessary calculations. Conclusions This paper gets an insight into the control loop of TM controlled Boost PFC preregulators based on the L6561 PFC controller. This reveals that the simple feedback capacitor used to compensate the error amplifier in preregulators for lamp ballast may not be adequate in systems that may experience large variations in input voltage and/or load current. Moreover it leads to an unstable loop if the load is a switching converter. Appropriate compensation schemes are suggested for both cases and a calculation tool (Mathcad file) is provided so as to make control loop design easier in such systems. References [1] "L6561, Enhanced Transition Mode Power Factor Corrector", (AN966) [2] "L6569 - L6561 Lighting Application with PFC" (AN991) [3] "Electronic Ballast with PFC Using L6574 and L6561" (AN993) [4] "Design Equations of High-Power-Factor Flyback Converters Based on the L6561" (AN1059) [5] "Flyback Converters with the L6561 PFC Controller" (AN1060) Appendix This Mathcad file allows to design the control loop and performs a stability analysis of PFC preregulators in boost topology operated in Transition Mode and controlled by the L6561. Highlighted equations indicate data that must be manually entered. These data are supposted to be known to the user as a result of the design of the PFC preregulator (the use of the PFC design software included in the CD-ROM "Linear and Switching Voltage Regulators" is recommended). The example values are taken from the L6561 demo board circuit. PFC Converter Data: Output Voltage Output Capacitor Sense Resistor Output Overvoltage Threshold Expected Efficiency Multiplier Biasing: Input Divider Upper Resistor Input Divider Lower Resistor Analysis Setpoint: Mains RMS Voltage Output Power Virms := 264 PO := 80 V W Rup := 1240 Rlow := 10 k k VO := 400 CO := 47 Rs := 0.41 OVP := 40 := 0.9 V F V
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AN1089 APPLICATION NOTE
Preliminary calculations & Service Variables: Equivalent Load Resistance
Ro :=
VO2
PO
RO = 2 103
Input Divider Gain Large-signal Multiplier Gain: Error Amplifier Quiescent Point:
KP :=
Rlow Rlow + Rup
KP = 8 10-3
KM(VCOMP) := 0.651 (1 - 85.29 e-1.776 VCOMP) VCOMP := 4 2 Po RS KM(VCOMP) KP Vir ms VCOMP = 2.898
2
VCOMP := root 2.5 +
- VCOMP, VCOMP [V]
d [KM(VCOMP) (VCOMP - 2.5)] dVCOMP km = 0.557 -----------------------------------------------------------------------------------------------------------------------------------------Small signal Multiplier Gain
km:=
j: = -1
n: = 100
Dec: = 6
w:= 0,1..n
(w): = 10w
Dec -1 n
f: = 1
Control-to-Output Transfer Function (constant power load): G () : = km KP Virms2 1 106 RS j CO 2 VO /G
150
¦G ¦
89
100 deg 3 1 .10 dB
50
90
0
50 0.1
1
10 f
100
91 0.1
1
10 f
100
3 1 .10
Compensated E/A Transfer Function (constant power load, refer to fig.8b) DC gain (VO/VCOMP): Pole: Zero: GO := 0.30 p := 0.23 z := 15 Hz Hz
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AN1089 APPLICATION NOTE
2z G1() := GO 1+j 2p 1+j ¦G1¦ /G1
Transfer Function:
0
0 20
20 deg dB
40 60
40 80 60 3 1 .10 100 0.1 3 1 .10
0.1
1
10 f
100
1
10 f
100
Open Loop Transfer Function (constant power load): F(): = G () G1 () F(): = arg (F()) 180
100
¦F ¦
0 40 80 120 160
/F
0
100 0.1
deg 3 1 .10
dB
1
10 f
100
200 0.1
1
10 f
100
3 1 .10
Crossover Frequency:
fc: = |root (|F(2 f)| - 1, f)| fc = 18.836 Hz : = 180 + F(2 fc) = 52.167
Phase Margin:
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AN1089 APPLICATION NOTE
Feedback Network Implementation (constant power load, refer to fig. 8b):
Output Divider Upper Resistor
R7: =
OVP 103 40 k R8 = 6.289 R12 = 300 k k
Output Divider Lower Resistor Parallel Feedback Resistor: Series Feedback Capacitor
R7 = 1 103 2.5 R8: = R7 VO - 2.5 R12: = GO R7
C3: =
106 1 1 2 R12 p z nF R11 = 4.672 k
C3 = 2.271 103 Series Feedback Resistor R11: = 106 2 z C3
Control-to-Output Transfer Function (resistive load): km KP Virms2 RO Rs 4 VO
G() : =
1 1 + j CO RO 10-6 2
100
¦G¦
0 20
/G
50 deg dB
40 60
0 80 50 0.1 3 1 .10 100 0.1 3 1 .10
1
10 f
100
1
10 f
100
Pole Location:
p :=
106 RO CO
p = 3.386
Hz
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AN1089 APPLICATION NOTE
Compensated E/A Transfer Function (resistive Load, refer to fig. 8a): High Frequency Gain: Zero: Transfer Function: Gh := 0.005 z := 15 G1() := Gh 2 z 1+j 2z j Hz
20
¦G 1 ¦
0 20 40 60
/G1
0 deg 3 1 .10 dB
20
40
80 100 0.1 3 1 .10
60
0.1
1
10 f
100
1
10 f
100
Open Loop Transfer Function (resistive load) F(): = G() G1() F(): = arg (F()) 180 /F
100
¦F ¦
0 40 80
50 deg dB
0
120 50 160 3 1 .10 200 0.1 3 1 .10
100 0.1
1
10 f
100
1
10 f
100
Crossover Frequency:
fc: = |root (|F(2 f )| - 1, f)| fc = 19.805 Hz
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AN1089 APPLICATION NOTE
Phase Margin: : = 180 + F(2 fc) = 62.563 Feedback Network Implementation (resistive load, refer to fig. 8a): Equivalent Load Resistance
R7: = R8: =
OVP 103 40 2.5 R7 VO - 2.5
R7 = 1 103
k
Output Divider Lower Resistor
R8 = 6.289
k
Series Feedback Capacitor
C3: =
106 2 z Gh R7 106 2 z C3
C3 = 2122 103
nF
Series Feedback Resistor
R11: =
R11 = 5
k
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AN1089 APPLICATION NOTE
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