STD2000
Single-Chip Worldwide iDTV Processor
DATABRIEF
SD/HD Digital Video SD/ID Analog Video Dual DDEC 3D Comb
HD Video Display Pipeline (TNR, DEI, Scaling, IQI) Compositor Display Driver Display
LCD PDP DL P CRT
ID Video Display Pipeline (TNR, DEI, Scaling, IQI) Graphics
Peripherals H/V SRC ST Bus On-Chip Interconnect VBI DMA Digital E ncoder
E MI
LMI
Dual Transpor t Demux
Video Dec oder MPEG-2 MP @HL MP @M Lx2
Audio DSP MPEG 1&2 MP3 Dolby Digital Decoder
ST40 CPU 266 MHz 480 MIPS 16K - I, 32K-D
Gamma 2D Graphics
Digital Audio In MPE G -2 Audio & Video Dual C.I. / One CableCardTM
DDR SDRAM
Dual-Channel High Definition Video Processor
Up to 12-bit Video Processing
3D Digital Luma/Chroma Noise Reduction 3D Motion Adaptive Pixel-based Advanced Deinterlacing with Diagonal Compensation Contour Sensitive De-interlacing CSDiTM Flexible H/V Scaling Engine with Multi Window management capabilities Image Quality Improvement Engine for crystal clear and crisp pictures
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VCR DVD Recorder
Chassis Cont rol
Digital Audio Out
Dual DVB-CI/one CableCARDTM interface MP@ML Dual Channel or MP@HL Single Channel MPEG-2 Video decoder 24-bit audio DSP Core, MPEG-1 (Layers 1, 2 & 3), MPEG2, Dolby Digital Decoder Gamma 2D Graphics Engine for Middleware graphics and On-Screen Display Auxiliary Video/Graphics Sub-System for Monitor output Exhaustive set of peripherals for DTV Chassis Control DDR333 Unified Memory Interface (LMI) Programmable External Memory Interface (EMI) CRT and Flat Panel Display Video Outputs 27 MHz Crystal Oscillator
Rev. 2
Dual Digital Chroma Decoder (PAL/SECAM/NTSC) with 3D/2D Comb Filter and Dual VBI Data Slicer Powerful 32-bit RISC ST40 CPU (266 MHz, 480 MIPS) Dual Transport Stream Demux with DES, DVB and Multi2 Descrambler
January 2006
1/11
STD2000
Dual Channel Video Input Processor
Analog Video Inputs
Zoom In or Zoom out (X and Y independent linear factors from x0.25 to x4) Panoramic mode H or V crop and independent rescaling Compositor supporting Monochrome and Graphics planes Video two-channel HD processing for: PIP/POP, Picture And Picture (Perfect PAP), Picture In Graphic (PIG) Color Space Translator (conversion to YCrCb 4:4:4 or RGB coding) Gamma Correction with programmable anycurve correction Perfect Color Engine (spatio-temporal dithering down to 4-to-8 bits) RGB 3x10-bit Digital output to flat panel or DMD RGB or YUV analog outputs Color warping for color gammut correction
CVBS, Y/C, 1H/2H/2.14H YPrPb, 1H/2H RGB analog inputs D1/HD Digital video input (CCIR 601-656 / SMPTE 274M, SMPTE 296M, SMPTE 260M) YCL Digital video input (proprietary port; YCrCb-4:2:2, 2H for off-chip Motioncompensated Video Processing) RGB to YCrCb 4:2:2 conversion Dual Digital Chroma Decoder (PAL/NTSC/SECAM) 3D Comb Filter support on one channel, adaptative 4H/2D comb filter on second channel Dual VBI data slicer for Teletext, CC, WSS and other systems 3:2/2:2 Pulldown, Video/Movie and Scene Change Detection 3D Digital Luma and Chroma Motion Adaptive Noise Reduction Automatic Letterbox Detection
Digital Video Inputs
Video Output Control
Analog Video Pre-Processing
CPU Sub-System
Dual Channel High Definition Video Processor
Image Processing
24, 25, 30, 50, 60 to 50, 60, 75, 100, 120 Hz Field up-rate conversion 3D Motion-adaptive pixel-based advanced deinterlacing with diagonal compensation (CSDiTM: Contour Sensitive Desinterlacer)
Image Quality Improvements
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32-bit RISC ST40 CPU (266 MHz, 480MIPs) 16 Kbytes I-Cache and 32 Kbytes D-Cache RAM Floating Point Unit (FPU) Memor y Management Unit (MMU)
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On-Chip Memory (64 Kbytes SRAM) Services Test Access Port and its link (JTAG based) Diagnostic Controller Unit (for low intrusion, real-time debugging) Advanced User Debug support System Bus Analyzer (SBAG)
LTI and CTI Contrast Enhancer: Black-White Stretch Blue Stretch Green Boost, Auto-Flesh and Tint Control Peaking: Adaptive Peaking and Coring Horizontal/Ver tical Format Conversion Suppor t of 4:3 and 16:9 display aspect ratios
Dual Transport Stream Processor
Dual Transport Stream Demux DES, DVB and Multi2 descramblers Dual Transport processing: DVB or ATSC (ISO/IEC 13818-x and A53) DVB-CI interface (Dual Slot support) CableCARDTM interface (Single Slot support)
Video Scaling & Composition
2/11
STD2000
MPEG2 Digital Video Decoder
DTV Chassis Control
MPEG2 Video (ISO/IEC 13818-2, ATSC-A54) MP@ML Dual-channel Decode or MP@HL Single-channel Decode Data Extraction (closed caption,...)
Two UARTs One Smartcard interface Two I²C (2 channels each) Four-channel PWM with input capture and compare Real-time Clock and WatchDog timer Infrared Receiver/Transmitter 10-bit, 8-channel low-speed A/D Converter 8 external interrupt channels with Interrupt Level Controller More than 56 General Purpose IOs Low-power mode and wake-up controller
Digital Audio Decoder
24-bit audio DSP Core (with embedded Software & Patch RAM) MPEG1 (layers 1, 2 & 3), MPEG2, Dolby Digital / ATSC-A52 Lt/Rt Downmix for standard Stereo digital outputs Triple I²S channel outputs One PCM/Stream or I²S Input (S/PDIF external receiver or HDMI) S/PDIF Digital Output (IEC60958 and IEC61937)
Interfaces
Local Memory Interface (LMI)
64-bit, dual-port DDR memory interface 16- and 32-bit DDR-SDRAM device support Up to 166 MHz support Suppor t devices of up to 512 Mbits
Gamma 2D Graphic Processor
Full Screen or windowed Bitmap area ARGB-4444 Graphics plane in mixed mode 2D-Graphics hardware accelerator GFx/Video programmable alpha-blending Background Color Plane Horizontal and/or Vertical Scrolling, controlled by software
Auxiliary Video/Graphics Processor
On-chip PAL/NTSC/SECAM Encoder for monitor output
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Encoding of Teletext, WSS, VPS or Closed Caption Graphics plane for optional Subtitle support Macrovision Copy Protection (Factory Disable option)
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Programmable External Memory Interface (EMI) 16-bit/8-bit External Memory Interface for supporting Flash and optional peripherals Suppor t NOR Flash devices of up to 256 Mbits 6 separately configurable banks Suppor t for external memory-mapped ICs or sub-systems RGB 3x10-bit digital output to flat panel or DMD RGB or YUV analog outputs for CRT
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FDP and CRT Video Outputs
3/11
General Information
STD2000
1
1.1
General Information
Introduction
The STD2000 is a highly-integrated, high performance system-on-chip iDTV processor that combines Set-top Box decoding facility with a powerful TV processor. A dual-channel PIP/PAP video processor supports High Definition formats. Its advanced integration drastically reduces integrated Digital TV BOM costs by removing redundancy between Analog and Digital source video processing. Compliant with worldwide standards such as ATSC, DVB-T, ISDB-T and the Chinese Digital Terrestrial Standard, the STD2000 also includes a built-in CableCARDTM interface for US OpenCableTM specifications and a dual DVB-CI interface for European DVB-T specifications.
1.2
Typical Applications
Typical applications for the STD2000 system-on-chip are illustrated in the following diagrams:
Figure 1: US LCD Digital Cable Ready HDTV
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4/11
STD2000
Figure 2: China CRT Digital Cable HDTV
General Information
CA
Chinese C.I.
Figure 3: Europe LCD iDTV
Optional
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5/11
STD2000 Pin List
STD2000
2
2.1
STD2000 Pin List
General Package Information
The STD2000 is delivered in a 745-ball BGA package.
Table 1: BGA Package Information
Package Type Body Size Ball Count Ball Pitch Ball Matrix Center Matrix MCM-BGA 40 x 40 745 1.27 31 x 31 (5-row perimeter) 15 x 15 mm Balls mm Balls Balls
Figure 4: STD2000 Package Overview
LMI 1
A1 B1 C1 D1 E1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5 R5 T5 U5 V5 J9 K9 L9 M9 N9 P9 J10 K10 L10 J11 K11 L11 J12 K12 L12 J13 K13 L13 A6 B6 C6 D6 E6 A7 B7 C7 D7 E7 A8 B8 C8 D8 E8 A9 B9 C9 D9 E9 A10 B10 C10 D10 E10 A11 B11 C11 D11 E11 A12 B12 C12 D12 E12 A13 B13 C13 D13 E13 A14 B14 C14 D14 E14 A15 B15 C15 D15 E15 A16 B16 C16 D16 E16 A17 B17 C17 D17 E17 A18 B18 C18 D18 E18 A19 B19 C19 D19 E19 A20 B20 A21 B21 A22 B22 A23 B23 A24 B24
C20 D20 E20
LMI 2
F1 G1 H1 J1 K1
2.5V Supply
J14
K14 L14
Feed_Back 2.5V
L1 M1
M10 N10 P10
System 2
N1 P1 R1
YCL
T1 U1
D1 out
V1 W1 Y1
D1 In Audio
COMs
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AA1 AA2 AA3 AB1 AB2 AB3 AC1 AC2 AC3 AD1 AE1 AF1 AG1 AH1 AJ1 AK1 AL1 AD2 AE2 AF2 AG2 AH2 AJ2 AK2 AL2 AD3 AE3 AF3 AG3 AH3 AJ3 AK3 AL3
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W4 Y4 W5 Y5 AA4 AA5 AB4 AC4 AD4 AE4 AF4 AG4 AH4 AJ4 AK4 AL4 AB5 AC5 AD5 AE5 AF5 AG5 AH5 AJ5 AK5 AL5 AG6 AH6 AJ6 AK6 AL6
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R9 T9
R10 T10
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M11 N11 P11 M12 N12 P12 M13 N13 P13 R11 T11 U11 V11 W11 Y11 AA11 AB11 AC11 R12 T12 U12 V12 W12 Y12 AA12 AB12 AC12 R13 T13 U13 V13 W13 Y13 AA13 AB13 AC13
M14 N14 P14 R14 T14 U14 V14
Ob J15 J16 J17 K15 L15 K16 L16 K17 L17 M15 N15 P15 R15 T15 U15 V15 W15 Y15 AA15 AB15 AC15 M16 N16 P16 R16 T16 U16 V16 W16 Y16 AA16 AB16 AC16 M17 N17 P17 R17 T17 U17 V17 W17 Y17 AA17 AB17 AC17
J18
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J19 K19 L19 M19 N19 P19 R19 T19 U19 V19 W19 Y19 AA19 AB19 AC19
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C21 C22 C23 C24 D21 E21 D22 E22 D23 E23 D24 E24 J21 K21 L21 M21 N21 P21 R21 T21 U21 V21 W21 Y21 AA21 AB21 AC21 J22 K22 L22 M22 N22 P22 R22 T22 U22 V22 W22 Y22 AA22 AB22 AC22 J23 K23 L23 M23 N23 P23 R23 T23 U23 V23 W23 Y23 AA23 AB23 AC23
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A25 A26 B25 B26 C25 C26 D25 E25 D26 E26
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A27 A28 A29 B27 C27 D27 E27 F27 G27 H27 J27 K27 B28 C28 D28 E28 F28 G28 H28 J28 K28 L28 M28 N28 P28 R28 T28 U28 V28 W28 Y28 AA28 AB28 AC28 AD28 AE28 AF28 AG28 AH28 AJ28 AK28 AL28 B29 C29 D29 E29 F29 G29 H29 J29 K29 L29 M29 N29 P29 R29 T29 U29 V29 W29 Y29 AA29 AB29 AC29 AD29 AE29 AF29 AG29 AH29 AJ29 AK29 AL29
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A30 B30 C30 D30 E30 F30 G30 H30 J30 K30 L30 M30 N30 P30 R30 T30 U30 V30 W30 Y30 AA30 AB30 AC30 AD30 AE30 AF30 AG30 AH30 AJ30 AK30 AL30 A31 B31 C31 D31 E31
EMI
F31 G31 H31 J31 K31 L31 M31
J20
K18 L18
K20 L20 M20 N20 P20 R20 T20 U20 V20 W20 Y20 AA20 AB20 AC20
3.3V Supply
L27 M27 N27 P27 R27 T27 U27 V27 W27 Y27 AA27 AB27 AC27 AD27 AE27 AF27
M18 N18 P18 R18 T18 U18 V18
Power supply feedback 2
3.3V Supply (4)
AG7 AH7 AJ7 AK7 AL7 AG8 AH8 AJ8 AK8 AL8 AG9 AH9 AJ9 AK9 AL9
test
(NC)
N31 P31 R31 T31 U31 V31 W31 Y31 AA31 AB31 AC31 AD31 AE31 AF31 AG31 AH31 AJ31
Supply 1.0V
U9 V9
U10 V10
Denc Ref
W9 Y9 AA9 AB9 AC9
W10 Y10 AA10 AB10 AC10
W14 Y14 AA14 AB14 AC14
W18 Y18 AA18 AB18 AC18
Test
CI
Supply 1.8V (4) Analog Out Ref
AG10 AH10 AJ10 AK10 AL10 AG11 AH11 AJ11 AK11 AL11 AG12 AH12 AJ12 AK12 AL12 AG13 AH13 AJ13 AK13 AL13
Supply 3.3VA
Supply 1.8VA (4)
Analog In Ref
AG14 AH14 AJ14 AK14 AL14 AG15 AH15 AJ15 AK15 AL15 AG16 AH16 AJ16 AK16 AL16 AG17 AH17 AJ17 AK17 AL17 AG18 AH18 AJ18 AK18 AL18
2.5V Analog Supply (6)
AG19 AH19 AJ19 AK19 AL19 AG20 AH20 AJ20 AK20 AL20 AG21 AH21 AJ21 AK21 AL21 AG22 AH22 AJ22 AK22 AL22 AG23 AH23 AJ23 AK23 AL23 AG24 AH24 AJ24 AK24 AL24 AG25 AH25 AJ25 AK25 AL25 AG26 AH26 AJ26 AK26 AL26
AG27 AH27 AJ27 AK27 AL27
TS2 In
AK31 AL31
PIOs
Scan
Analog out
Analog In
Denc
System1
Audio
COMs
TS1 In
6/11
2.2
STD2000
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Ballout Description
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GND GND GND GND GND GND GND GND GND GND GND GND GND VDD33P EMI_CSN0 EMI_CSN1 EMI_WAIT (NC-15) TDI TDO
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20
DDR2_CAS DDR2_BA1 DDR2_AD3 DDR2_BA0 DDR2_D13 DDR2_D8 DDR2_DQS0 DDR2_D4 DDR2_D0 DDR1_D28 DDR1_D24 DDR1_DM2 DDR1_D21 DDR1_D17 DDR1_AD6 DDR1_AD8 DDR1_CLK DDR1_AD5 DDR1_CS DDR1_AD3 DDR1_RAS DDR1_D14 DDR1_D10 DDR1_DM1 DDR1_D7 DDR1_D3 EMI_A2 EMI_A6 EMI_A18 EMI_R/WN EMI_A20 DDR2_VREF DDR2_CS DDR2_AD2 DDR2_AD10 DDR2_D14 DDR2_D9 DDR2_DM0 DDR2_D5 DDR2_D1 DDR1_D29 DDR1_D25 DDR1_DM3 DDR1_D22 DDR1_D18 DDR1_AD4 DDR1_AD11 DDR1_AD12 DDR1_VREF DDR1_BA1 DDR1_AD1 J2 J3 J4 J5 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J27 J28 J29 J30 J31 K1 K2 K3 K4 K5 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K27 K28 K29 K30 K31 L1 L2 M23 M27 M28 M29 M30 M31 N1 N2 N3 N4 N5 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N27 N28 N29 N30 N31 P1 P2 P3 P4 P5 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 T16 T17 T18 T19 T20 T21 T22 T23 T27 T28 T29 T30 T31 U1 U2 U3 U4 U5 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U27 U28 U29 U30 U31 V1 V2 V3 V4 V5 V9 V10 V11 V12 V13 V14 V15 V16
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20
DDR2_CLK DDR2_AD12 DDR2_AD9 DDR2_AD1 DDR2_D15 DDR2_D10 DDR2_DM1 DDR2_D6 DDR2_D2 DDR1_D30 DDR1_D26 DDR1_DQS3 DDR1_D23 DDR1_D19 DDR1_D16 DDR1_CKE DDR1_AD9 DDR1_CAS DDR1_AD0 DDR1_AD10 DDR1_D15 DDR1_D12 DDR1_D8 DDR1_DQS0 DDR1_D5 DDR1_D1 EMI_A4 EMI_A13 EMI_A12 EMI_A14 EMI_A15 DDR2_AD11 GND DDR2_CLKN DDR2_CKE DDR2_WE DDR2_D11 DDR2_DQS1 VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P VDD25P
GND DDR2_DQS3 DDR2_D25 DDR2_D24 GND GND GND GND GND GND GND DDR_REXT GND GND GND GND GND GND GND VDD33P EMI_OE EMI_D0 EMI_FLA_CSN EMI_A0 DDR2_D31 DDR2_D30 DDR2_D27 DDR2_D29 DDR2_D28
Figure 5: Ballout Information (Part 1)
GND VDD33P (NC-9) (NC-10) (NC-8) (NC-7) SBA_SYNC AUD_CK AUD_DAT2 AUD_DAT0 AUD_DAT1 VPP GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDD33P (NC-5) (NC-6) (NC-4) (NC-3) SBA_CK SBA_DAT0 SBA_DAT3 SBA_DAT1 SBA_DAT2 VDD10P GND GND GND GND GND GND GND GND GND GND GND GND GND GND
GND Y9 MS_TDI GND Y10 GND GND Y11 GND GND Y12 GND GND Y13 GND GND Y14 GND GND Y15 GND GND Y16 GND VDD33P Y17 GND CI2_MDI0 Y18 GND CI1_MISTRT Y19 GND CI1_MDI0 Y20 GND CI2_MDI1 Y21 GND YCL_VAL Y22 GND YCL_VSYNC Y23 GND D1O_BI_CBI_2 Y27 GND D1O_BI_CBI_0 Y28 CI1_MOVAL D1O_BI_CBI_1 Y29 CI2_MOVAL VDD10P Y30 CI2_MDO5 GND Y31 CI1_MDO5 GND AA1 D1I_HD_CK GND AA2 D1I_HD_HSYNC GND AA3 I²SI_SCK GND AA4 D1I_HD_VSYNC GND AA5 I²SI_LRCK GND AA9 MS_TMS GND AA10 MS_TSTRSTN GND AA11 GND GND AA12 MS_SCANMODE GND AA13 MS_TSTMODE GND AA14 GND GND AA15 TST_AFE0 DENC_VREF AA16 TST_AFE1 CI1_WAIT AA17 TST_AFE2 CI2_MIVAL AA18 TST_AFE3 CI2_WAIT AA19 GND CI1_MIVAL AA20 MS_TSTCK27 CI2_MISTRT_POD_OOB_DI 21 MS_TSTCK54 AA D1O_BI_CBI_3 AA22 MS_TSTCK81 D1O_BI_CBI_4 AA23 GND D1O_BI_CBI_7 AA27 CI2_IREQ D1O_BI_CBI_5 AA28 CI1_IREQ D1O_BI_CBI_6 AA29 CI1_MDO3 VDD10P AA30 CI2_MDO4 GND AA31 CI1_MDO4 GND AB1 I²SI_MCK GND AB2 I²SI_DAT GND AB3 INT7 GND AB4 SDA1 GND AB5 SCL1 GND AB9 MS_TRST
AC30 CI1_MDO0 AC31 CI2_MDO1 AD1 MAFEIF_FSI AD2 SC_CLK AD3 SC_DATA AD4 SC_RST AD5 SC_CMD_VCC AD27 CI1_CE1_POD_CE2 AD28 CI_OE AD29 CI2_CE1_POD_CE1 AD30 CI_IORD AD31 CI_IOWR AE1 SC_DETECT AE2 CDA_REQ_RXD AE3 CDA_DAT_CTS AE4 CDA_CK_TXD AE5 CDA_DVAL_RTS AE27 CI2_MDI6 AE28 CI1_MDI6 AE29 CI1_MDI5 AE30 CI2_MDI7 AE31 CI1_MDI7 AF1 INT0 AF2 INT1 AF3 GPIO2 AF4 GPIO0 AF5 GPIO1 AF27 CI1_MDI3 AF28 CI2_MDI4 AF29 CI2_MDI3 AF30 CI1_MDI4 AF31 CI2_MDI5 AG1 TIMER1_PWM4 AG2 V10_REG_OUT AG3 V18_REG_OUT AG4 SDA0 AG5 SCL0 AG6 VDD33S AG7 VDD33S AG8 VDD33S AG9 VDD33S AG10 IREF_ABE AG11 GNDREF_ABE AG12 VREF_ABE AG13 REFP_AFE_F AG14 REFN_AFE_F AG15 RREF_AFE AG16 RREF_GND_AFE AG17 VREF_AFE AG18 REFP_AFE_S AG19 VCC10P
AH31 TS2_DIN1 AJ1 FPD_B5 AJ2 FPD_B4 AJ3 FPD_B3 AJ4 FPD_G7 AJ5 FPD_G4 AJ6 FPD_G0 AJ7 FPD_R6 AJ8 FPD_R2 AJ9 FPD_DE_PWM3 AJ10 HOUTA_PWM2 AJ11 HCLKVBK AJ12 ROUT AJ13 SVM AJ14 CVBS2_Y2_N AJ15 R1_C1_PR1_P AJ16 VSYNC AJ17 DENC_Y AJ18 SSCG_CKI AJ19 XTALOUT AJ20 CLKXTP AJ21 I2SO_DAT2 AJ22 I2SO_MCK AJ23 INT3 AJ24 AD4 AJ25 TIMER0_BLAST_OUT AJ26 SDA2 AJ27 TS1_DIN6 AJ28 TS1_DIN2 AJ29 TS1_CK AJ30 TS2_DIN5 AJ31 TS2_DIN4 AK1 FPD_B2 AK2 FPD_B1 AK3 FPD_G8 AK4 FPD_G6 AK5 FPD_G2 AK6 FPD_R8 AK7 FPD_R4 AK8 FPD_R0 AK9 FPD_CK1_VFLYBACK AK10 HS_OUT AK11 DPC AK12 BOUT AK13 C2_PR2_N AK14 CVBS1_Y1_PB2_N AK15 G1_CVBS1P_Y1P_P AK16 B1_PB1_N AK17 GND AK18 GND AK19 GND
STD2000 Pin List
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7/11
8/11
ball signal ball signal ball signal ball signal ball signal ball signal
STD2000 Pin List
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Figure 6: Ballout Information (Part 2)
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B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31
DDR1_WE DDR1_D13 DDR1_D9 DDR1_DM0 DDR1_D6 DDR1_D2 EMI_A3 EMI_A7 EMI_A21 EMI_A19 EMI_A8 DDR2_AD7 DDR2_AD5 DDR2_AD0 GND DDR2_RAS DDR2_D12 GND DDR2_D7 DDR2_D3 DDR1_D31 DDR1_D27 GND DDR1_DQS2 DDR1_D20 GND DDR1_CLKN DDR1_AD7 GND DDR1_AD2 DDR1_BA0 GND DDR1_D11 DDR1_DQS1 GND DDR1_D4 EMI_A1 EMI_A5 EMI_A17 EMI_A9 EMI_A10 EMI_A11 L3 L4 L5 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L27 L28 L29 L30 L31 M1 M2 M3 M4 M5 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 P27 P28 P29 P30 P31 R1 R2 R3 R4 R5 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R27 R28 R29 R30 R31 T1 T2 T3 T4 T5 T9 T10 T11 T12 T13 T14 T15 V17 V18 V19 V20 V21 V22 V23 V27 V28 V29 V30 V31 W1 W2 W3 W4 W5 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W27 W28 W29 W30 W31 Y1 Y2 Y3 Y4 Y5 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31
E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 F1 F2 F3 F4 F5 F27 F28 F29 F30 F31 G1 G2 G3 G4 G5 G27 G28 G29 G30 G31 H1 H2 H3 H4 H5 H27 H28 H29 H30 H31 J1
VDD25P VDD25P VDD25P VDD25P VDD25P DDR1_D0 EMI_A22 EMI_A16 EMI_CSN2 EMI_D15 EMI_D7 DDR2_D17 DDR2_D16 DDR2_AD8 DDR2_AD4 DDR2_AD6 EMI_D6 EMI_D13 EMI_D14 EMI_D5 EMI_D12 DDR2_D21 DDR2_D20 DDR2_D18 GND DDR2_D19 VDD33P EMI_D11 EMI_D4 EMI_D3 EMI_D10 DDR2_DM3 DDR2_DM2 DDR2_D22 DDR2_DQS2 DDR2_D23 VDD33P EMI_D9 EMI_D2 EMI_D1 EMI_D8 DDR2_D26
V25_REG_OUT ASEBRK RESETN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDD33P (NC-13) (NC-14) (NC-12) (NC-11) AUD_DAT3 AUD_SYNC TRST TCK TMS CORE_TST GND GND GND GND GND GND GND GND GND GND GND GND GND
VDD33P (NC-1) (NC-2) CI1_CI2_CS CI1_CD2 YCL_RI_CRI_4 YCL_RI_CRI_3 YCL_RI_CRI_0 YCL_RI_CRI_2 YCL_RI_CRI_1 VDD10P GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDD33P CI1_MDI2 CI2_CD2 CI2_MDI2 CI1_MDI1 YCL_RI_CRI_5 YCL_RI_CRI_6 YCL_REQ YCL_RI_CRI_7 YCL_CK VDD10P GND GND GND GND GND GND
GND AB10 GND AB11 GND AB12 GND AB13 GND AB14 GND AB15 DENC_IREF AB16 CI2_MCLKI_POD_OOB_ AB17 CI1_MCLKI_POD_A14 AB18 CI1_MDO7 AB19 CI2_RESET AB20 CI1_RESET AB21 D1O_CK AB22 GND AB23 D1I_GI_YI82 AB27 D1I_GI_YI_0 AB28 D1I_GI_YI_1 AB29 VDD10P AB30 GND AB31 GND AC1 GND AC2 GND AC3 GND AC4 GND AC5 GND AC9 GND AC10 GND AC11 GND AC12 GND AC13 GND AC14 GND AC15 GND AC16 CI1_MCLKO AC17 CI2_MDO6 AC18 CI2_MCLKO_POD_RC74AC19 CI1_MDO6 AC20 CI2_MDO7 AC21 D1I_GI_YI_3 AC22 D1I_GI_YI_4 AC23 D1I_GI_YI_7 AC27 D1I_GI_YI_5 AC28 D1I_GI_YI_6 AC29
GND GND GND GND GND GND GND GND GND GND GND GND GND GND CI2_MDO2 CI1_MDO2 CI1_MDO1 CI_WE CI2_MDO3 INT6 MAFEIF_DOUT MAFEIF_DIN MAFEIF_HC1 MAFEIF_SCLK MS_TCK MS_TDO VDD18S VDD18S VDD18S VDD18S VCC33S VCC33S VCC33S VCC18S VCC18S VCC18S VCC18S GND GND CI1_MOSTRT CI2_MDO0_POD_A8 CI2_MOSTRT_POD_A9
VCC10P VCC25P I2SO_SCK INT2 AD3 IR INT5 TS1_DIN7 TS2_CK TS2_DIN0 CI2_CD1 CI1_CD1 FPD_B9 FPD_B8 FPD_B6 FPD_B7 FPD_G3 FPD_R9 FPD_R5 FPD_R1 FPD_CK2_PWM0 VS_OUT BCL_SAF GOUT GND CVBS2_Y2_P R1_C1_PR1_N FB DENC_CVBS REFN_AFE_S VCC10P VCC25P VCC25P I2SO_LRCK SCL3 AD2 AD7 TIMER3_INT4 TS1_STR TS1_DIN3 TS2_DIN3 TS2_DIN2
GND GND I2SO_DAT0 SDA3 AD1 AD6 TIMER2_PWM5 TS1_VDAT TS1_DIN4 TS1_DIN0 TS2_STR TS2_DIN6 FPD_B0 FPD_G9 GND FPD_G5 FPD_G1 FPD_R7 FPD_R3 FPD_GFX_PWM1 HDRIVE VMEAS ICATH BLANKOUT C2_PR2_P CVBS1_Y1_PB2_P G1_CVBS1P_Y1P_N B1_PB1_P HCSYNC DENC_C SSCG_CKO XTALIN CLKXTM I2SO_DAT1 SPDIF_OUT AD0 AD5 GPIO3 SCL2 TS1_DIN5 TS1_DIN1 TS2_VDAT TS2_DIN7
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STD2000
STD2000
Package Mechanical Data
3
Package Mechanical Data
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Revision History
STD2000
4
Revision History
Date
1-Mar-2005 2-Jan 2006
Revision
1 2 Initial release
Changes
Small changes applied to block diagram, features, figures 2 and 3.
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STD2000
NOTES:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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