ST21Y144
Smar tcard MCU with 144 Kbytes High Density EEPROM
Data Brief
Feature summary
ST21Y144 major applications include:
Mobile communications (GSM and CDMA) Java applications
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Hardware features
Enhanced 8/16-bit CPU core with 16 MBytes linear addressable memory 400 Kbytes User ROM 8 Kbytes User RAM 144 Kbytes User EEPROM including 64 Bytes User OTP area: Highly reliable CMOS EEPROM submicron technology 10-year data retention 500,000 Erase/Write cycles endurance typical at 25C 1 to 64 Bytes Erase or Program in 1.5 ms Asynchronous Receiver Transmitter supporting ISO 7816-3 T=0 and T=1 protocols Two 8-bit timers with interrupt capability 1.8V, 3V and 5V supply voltage ranges External clock frequency from 1 up to 7.5 MHz High performance provided by: CPU clock frequency up to 22 MHz External clock multiplier (2x, 3x, and 4x) Current consumption complies with GSM specifications Power-saving Standby mode Contact assignment compatible ISO 7816-2 ESD protection greater than 4 kV (HBM)
Micromodule
Wafer
Security features
Monitoring of environmental parameters Protection against faults ISO 3309 CRC calculation block Cryptographic performances(1): Triple DES (with keys loaded): 9.3 s Single DES (with keys loaded): 3.1 s True Random Number Generator Unique serial number on each die Hardware DES accelerator
Development environment
Software development and firmware generation are supported by a comprehensive set of development tools dedicated to software design and validation.
1. Typical values at 22 MHz
March 2007
Rev 2
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Description
ST21Y144
1
Description
The ST21Y144 product is a serial access microcontroller specially designed for costeffective secure mobile applications. It is based on an enhanced STMicroelectronics 8/16-bit CPU core offering 16 MBytes linear addressing space. It is manufactured using an advanced highly reliable ST CMOS EEPROM technology. The device includes a DES accelerator. A serial interface fully compatible with the ISO 7816-3 standard (T = 0 and T = 1) for Smartcard applications is available. A CRC calculation block is also available and is directly accessible by the User. The product architecture is optimized for low power consumption applications. A flexible clock generator module provides increased performance for specific current requirements. Figure 1. Block diagram
RAM
EEPROM
ROM
DES Accelerator
Internal Bus
CRC Module
Clock Generator Module CLK
2x 8-bit timers
Security Administrator
True Random Number Generator Vcc
8/16-bit CPU Core
IART
RESET
GND
I/O
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Revision history
1.1
Development environment
Development tools for smartcard products include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you to develop and debug your application and evaluate smartcard products and their peripherals. An Integrated Development Environment (IDE), the STMicroelectronics Visual Debug (STVD), provides a set of tools for developing embedded applications. This interface manages the project configuration, code edition, code generation and program debugging. An emulator (SCICS) and a simulator are available for developing and validating your application code. All the information needed to generate the application code and personalization will be collected in a delivery file (.DLV extension). This file is created using the Delivery menu of the STMicroelectronics configuration software tool, SCOOL.
2
Revision history
Table 1.
Date 23-Jan-2007 20-Mar-2007
Document revision history
Revision 1 2 Initial release. Updated Erase/Write cycles endurance value and Section 1.1: Development environment on page 3. Changes
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ST21Y144
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