STEVAL-MKI005V1
MEMS 3-axis 2g/6g digital output low voltage linear accelerometer evaluation board based on the LIS3LV02DL
Data Brief
Features
Graphical user interface USB connector Control switches MEMS sensor LED indicators ST7-USB microcontroller
Description
The STEVAL-MKI005V1 is an evaluation kit designed to provide the user with a complete, ready-to-use platform for evaluation of the LIS3LV02DL, a low power 3-axis linear accelerometer with digital output. The device includes a sensing element and an IC interface capable of translating information from the sensing element into a measured signal that can be used for external applications. In addition to the MEMS sensor, the evaluation board utilizes an ST7-USB microcontroller which functions as a bridge between the sensor and the PC, on which it is possible to use the graphical user interface (GUI) included with the kit or dedicated software routines for customized applications.
STEVAL-MKI005V1
Januar y 2008
Rev 1
1/4
www.st.com 4
For further information contact your local STMicroelectronics sales office.
1
cs_pad
sck V ddf
mosi
mi so
da a_re dy t a
5
6
3
2
RD Y/ I NT
Circuit schematic
nc CK
GND
SCL/ SPC
7 8 D4 R G
V dd_I O
SD O
USB_B
R2 100R
CS
1 V+ 2 DM 3 DP 4 GND Vddf C5 100n R3 100R
4
C1 10u +
C4 C2 100n 4u7
1
SD A/ SDI / SDO
res
V dd
res
V dd
9
12
13
10
oscout osci n
i ccdata i cccl k
nRsel ET i ccES
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
U2 ST7265X_TQFP64 Gled Rled
R6 1k 5 Yoscm1 Cosc1 33p 12MH z Cosc2 33p
Vddf
OSCOU T OSCI N V ss2 V ssa V dda V dd2 I CCD AT A I CCCL K U SBEN A I N1 A I N0 SD A SCL RES T E V pp/I CCSEL PWM 1
osci n
oscout
Rled Gled
C8 47n
C9
+ C10
220n
PB6 PB7 PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PA 6 PA 7 SS M I SO M OSI SCK V dd1 V ss1
10u
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UV ss UD M UD P UV cc UV dd Vddf Vssf PE5 PE6 PE7 PB0 PB1 PB2 PB3 PB4 PB5 PWM 0 AI N6 AI N5 AI N4 AI N3 AI N2 OCM P2 OCM P1 PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4
48 47 46 45 44 43 42 41 40 39 38 37 36 CS1 35 CS2 34 33 cs_pad
VCC
17 18 19 20 21 22 da a_re dy 23 t a 24 25 26 27 28 29 30 31 32
V ddf mi so mosi sck
C3 4u7 C6 100n
+
J2 iccdata icccl k nRESET iccsel
sck mi so mosi da a_re dy t a cs_pad
R7 10K
CS2 CS1
R8 10K
VCC
1 3 5 7 9 I CP TP1
2 4 6 8 10
Riccsel1 10k
SW1 NReset
11
14
GND
STEVAL-MKI005V1
J3 SPI
7 6 5 4 3 2 1
2/4
Circuit schematic
Figure 1.
D1 R5 100R
R1 180R D3
J1
VCC
U1 LI S3LV02DL
+
GND res
16 15
Circuit schematic
C7 100n
SW2
SW3
STEVAL-MKI005V1
Revision history
2
Revision history
Table 1.
Date 17-Jan-2008
Document revision history
Revision 1 Initial release Changes
3/4
STEVAL-MKI005V1
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