STEVAL-TDR005V1
RF power amplifier using 2 x SD2943 N-channel enhancement-mode lateral MOSFETs
Features
Excellent thermal stability Frequency: 1.8 - 54 MHz Supply voltage: 48 V Output power: 450 W typ. Input power 10 W max. Efficiency: 55 % - 76 % IMD at 300 WPEP < -24 dBc Load mismatch: 3:1 all phases
Description
The STEVAL-TDR005V1 is a RF broadband power amplifier intended for linear or nonlinear operation over the band 1.8 to 54 MHz using 2x SD2943 gold metallized N-channel MOS fieldeffect transistors. The temperature compensating biasing circuit supports class B and class AB operation. STEVAL-TDR005V1 is designed in cooperation with specific RF devices. Table 1. Device summary
Order code STEVAL-TDR005V1
July 2008
Rev 1
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Contents
STEVAL-TDR005V1
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 3 4 5 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Photos of STEVAL-TDR005V1 amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 6 STEVAL-TDR005V1 class of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SD2943 mounting recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.1 6.2 Mounting recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mounting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STEVAL-TDR005V1
Electrical data
1
1.1
Electrical data
Maximum ratings
Table 2.
Symbol PIN POUT VDD
(1)
Absolute maximum ratings
Parameter Input power Output power Drain supply voltage Gate biasing voltage Drain current Power dissipation Value 16 500 50 15 20 400 Unit W W V V A W
VGG IDD PDISS
1. VGG from 9 to 15 V and PIN < 16 W
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Electrical characteristics
STEVAL-TDR005V1
2
Electrical characteristics
TA = +25 oC, VDD = 48 V, IDQ = 2 x 900 mA Table 3.
Symbol Freq. POUT Gain ND H2 H3 VSWR
Electrical specification
Test Conditions Frequency range PIN = 10 W PIN = 10 W PIN = 10 W 2
ND
Min 1.8 350
Typ
Max 54
Unit MHz W dB % dBc dBc
450 16.6 0.6 dB 55 - 76 -24 / -49 -15 / -58 3:1
Harmonic @ POUT = 300 W
3RD Harmonic @ POUT = 300 W Load mismatch all phases @ POUT = 300 W
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STEVAL-TDR005V1
Typical performance
3
Figure 1.
Typical performance
Output power vs frequency Figure 2. Output power vs frequency
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Photos of STEVAL-TDR005V1 amplifier
STEVAL-TDR005V1
4
Photos of STEVAL-TDR005V1 amplifier
Figure 3. Top view
Figure 4.
Side view
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STEVAL-TDR005V1
STEVAL-TDR005V1 class of operation
5
STEVAL-TDR005V1 class of operation
Class B: a low bias point with ~100 mA per transistor Class AB: a higher bias point with ~ 900 mA per transistor The bias point is 2x 100 mA if "BIAS" is left open and in this case a DC voltage of ~5 V is present The bias point is 2 x 900 mA if "BIAS" is connected to ground. To switch-on biasing circuit, connect "PA_ON" to ground. To switch-off biasing circuit, left open "PA_ON"
To select a bias point, STEVAL-TDR005V1 has a control port "BIAS".
"PA_ON" control port / ON-OFF bias current
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SD2943 mounting recommendations
STEVAL-TDR005V1
6
6.1
SD2943 mounting recommendations
Mounting recommendations
Ensure holes in heatsinks are free from burrs; Minimum depth of tapped holes in heatsinks is 6 mm; Use 4-40 UNC-2A cheese-head screws with a flat washer to spread the joint pressure; The minimum flatness of the mounting area is 0.02 mm; Mounting area roughness should be less than 0.5 m (micro); Avoid, as much as possible, use of flux or flux solutions because flux can penetrate even when hermetically sealed ceramic-capped transistors. Tin and wash the printedcircuit board BEFORE mounting the power transistors, then solder the transistor leads without using flux; Transistor leads may be tinned by dipping them full-length into a solder bath at a temperature of about 230 C. No flux should be used during tinning; Recommended heatsink compounds: WPSII (silicon free) from austerlitz electronics, 340 from down corning etc.
6.2
Mounting sequence
Apply a thin layer of evenly distributed heatsink compound to the flange; Position the device with flat washers in place; Tighten the screws until finger tight (0.05 Nm); Fur ther tighten the screws until the specified torque is reached; For M174, M177 and M244 type of packages, torque should be minimum 0.6 Nm and 0.75 Nm max.
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STEVAL-TDR005V1
SD2943 mounting recommendations
Table 4.
DMOS packages - list of materials
Ceramic insulator BeO (99.5% min) Plating Leads Flange Torque (Nm) Min Ma x
Package Description Flange Leadframe Type 0.500 DIA 4L NON HERM W/FLANGE ALLOY 42 (Fe58 / Ni42)
M174
Cu
Au (100 min) over Ni(100 min) + Pd Ni (100 min / (10 min) 350 max)
0.6
0.75
M174 (Moly disk)
0.500 DIA 4L NON HERM Cu-MoW/FLANGE Cu (MOLY DISK) 0.550 DIA 4L NON Cu-MoHERM Cu W/FLANGE 2x W 0.400x0.425 (85%) WIDE 2L Cu LAP N/H (15%) FLANGE
ALLOY 42 (Fe58 / Ni42)
BeO (99.5% min)
Au (100 min) over Ni(100 min) + Pd Ni (100 min / (10 min) 350 max)
0.6
0.75
M177
ALLOY 42 (Fe58 / Ni42)
BeO (99.5% min)
Au (60 min) over Ni (100 min / 350 max)
Au (100 min) over Ni (100 min / 350 max)
0.6
0.75
M244
ALLOY 42 (Fe58 / Ni42)
BeO (99.5% min)
Au (60 min) over Ni (100 min / 350 max)
Au (60 min) over Ni (100 min / 350 max)
0.6
0.75
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Package mechanical data
STEVAL-TDR005V1
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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STEVAL-TDR005V1
Revision history
8
Revision history
Table 5.
Date 01-Jul-2008
Document revision history
Revision 1 Initial release Changes
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STEVAL-TDR005V1
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