STM32TS60
Multi-touch screen controller device using a digital resistive touchpanel with I²C, SPI, UART and USB interfaces
Data brief
Features
FBGA
Patented digital resistive multi-touchpanel technology powered by PmatrixTM firmware engine Able to track up to 10 independent touches simultaneously Finger, nail and any stylus touch capability Up to 0.17 mm resolution Touch actuation force information No calibration requirements Typical touchpanel scan rate of 125 Hz up to 250 Hz Single- or dual-chip architecture able to support up to 10.1" screens Single-chip controller able to support up to 129 rows/columns coming from the sensor matrix. Embedded compensation resistors for reduced BOM and easy connection to the touchpanel I2C, SPI, UART and USB communication interfaces Very low power mode allowing "wakeup on touch/release" mode Wakeup response time: 10 s from Sleep mode and 100 s from Standby mode STM32TS60 device summary
Feature Description 2.5" to 6" (single-chip) / 6" to 10.1" (dual-chip) Up to 129 rows and columns with a maximum of 64 rows and 81 columns (see main architectures in Section 3) I²C, SPI, UART and USB 2.4 to 3.6 V -40 C to +85 C UFBGA 144 (7 x 7 mm, 0.5 pitch) ECOPACK package
UFBGA144 (7 x 7 mm)
Applications
Gaming devices Mobile handsets Smart phones Portable media players Personal navigation devices Mobile internet devices Netbooks
Table 1.
Touchpanel size Columns, rows Interface Supply voltage range Max. temperature range Package
Februar y 2010
Doc ID 16925 Rev 2
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www.st.com 1
For further information contact your local STMicroelectronics sales office.
Contents
STM32TS60
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 1.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Main benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 3 4 5 6
Ballout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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STM32TS60
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. STM32TS60 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32TS60 single-chip pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STM32TS60 dual-chip pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Single-chip typical application passive component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Dual-chip typical application passive component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 UFBGA144 - 7 x 7 mm ultra low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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List of figures
STM32TS60
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. STM32TS60 single-chip UFBGA144 ballout top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM32TS60 dual-chip (master) UFBGA144 ballout top view. . . . . . . . . . . . . . . . . . . . . . . . 7 STM32TS60 dual-chip (slave) device UFBGA144 ballout top view . . . . . . . . . . . . . . . . . . . 8 Single-chip typical application schematic for 2.5" to 6" panels . . . . . . . . . . . . . . . . . . . . . . 20 Dual-chip typical application schematic for 6" to 10.1" panels . . . . . . . . . . . . . . . . . . . . . . 21 UFBGA144 - 7 x 7 mm ultra low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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STM32TS60
Description
1
1.1
Description
Device overview
The STM32TS60 product is a multitouch controller device based on Stantum's patented digital resistive multitouch technology. This technology employs the connectivity power of the universal serial bus (USB) with CortexTM-M3 processors and ARM architecture. Conventional resistive touch controllers are unable to detect more than one contact at a time. Thanks to the STM32TS60 device, it is possible to detect and track up to ten contacts over a touchpanel. The STM32TS60 delivers an exact image of what is happening on the touchpanel surface in the most reliable way with very fast response time and with high noise immunity performances. The STM32TS60 represents a breakthrough over competing technologies, bringing outstanding multitouch performance with the best power budget. The resistive technology does not require any panel scan during Standby. Consequently, the STM32TS60 device has very low standby power consumption. In addition, this device benefits from the industry-leading mW/MIPS power performance of the ARM Cortex-M3 core.
1.2
Main benefits
Unique resistive true multitouch technology with up to 10 touches at a time Finger, nail and any stylus touch capability Fingers actuation force detection based on linear measurement of the touch area surface variation High responsiveness with low power consumption (at standby, near zero consumption) Homogeneous sensitivity on all points of the touchpanel area No calibration IP protected by solid patents based on proven resistive technology with very powerful EMI (electromagnetic insulation). Very low power Standby mode and zero power resistive panel Panel adapted from the proven high-volume resistive technology; able to reach high durability and 90 % transparency.
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Ballout and pin description
STM32TS60
2
Figure 1.
Ballout and pin description
STM32TS60 single-chip UFBGA144 ballout top view
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STM32TS60 Figure 2.
Ballout and pin description STM32TS60 dual-chip (master) UFBGA144 ballout top view
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Ballout and pin description Figure 3. STM32TS60 dual-chip (slave) device UFBGA144 ballout top view
STM32TS60
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STM32TS60 Table 2.
PIn no. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3
Ballout and pin description STM32TS60 single-chip pin definitions
PIn level(2) Pin name PI6/COL PI12/COL PI14/COL PI3/COL PG6/COL VDD_1 VSS_1 PA0/SPI_NSS/WAKEUP PF1/COL/ROW PF3/COL/ROW PF5/COL/ROW PF7/COL/ROW PI15/COL PI0/COL PI5/COL PI4/COL PG8/COL PA12/COL/OSC_OUT FT PA5/USBPU PA2/USBDM PF9/COL/ROW PF13/COL/ROW PF11/COL/ROW PF12/COL/ROW PI13/COL PI7/COL PI8/COL Pin function Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Supply voltage pin 1 Ground pin 1 SPI slave select from host Wakeup from host Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column 16 MHz crystal/resonator oscillator output USB pull-up USB dataTouchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel column Touchpanel column
PIn type(1) O O O O O S S I IO IO IO IO O O O O O O O IO IO IO IO IO O O O
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Ballout and pin description Table 2.
PIn no. C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7
STM32TS60
STM32TS60 single-chip pin definitions (continued)
PIn level(2) Pin name PI10/COL PC12/ROW PA11/COL/OSC_IN FT PA8/NCHG PA6/LED/DBG PA1/USBDP PF15/COL/ROW PF10/COL/ROW PF8/COL/ROW PI1/COL PI2/COL PI9/COL PI11/COL PB6/COL PA7/SPI_SI/UART_RX FT PA3/SPI_CLK/I2C_SCL PA4/SPI_SO/I2C_SDA/UAR T_TX PB8/COL PF6/COL/ROW PF0/COL/ROW PF4/COL/ROW PE0/ROW PE4/ROW PE6/ROW PE5/ROW PB9/COL Pin function Touchpanel column Touchpanel row Touchpanel column 16 MHz crystal/resonator oscillator input NCHG (pull-up required) Device activity LED Debug output USB data+ Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column SPI slave in from host UART data receive from host SPI clock input from host I2C clock from/to host SPI slave out to host I2C data from/to host UART data transmit to host Touchpanel column Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel column
PIn type(1) O IO O I OD IO IO IO IO O O O O O I/I I/OD
D8 D9 D10 D11 D12 E1 E2 E3 E4 E5
O/OD/O O IO IO IO IO IO IO IO O
FT
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STM32TS60 Table 2.
PIn no. E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2
Ballout and pin description STM32TS60 single-chip pin definitions (continued)
PIn level(2) Pin name PC0/ROW PC1/ROW PG0/COL PA10/COL PB1/COL PF2/COL/ROW PF14/COL/ROW PE8/ROW PE1/ROW PE2/ROW PE3/ROW PC2/ROW PC11/ROW PC9/ROW PG11/COL PG13/COL PB7/COL PG10/COL PG12/COL PE11/ROW PE12/ROW PE10/ROW PE9/ROW PC3/ROW BOOT0 PA9/COL PB0/COL PB2/COL PG14/COL PG4/COL PG15/COL PE15/ROW PE13/ROW Pin function Touchpanel row Touchpanel row Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Boot mode selection Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row
PIn type(1) IO IO O O O IO IO IO IO IO IO IO IO IO O O O O O IO IO IO IO IO I O O O O O O IO IO
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Ballout and pin description Table 2.
PIn no. H3 H4 H5 H6
STM32TS60
STM32TS60 single-chip pin definitions (continued)
PIn level(2) Pin name PE14/ROW PE7/ROW PC4/ROW PA14/COL/JTCK/SWCLK Pin function Touchpanel row Touchpanel row Touchpanel row Touchpanel column JTAG clock Serial wire clock Touchpanel column JTAG mode selection Serial wire data input/output Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel column JTAG reset Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Reset (active low) Touchpanel column JTAG data output
PIn type(1) IO IO IO O/I/I
H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 K8
O/I/OD O O O O O IO IO IO IO IO IO O/I O O O O O IO IO IO IO IO IO I O/OD
PA13/COL/JTMS/SWDIO PG2/COL PG3/COL PG7/COL PG5/COL PG9/COL PD3/ROW PD4/ROW PD2/ROW PD1/ROW PC5/ROW PC10/ROW PB4/COL/JTRST PG1/COL PH13/COL PH7/COL PH2/COL PH14/COL PD5/ROW PD0/ROW PD7/ROW PD9/ROW PC6/ROW PC13/ROW NRST PB3/COL/JTDO
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STM32TS60 Table 2.
PIn no. K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
Ballout and pin description STM32TS60 single-chip pin definitions (continued)
PIn level(2) Pin name PH8/COL PH9/COL PH11/COL PH15/COL PD6/ROW PD11/ROW PD12/ROW PD14/ROW PC8/ROW PC15/ROW PC14/ROW PA15/COL/JTDI PH0/COL PH10/COL PH4/COL PH12/COL PD8/ROW PD10/ROW PD13/ROW PD15/ROW PC7/ROW VDD_2 VSS_2 PB5/COL PH1/COL PH5/COL PH6/COL PH3/COL Pin function Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel column JTAG data input Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Supply voltage pin 2 Ground pin 2 Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column
PIn type(1) O O O O IO IO IO IO IO IO IO O/I O O O O IO IO IO IO IO S S O O O O O
1. I = input pin, O = output push-pull pin, IO = input/output pin, OD = output open drain pin, S = supply pin. 2. FT = 5 V tolerant
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Ballout and pin description Table 3.
PIn no. A1 A2 A3 A4 A5 A6 A7
STM32TS60
STM32TS60 dual-chip pin definitions
PIn level(2) Master (M) or slave (S) device M/S M/S M/S M/S M/S M/S M/S M Pin name PI6/COL PI12/COL PI14/COL PI3/COL PG6/COL VDD_1 VSS_1 PA0/SPI1_NSS/WAKEUP PA0/SPI2_NSS(3) PF1/COL/ROW PF3/COL/ROW PF5/COL/ROW PF7/COL/ROW PI15/COL PI0/COL PI5/COL PI4/COL PG8/COL PA12/COL/OSC_OUT Pin function Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Supply voltage pin 1 Ground pin 1 SPI slave select from host Wakeup from host Interdevice SPI slave select Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column 16 MHz crystal/resonator oscillator output
PIn type(1) O O O O O S S
A8
I S
A9 A10 A11 A12 B1 B2 B3 B4 B5
IO IO IO IO O O O O O
M/S M/S M/S M/S M/S M/S M/S M/S M/S M
B6
O S PA12/COL PA5/SPI2_CLK(3) PA2/USBDM PA2 PF9/COL/ROW PF13/COL/ROW Touchpanel column Interdevice SPI clock USB dataNot used Touchpanel column Touchpanel row Touchpanel column Touchpanel row
B7 B8
O IO
FT
M/S M S
B9 B10
IO IO
M/S M/S
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STM32TS60 Table 3.
PIn no. B11 B12 C1 C2 C3 C4 C5
Ballout and pin description STM32TS60 dual-chip pin definitions (continued)
PIn level(2) Master (M) or slave (S) device M/S M/S M/S M/S M/S M/S M/S M Pin name Pin function Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel column 16 MHz crystal/resonator oscillator input
PIn type(1) IO IO O O O O IO
PF11/COL/ROW PF12/COL/ROW PI13/COL PI7/COL PI8/COL PI10/COL PC12/ROW PA11/COL/OSC_IN
C6
O S PA11/COL Touchpanel column NCHG (pullup required) Debug output Debug output Interdevice SPI master in/slave out USB data+ Not used Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column SPI slave in from host UART data receive from host Not used
M C7 I FT S C8 C9 OD IO S C10 C11 C12 D1 D2 D3 D4 D5 IO IO IO O O O O O M/S M/S M/S M/S M/S M/S M/S M/S M D6 I/I S M/S M
PA8/NCHG/DBG PA8/DBG PA6/SPI2_MISO(3) PA1/USBDP PA1 PF15/COL/ROW PF10/COL/ROW PF8/COL/ROW PI1/COL PI2/COL PI9/COL PI11/COL PB6/COL PA7/SPI1_SI/UART_RX PA7
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Ballout and pin description Table 3.
PIn no.
STM32TS60
STM32TS60 dual-chip pin definitions (continued)
PIn level(2) Master (M) or slave (S) device M Pin name Pin function SPI clock input from host I2C clock from/to host Not used SPI slave out to host I2C data from/to host UART data transmit to host Not used Touchpanel column Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel column Touchpanel row Touchpanel row Touchpanel column Interdevice SPI master out/slave in Touchpanel column Touchpanel column Touchpanel row Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row
PIn type(1)
PA3/SPI1_CLK/I2C_SCL PA3 PA4/SPI1_SO/I2C_SDA/U ART_TX
D7
I/OD
FT S
M D8 O/OD/O FT S D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 O IO IO IO IO IO IO IO O IO IO O O O IO IO IO IO IO IO IO IO M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S
PA4 PB8/COL PF6/COL/ROW PF0/COL/ROW PF4/COL/ROW PE0/ROW PE4/ROW PE6/ROW PE5/ROW PB9/COL PC0/ROW PC1/ROW PG0/COL PA10/SPI2_MOSI(3) PB1/COL PF2/COL/ROW PF14/COL/ROW PE8/ROW PE1/ROW PE2/ROW PE3/ROW PC2/ROW PC11/ROW
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STM32TS60 Table 3.
PIn no. F7 F8 F9 F10 F11 F12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6
Ballout and pin description STM32TS60 dual-chip pin definitions (continued)
PIn level(2) Master (M) or slave (S) device M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M /S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/ S Pin name PC9/ROW PG11/COL PG13/COL PB7/COL PG10/COL PG12/COL PE11/ROW PE12/ROW PE10/ROW PE9/ROW PC3/ROW BOOT0 PA9/USBPU PB0/COL PB2/COL PG14/COL PG4/COL PG15/COL PE15/ROW PE13/ROW PE14/ROW PE7/ROW PC4/ROW PA14/COL/JTCK/SWCLK Pin function Touchpanel row Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Boot mode selection USB pullup Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel column JTAG clock Serial wire clock Touchpanel column JTAG mode selection Serial wire data input/output Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row
PIn type(1) IO O O O O O IO IO IO IO IO I O O O O O O IO IO IO IO IO O/I/I
H7 H8 H9 H10 H11 H12 J1
O/I/OD O O O O O IO
M/ S M/S M/S M/S M/S M/S M/S
PA13/COL/JTMS/SWDIO PG2/COL PG3/COL PG7/COL PG5/COL PG9/COL PD3/ROW
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Ballout and pin description Table 3.
PIn no. J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7
STM32TS60
STM32TS60 dual-chip pin definitions (continued)
PIn level(2) Master (M) or slave (S) device M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S Pin name PD4/ROW PD2/ROW PD1/ROW PC5/ROW PC10/ROW PB4/COL/JTRST PG1/COL PH13/COL PH7/COL PH2/COL PH14/COL PD5/ROW PD0/ROW PD7/ROW PD9/ROW PC6/ROW PC13/ROW NRST PB3/COL/JTDO PH8/COL PH9/COL PH11/COL PH15/COL PD6/ROW PD11/ROW PD12/ROW PD14/ROW PC8/ROW PC15/ROW PC14/ROW Pin function Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel column JTAG reset Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Reset (active low) Touchpanel column JTAG data output Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row
PIn type(1) IO IO IO IO IO O/I O O O O O IO IO IO IO IO IO I O/OD O O O O IO IO IO IO IO IO IO
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STM32TS60 Table 3.
PIn no.
Ballout and pin description STM32TS60 dual-chip pin definitions (continued)
PIn level(2) Master (M) or slave (S) device M Pin name Pin function Interdevice SPI slave select JTAG data input Touchpanel column JTAG data input Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel row Touchpanel row Touchpanel row Touchpanel row Touchpanel row Supply voltage pin 2 Ground pin 2 Touchpanel column Touchpanel column Touchpanel column Touchpanel column Touchpanel column
PIn type(1)
PA15/SPI2_NSS(3)/JTDI PA15/COL/JTDI PH0/COL PH10/COL PH4/COL PH12/COL PD8/ROW PD10/ROW PD13/ROW PD15/ROW PC7/ROW VDD_2 VSS_2 PB5/COL PH1/COL PH5/COL PH6/COL PH3/COL
L8
O/I S
L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
O O O O IO IO IO IO IO S S O O O O O
M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S M/S
1. I = input pin, O = output push-pull pin, IO = input/output pin, OD = output open drain pin, S = supply pin. 2. FT = 5 V tolerant 3. The SPI2 is used to interconnect devices in multichip architecture solutions.
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Application diagrams
STM32TS60
3
Application diagrams
Figure 4. Single-chip typical application schematic for 2.5" to 6" panels
HOST CONTROLLER
SPI, I2C or UART VDD R4 R3 R2 R5
USB VDD R6
C6 USB_PU SPI_SO/I2C_SDA/UART_TX SPI_SCK/I2C_SCL SPI_SI/UART_RX DEV TOOLS X1 OSC_OUT SWDIO SWCLK OSC_IN SPI_NSS USB_DM USB_DP NCHG NRST VDD1 VDD2
R1 C1 C2
C3 VSS1 VSS2 ROW COL BOOT0
C4
C5
TOUCHPANEL 2.5" ~ 6"
1. In single-chip architecture, up to 129 touchpanel signals are available, including a maximum of 81 columns and 64 rows.
Table 4.
Ref. C1,C2 X1 R1 R2 R3,R4
Single-chip typical application passive component list
Typ. Value
(1)
Comment For USB interface only
Ref. C3,C4 C5 C6 R5
Typ. value
Comment
100 nF Decoupling capacitors 1 F Filtering capacitors 10 nF Reset filter 1.5 K For USB interface only 10 K Reset filter
16 MHz For USB interface only
(1)
For USB interface only
10 K 4.7 K For I
2C
interface only
R6
1. Value depends on resonator or crystal characteristics.
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Doc ID 16925 Rev 2
STM32TS60 Figure 5.
Application diagrams Dual-chip typical application schematic for 6" to 10.1" panels
HOST CONTROLLER
SPI, I2C or UART VDD R4 R3 R2 R5
USB VDD R6
C6 DEV TOOLS X1 OSC_OUT C3 VSS1 SPI2_MOSI SPI2_MISO SPI2_NSS SPI2_SCK VSS2 ROW COL BOOT0 SWDIO SWCLK OSC_IN STM32TS60 "MASTER" NRST VDD1 VDD2
R1 C1 C2
C4
C5
TOUCHPANEL 6" ~ 10.1" Sub-panel #1 Sub-panel #2
ROW
SPI2_MOSI
DEV TOOLS
SPI2_MISO
SPI2_NSS
SPI2_SCK
VDD1 VDD2
NRST
COL
VDD
C3' STM32TS60 "SLAVE" VSS1 VSS2 BOOT0
C4'
C5'
1. In dual-chip architecture, up to 124 touchpanel signals are available on master devices, including a maximum of 76 columns and 64 rows. On the slave side, up to 128 touchpanel signals are available, including a maximum of 80 columns and 64 rows.
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Application diagrams Table 5.
Ref. C1,C2 X1 R1 R2 R3,R4
STM32TS60 Dual-chip typical application passive component list
Typ. value
(1)
Comment For USB interface only
Ref. C3,C4,C3',C4' C5, C5' C6 R5
Typ. value
Comment
100 nF Decoupling capacitors 1 F 10 nF Filtering capacitors Reset filter
16 MHz For USB interface only
(1)
For USB interface only
10K 4.7K For I2C interface only
1.5 K For USB interface only 10 K Reset filter
R6
1. Value depends on resonator or crystal characteristics.
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Doc ID 16925 Rev 2
STM32TS60
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark. Figure 6. UFBGA144 - 7 x 7 mm ultra low profile fine pitch ball grid array package out line
Z
Seating plane A2 A4 A3 A A1 ddd Z
X D D1 e Ball A1 F Y
A F
E1 E
e
M
Øb
(144 balls) Ø eee M Z Ø fff M Z Y X
A0AS_ME
1. Drawing is not to scale.
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Package mechanical data Table 6.
STM32TS60
UFBGA144 - 7 x 7 mm ultra low profile fine pitch ball grid array package mechanical data
millimeters inches(1) Max 0.600 0.100 0.500 0.180 0.370 0.300 7.050 5.550 7.050 5.550 0.550 0.800 Typ 0.0209 0.0031 0.0177 0.0051 0.0126 0.0098 0.2756 0.2165 0.2756 0.2165 0.0197 0.0295 Min 0.0181 0.0024 0.0157 0.0031 0.0106 0.0079 0.2736 0.2146 0.2736 0.2146 0.0177 0.0276 0.0039 0.0059 0.0020 Max 0.0236 0.0039 0.0197 0.0071 0.0146 0.0118 0.2776 0.2185 0.2776 0.2185 0.0217 0.0315
Symbol Typ A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 0.530 0.080 0.450 0.130 0.320 0.250 7.000 5.500 7.000 5.500 0.500 0.750 Min 0.460 0.060 0.400 0.080 0.270 0.200 6.950 5.450 6.950 5.450 0.450 0.700 0.100 0.150 0.050
1. Values in inches are converted from mm and rounded to four decimal digits.
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Doc ID 16925 Rev 2
STM32TS60
Ordering information
5
Ordering information
Table 7.
Example: Device family STM32 = ARM-based 32-bit microcontroller Device sub-family TS = touchscreen family Touch sensing technology 60 = multitouch resistive Pin count Z = 144 pins Package H = UFBGA Temperature range 6 = industrial temperature range 40C to 85C Firmware configuration Firmware revision
Ordering information scheme
STM32 TS 60 Z H 6 xx y
For further information on any aspect of this device, please contact your nearest ST Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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Revision history
STM32TS60
6
Revision history
Table 8.
Date 16-Dec-2009
Document revision history
Revision 1 Initial release Updated Table 1: STM32TS60 device summary. Updated Figure 1 and added Figure 2 and Figure 3 ballouts. Replaced Table 2: STM32TS60 single-chip pin definitions. Added Table 3: STM32TS60 dual-chip pin definitions. Figure 4: Single-chip typical application schematic for 2.5" to 6" panels: updated title and pins; added footnote. Figure 5: Dual-chip typical application schematic for 6" to 10.1" panels: updated title, added SPI2_NSS pin, and added footnote. Passive component list Table 4 and Table 5: updated title and footnotes. Added Section 4: Package mechanical data. Renamed Section 5: Ordering information. Changes
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Doc ID 16925 Rev 2
STM32TS60
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