LNBEH21
LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
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C OMPLETE INTERFACE BETWEEN LNB AND I2CTM BUS BUILT-IN DC/DC CONTROLLER FOR SINGLE 12V SUPPLY OPERATION AND HIGH EFFICIENCY (Typ. 94% @ 750mA) TWO SELECTABLE OUTPUT CURRENT LIMIT (450mA / 750mA) ACCUR ATE BUILT-IN 22KHz TONE OSCILLATOR SUITS WIDELY ACCEPTED STANDARDS FAST OSCILLATOR START-UP FACILITATES DiSEqCTM ENCODING BUILT-IN 22KHz TONE DETECTOR SUPPORTS BI-DIRECTIONAL DiSEqCTM 2.0 13/18V CONTROL WORD COMMUNICATION SEMI-LOWDROP POST REGULATOR AND HIGH EFFICIENCY STEP-UP PWM FOR LOW POWER LOSS: Typ. 0.56W @ 125mA TWO OUTPUT PINS SUITABLE TO BYPASS THE OUTPUT R-L FILTER AND AVOID ANY TONE DISTORSION (R-L FILTER AS PER DiSEqC 2.0 SPECs, SEE APPLICATION CIRCUIT) C ABLE LENGTH DIGITAL COMPENSATION OVERLOAD AND OVER-TEMPERATURE INTERNAL PROTECTIONS I2C WITH DIAGNOSTIC BITs
PowerSO-20
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LNB SHORT CIRCUIT SOA PROTECTION WITH I2C DIAGNOSTIC BIT +/- 4KV ESD TOLERANT ON INPUT/ OUTPUT POWER PINS
BLOCK DIAGRAM
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DESCRIPTION Intended for analog and digital satellite STB receivers/SatTV, sets/PC cards, the LNBEH21 is a monolithic voltage regulator and interface IC, assembled in POWER SO-20, specifically designed to provide the 13/18V power supply and the 22KHz tone signalling to the LNB downconverter in the antenna or to the multiswitch box. The LNBEH21 supports both methods of communication currently used, 13/18V Control W ord Communication Mode and DiSEqCTM communication. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I2CTM standard interfacing.
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St ep-up PWM Co ntroller
Vup-Feedback
VoTX
VoRX
Pr eregul. + U. V.lockou t +P. ON res. Linear Post-reg +Modulator +Protections
ISEL E XTM
SDA S CL ADDR
V Select IČ C interf . Enable
22 KHz
Dia gnostics
O scill.
OM=low
T one Detector
DETIN DS QOUT
Tone control Echo-pu lses control
T RISE= TFALL = 500s
TEN/VSEL
13/18V control
OM=High
July 2004
Rev. 1
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LNBEH21
Table 1: Ordering Codes
TYPE LNBEH21 PowerSO-20 (Tube) LNBEH21PD PowerSO-20 (Tape & Reel) LNBEH21PD-TR
Table 2: Absolute Maximum Ratings
Symbol VCC VUP IO VOTX/RX VI VDETIN VOH IGATE VSENSE Tstg Top DC Input Voltage DC Input Voltage Output Current DC Output Pins Voltage Logic Input Voltage (SDA, SCL, DSQIN, ISEL) Detector Input Signal Amplitude Logic High Output Voltage (DSQOUT) Gate Current Current Sense Voltage Storage Temperature Range Operating Junction Temperature Range Parameter Value -0.3 to 16 -03 to 25 Internally Limited -0.3 to 25 -0.3 to 7 -0.3 to 2 -0.3 to 7 400 -0.3 to 1 -0.3 to 7 Unit V V mA V V VPP V V V
VADDRESS Address Pin Voltage
-40 to +150 -40 to +125
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
Table 3: Thermal Data
Symbol Rthj-case Parameter Thermal Resistance Junction-case
Figure 1: Pin Configuration (top view)
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Value 2
Unit C/W
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LNBEH21
Table 4: Pin Description
PIN N 18 17 16 19 SYMBOL VCC GATE SENSE V UP NAME Supply Input External Switch Gate Current Sense Input Step-up Voltage FUNCTION 8V to 15V IC supply. A 220F bypass capacitor to GND with a 470nF (ceramic) in parallel is recommended External MOS switch Gate connection of the step-up converter DC/DC Current Sense comparator input. Connected to current sensing resistor Input of the linear post-regulator. The voltage on this pin is monitored by internal step-ut controller to keep a minimum dropout across the linear pass transistor. RX Output to the LNB in DiSEqC 2.0 application. See truth tables for voltage selections and Communication Mode section for details. Bidirectional data from/to I2C bus. Clock from I2C bus. Depending on the value set for OM bit this pin enable/disable the internal 22KHz tone generator (OM=0) or switch the output voltage from 13V to 18V and vice versa (OM=1) 22kHz Tone Detector Input. Must be AC coupled to the DiSEqC 2.0 bus. Open drain output of the tone Detector to the main controller for DiSEqC 2.0 data decoding. It is set LOW when a 22 KHz tone is detected. External Modulation Input acts on VOTX. Needs DC decoupling to the AC source. If not used, can be left open. Pins connected to Ground. Also internally connected to the die frame (exposed pad) for heat dissipation. Needed for internal preregulator filtering Set high or floating for IO 750mA, connect to ground for IO 450mA. Output of the linear post-regulator/modulator to the LNB. See truth tables for voltage selections. Four I2C bus addresses available by setting the Address Pin level voltage. See address pin characteristics table.
2 12 13 14
VORX SDA SCL
Output Port during 22KHz Tone RX Serial Data Serial Clock
TEN/VSEL DiSEqC or 13/18V TTL Logic Input DETIN DSQOUT Tone Detector Input DiSEqC Output
9 15
5 1, 6, 10, 11, 20 8 3 4 7
EXTM GND BYP ISEL VOTX ADDR
External Modulator GROUND Bypass Capacitor Current Limit Select Output Port during 22KHz Tone TX Address Setting
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LNBEH21
TYPICAL APPLICATION CIRCUITS Figure 2: Application Circuit for DiSEqC 1.x and Output Current < 450 mA
Axi al Ferrite Bead Filter
F1 suggested part number:
MURATA BL01RN1-A62 Panasonic EXCELS A35
D 2 1N4001
IC1
F1
19 VUP ISEL 3
C2 220F I C2
C9 100F
ST S4DNFS30L
C3 (***) 470nF Ceramic
V oR X
2
Set TTX=1
C10(* **) 10n F
to LNB
17 GATE
Vo TX 4
LNBEH2 1
L1=22H
R sc 0. 1 C4 (***) 470nF Ceramic
18 VCC 16 SEN SE
D4(***) BAT 43 (**) DETIN 9
B yp
8 C5(***) 470nF
Vin 12V
C1 220F
12 SDA 13 SCL EXTM 5 ADD RESS 7
Tone T on e Enable / 13/18 Selection R1 3.3K
14 TEN/VS EL
GND
DSQ OUT 15
Figure 3: Full Application Circuit for Bi-directional DiSEqC 2.0 and Output Current up to 750mA
Axial Ferrite Bead Filter
F1 suggested part number: Mur ata BL01RN1-A62 Panasonic EXCELS-A35 F1 C2 220F D1 1N5821 or STPS3L40A
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L1=22H
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MOS S TN4NF03L
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C9 100F
C3(***) 470nF Ceramic
(s) t
IC1 Vu p Gate Sense
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V>3.3V
(or floating)
Current Limit Selection
Iou t<750mA Iou t<450mA
C8 (***) 100nF
D4 (***) BAT43 270H
to LNB
LNBEH21
(**) DETIN
C7 (***) 100nF
D3(***) BAT43
15 (*) see note
C6 10nF B yp Vcc C5 (***) 470nF
C1 220F
C4 (***) 470nF Ceramic
I2C Bus
Tone Tone Enable / 13/18 Selection
{
SD A SCL TEN/VSEL G ND
EXTM ADDRESS DSQOUT 0
R1 3.3K
(*) R-L Filter to be used according to EUTELSAT recommendation to implement the DiSEqCTM 2.0, (see DiSEqCTM implementation section). If bidirectional DiSEqCTM 2.0 is not implemented the R-L filter can be removed and the above DiSEqC 1.x circuit can be used. (**) Do not leave these pins floating if not used. (***) To be soldered as close as possible to relative pins. -C8 and D3,4 are needed only to protect the output pins from any negative voltage spikes during high speed voltage transitions.
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LNBEH21
APPLICATION INFORMATION This IC has a built in DC/DC Step-Up controller that, from a single supply source ranging from 8 to 15V, generates the input voltages (VUP) that let the linear post-regulator to work at a minimum dissipated power of 1.65W typ. @ 750mA load (the linear regulator drop voltage is internally kept at: VUP-VOUT=2.2V typ.). An UnderVoltage Lockout circuit will disable the whole circuit when the supplied VCC drops below a fixed threshold (6.7V typically). All the functions of this IC are controlled via I2CTM bus by writing 6 bits on the System Register (SR, 8 bits). The same register can be read back, and two bits will report the diagnostic status. When the IC is put in Stand-by (EN bit LOW), the power blocks are disabled. The LNBEH21 is compliant both with the DiSEqCTM 2.0 specification and with the 13/18V Control Word Communication Mode. The communication mode is selected by the "OM" I2CTM bit and, depending on the OM bit status, the TEN/VSEL pin function (see block diagram) is switched to control the 13/18V output voltage level or to enable the internal 22KHz tone generator when in DiSEqC mode. (refer to Communication Mode section for details). W hen the regulator blocks are active (EN bit = 1) and in DiSEqC mode (OM=0), the LNB output voltage can also be logic controlled to select 13V or 19.5V by mean of the VOM bit. The control of the VOM bit on the VUP voltage level depends on the OM bit status in order to allow the 13/18V Control Word Communication (see Communication Mode section). Additionally, it is possible to increment by 1V (Typ.) the selected output voltage value to compensate the excess voltage drop along the coaxial cable using the LLC SR bit (LLC=1). In order to improve design flexibility and to allow implementation of newcoming LNB remote control standards, an analogic modulation input pin is available (EXTM). An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. Also in this case, the VOTX output must be set ON during the tone transmission by setting the TTX bit High. When the external modulation is not used, the relevant pin can be left open. The current limitation block is SOA type and it is possible to select two current limit thresholds, by the dedicated ISEL pin. The higher threshold is in the range of 750mA to 1A if the ISEL is left floating or connected a voltage >3.3V. The lower threshold is in the range of 450mA to 700mA when the ISEL pin is connected to ground. When the output port is shorted to ground, the SOA current limitation block limits the short circuit current (ISC) at typically 300mA, to reduce the power dissipation. Moreover, it is possible to set the Short Circuit Current protection either statically (simple current clamp) or dynamically by the PCL bit of the I2C SR; when the PCL (Pulsed Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically, as soon as an overload is detected, the output is shut-down for a time TOFF, typically 900ms. Simultaneously the OLF bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time TON=1/10TOFF (typ.). At the end of Ton, if the overload is still detected, the protection circuit will cycle again through TOFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical TON+TOFF time is 990ms and it is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up in most conditions. However, there could be some cases in which an highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL=HIGH) and then switching to the dynamic mode (PCL=LOW) after a chosen amount of time. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns LOW when the overload condition is cleared. This IC is also protected against overheating: when the junction temperature exceeds 150C (typ.), the step-up converter and the linear regulator are shut off, and the OTF SR bit is set to HIGH. Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 135C (typ.).
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(*): External components are needed to comply to bi-directional DiSEqCTM bus hardware requirements. Full compliance of the whole application with DiSEqCTM specifications is not implied by the use of this IC.
I2C BUS INTERFACE Data transmission from main P to the LNBEH21 and vice versa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).
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LNBEH21
DA TA VALIDITY As shown in fig. 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. START AND STOP CONDITIONS As shown in fig. 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. BYTE FORMAT Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. A C K N OW L E D GE The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 6). The peripheral (LNBEH21) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBEH21 won't generate the acknowledge if the VCC supply is below the Undervoltage Lockout threshold (6.7V typ.) TRANSMISSION WITHOUT ACKNOWLEDGE Avoiding to detect the acknowledge of the LNBEH21, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 4: Data Validity On The I2C Bus
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Figure 5: Timing Diagram On I2C Bus
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LNBEH21
Figure 6: Acknowledge On I2C Bus
LNBEH21 SOFTWARE DESCRIPTION INTERFACE PROTOCOL The interface protocol comprises: - A start condition (S) - A chip address byte = hex 10 / 11 (the LSB bit determines read(=1)/write(=0) transmission) - A sequence of data (1 byte + acknowledge) - A stop condition (P)
CHIP ADDRESS MSB 0 LSB MSB R/W ACK
S
0
0
1
0
0
0
ACK= Acknowledge; S = Start; P = Stop; R/W = Read/Write
SYSTEM REGISTER (SR, 1 BYTE)
MS B R, W PCL R, W TTX R, W OM
R,W = read and write bit; R = Read-only bit All bits reset to 0 at Power-On
TRANSMITTED DATA (I2C BUS WRITE MODE) W hen the R/W bit in the chip address is set to 0, the main P can write on the System Register (SR) of the LNBEH21 via I2C bus. Only 6 bits out of the 8 available can be written by the P, since the remaining 2 are left to the diagnostic flags, and are read-only.
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LSB A CK P
R, W LLC
R, W VOM
R, W EN
R OTF
LSB R OLF
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LNBEH21
RECEIVED DATA (I2C bus READ MODE) The LNBEH21 can provide to the Master a copy of the SYSTEM REGISTER information via I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following master generated clocks bits, the LNBEH21 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: - acknowledge the reception, starting in this way the transmission of another byte from the LNBEH21; - no acknowledge, stopping the read mode communication. W hile the whole register is read back by the P, only the two read-only bits OLF and OTF convey diagnostic informations about the LNBEH21
PCL TTX OM LLC VOM EN OTF
0 These bits are read exactly the same as they were left after last write operation
Values are typical unless otherwise specified
OLF
Function
TJ<135C, normal operation TJ>150C, power block disabled
1 0 1
IOUTIOMAX, overload protection triggered
P O W E R - ON INTERFACE RESET The I2C interface built in the LNBEH21 is automatically reset at power-on. As long as the VCC stays below the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I2C command and the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the VCC rises above 7.3V typ, the I2C interface becomes operative and the SR can be configured by the main P. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the Power-On reset circuit. AD DRESS PIN Connecting this pin to GND the Chip I2C interface address is 0001000, but, it is possible to choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 11). COMMUNICATION MODE SELECTION
I2C
I2C OM bit (Operating Mode selection bit) The LNBEH21 can work either in DiSEqCTM mode or in 13/18V Control Word mode; the selection of the communication mode is achieved through the dedicated I2C OM bit that must be respectively set to LOW or to HIGH. Depending on the communication mode selection (OM bit state) the I2C VOM bit and the TEN/ VSEL pin (#14) operation are switched between two different functions: VOM bit and TEN/VSEL pin functions with OM=0 (DiSEqCTM mode). - The TEN/VSEL pin controls the 22KHz bursting code, by enabling the internal 22KHz tone generator, to allow immediate DiSEqCTM data encoding. - In DiSEqCTM mode, the VOM I2C bit controls simultaneously the post-regulator output voltage (VOUT) and the DC/DC converter output voltage (VUP). The VOM bit function is to select the LNB output voltage to 13.25V or 19.5V respectively if VOM=0 or VOM=1 (14.25V or 20.5V if LLC=1) and VUP is set to VOUT+2.2V typ., according to DiSEqC section in the Truth Table on page 11;
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LNBEH21
VOM bit and TEN/VSEL pin functions with OM=1 (13/18V Control Word mode). - When OM=1, the TEN/VSEL controls the 13/18V output voltage level. The usage of the TEN/VSEL pin in combination with the VOM bit allows the 13/18V Control Word Communication (see block diagram on page 1). The TEN/VSEL is a TTL control logic pin. - in 13/18V Control Word Communication mode, the VOM bit does not control the LNB output voltage but only forces the DC/DC Converter output voltage (VUP) in a steady state (VUP=21.7V typ. if LLC=0 and VUP=22.7V typ. if LLC=1). When OM=VOM=1, the LNB output voltage is controlled only by the TEN/VSEL pin. COMMUNICATION MODE IMPLEMENTATION DiSEqCTM 2.0 and 1.x mode, OM=0 W hen OM=0, the LNBEH21 is suitable both for DiSEqC 2.0 and for unidirectional DiSEqC 1.x applications. The bi-directional DiSEqC 2.0 protocol implementation is allowed by an easy PWK modulation/ demodulation of the 22KHz carrier. The PWK data are exchanged between the LNBEH21 and the main P, using logic levels that are compatible with both 3.3 and 5V microcontrollers. This data exchange is made through two dedicated pins, TEN/VSEL (when OM=0) and DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK modulation as accurate as possible. These two pins should be directly connected to two I/O pins of the P, thus leaving to the resident firmware the task of encoding and decoding the PWK data in accordance to the DiSEqC protocol. The fully bi-directional DiSEqCTM 2.0 interfacing is completed by the built-in 22KHz tone detector. Its input pin (DETIN) must be AC coupled to the DiSEqC TM bus and the extracted PWK data are available on the DSQOUT pin biased with a pull-up resistor to a fixed voltage (see Fig. 7 and 8). Full compliance of the system to the specification is not implied by the bare use of the LNBEH21; the system designer should also take in consideration that, to comply to the bi-directional DiSEqC TM 2.0 bus hardware requirements, an output R-L filter is needed. In order to help the system designer to avoid any distortion during the 22KHz tone transmission, due to the output R-L impedance, the LNBEH21 is provided with two output pins: the VOTX, to be used during the 22KHz tone transmission; and the VORX, to be used when the tone is received (see DiSEqC 2.0 typical application circuit). This allows the 22KHz tone to pass without any losses due to the R-L filter. During the 22KHz transmission, activated by TEN/VSEL pin, the VOTX pin must be preventively activated by the TTX I2C bit, so that, both the power supply and the 22KHz tone, are provided by mean of VOTX output. As soon as the tone transmission is expired, the VOTX must can set to OFF by setting the TTX I2C bit to zero, and the power supply is provided to the LNB by the VORX pin through the R-L filter. Unidirectional DiSEqC 1.x and non-DiSEqC systems normally don't need the output R-L termination, and the VOTX pin can be directly connected to the LNB supply port of the Tuner (see DiSeqC 1.x typical application circuit). There is also no need of Tone Decoding, thus DETIN and DSQOUT pins can be left connected to ground; both the 22KHz tone and the power supply, are provided by the VOTX by setting always TTX=1. W hen In DiSEqC mode, the Output Voltage level (13.1V,14.1V,19.5V,20.5V) is selected only by the VOM and LLC I2C bits combinations (refer to DiSEqC section in the Complete Truth Table on page 10 for detailed logic combination and corresponding function description).
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LNBEH21
Figure 7: DETIN/DSQOUT Circuit Figure 8: DETIN/DSQOUT Waveform
LNBEH21 DETIN
Ton e Detector
to DiSEqC bus
(LNB)
C6 100n F
DSQOUT
PWK data out
5V 0
R1 2.5K VDD (5V)
CH1=22KHz Tone to DETIN, CH2=PWK data at DSQOUT
13/18V Control Word mode, OM=1
W hen OM=1 the VOM is used to force the DC/DC Converter output voltage (VUP) in a steady state and to control the TEN/VSEL pin function. According to the VOM selection TEN/VSEL will absolve two different functions: 1)VOM=0 - TEN/VSEL pin controls both the post regulator output voltage (VOUT) and the DC/DC Converter output voltage (VUP). 2)VOM=1 - TEN/VSEL pin controls only the post regulator output voltage while the DC/DC Converter output voltage is forced in a steady state, at the high level, 22.7V typ. with LLC=1 and 21.7V typ. if LLC=0. During normal operation, when no 13/18V control word is transmitted, the device must work with VOM=0 and TEN/VSEL pin is used to select the odd or even numbered transponder setting up the post regulator output voltage in a steady state (13.25 or 19.5V); the VUP voltage is selected by the IC according to the VOUT value in order to minimize the power dissipation. Before the beginning of the 13/18V Control Word Communication, it is mandatory to set VOM at HIGH level forcing the VUP at 21.7V typ.; after a certain setup time the P can start to send the 13/18V pulses command to the TEN/VSEL pin. During the 13/18V pulses, the VOUT rise and fall time between 13.25V and 19.5V of are fully controlled by the internal voltage reference and they are maintained on a typical value of 575s, this time is guaranteed with a maximum output capacitance of 330nF and a load current in the range of 6 to 450mA. As soon as the communication has expired VOM bit must be set LOW to avoid any additional power dissipation (See Thermal Design Note). Refer to 13/18V Control Word section in the complete truth table on page 11 for detailed logic combination and corresponding function description.
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LNBEH21
DiSEqC COMMUNICATION TRUTH TABLE (TEN/VSEL pin controls the internal 22KHz Tone)
PCL TTX OM
0
LLC
0
VOM
0
EN
1
OTF
X
OLF
X
Function
VO = 13.25 V and VUP = 15.45 V TEN/VSEL = HIGH 22KHz Enabled TEN/VSEL = LOW 22KHz Disabled VO = 19.5V and VUP= 21.7 V TEN/VSEL = HIGH 22KHz Enabled TEN/VSEL = LOW 22KHz Disabled VO = 14.25 V and VUP = 16.45 V TEN/VSEL = HIGH 22KHz Enabled TEN/VSEL = LOW 22KHz Disabled VO = 20.5 V and VUP = 22.7 V TEN/VSEL = HIGH 22KHz Enabled TEN/VSEL = LOW 22KHz Disabled
0
0
1
1
X
X
0
1
0
1
X
X
0
1
1
1
X
X
13/18V CONTROL WORD COMMUNICATION TRUTH TABLE (TEN/VSEL pin function depends on VOM bit state)
PCL TTX OM LLC VOM EN OTF OLF Function
1
0
0
1
X
X
TEN/VSEL pin controls both the LNB output voltage and the DC/DC Converter Voltage (VUP) TEN/VSEL = LOW, VO = 13.25 V and VUP = 15.45 V TEN/VSEL = HIGH, VO = 19.5V and VUP= 21.7 V TEN/VSEL pin controls only the LNB output voltage and the DC/DC Converter output is forced always at 21.7 V TEN/VSEL = LOW, VO = 13.25 V and VUP = 21.7 V TEN/VSEL = HIGH, VO = 19.5V and VUP= 21.7 V
1
0
1
1
X
X
1
1
0
1
X
X
1
1
1
1
GENERAL FEATURES TRUTH TABLE
PCL
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TTX
OM
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TEN/VSEL pin controls both the LNB output voltage and the DC/DC Converter Voltage (VUP) TEN/VSEL = LOW, VO = 14.25 V and VUP = 16.45 V TEN/VSEL = HIGH, VO = 20.5V and VUP= 22.7 V TEN/VSEL pin used to set only the LNB output voltage. DC/DC Converter output voltage forced always at 22.7 V TEN/VSEL = LOW, VO = 14.25 V and VUP = 22.7 V TEN/VSEL = HIGH, VO = 20.5V and VUP= 22.7 V
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X
EN
1
OTF
X
OLF
X
Function
When TTX = 0 the device is set in receiving mode, the TX output is partially OFF the VORX pin is ON: VOTX = OFF, VORX = ON When TTX = 1 the device is set in receiving mode, the RX output is partially OFF the VOTX pin is ON: VOTX = ON, VORX = OFF Pulsed (dynamic) current limiting is selected Static current limiting is selected Power blocks disabled
X
1 1 1 0
X X X X
X X X X
X
X
X
X = don't care; values are typical unless otherwise specified.
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LNBEH21
Table 5: Electrical Characteristics TJ = 0 to 85C, EN=1, LLC=PCL=OM=VOM=0, 22KHz Tone Disabled, TTX=0/1, ISEL=High, VI=12V, IO=50mA, unless otherwise specified. See software description section for I2C access to the system register.
Symbol
VI II VO
Parameter
Supply Voltage Supply Current Output Voltage
Test Conditions
VO = 20.5V, IO = 750 mA Tone enabled VO = 20.5V, Tone Enabled, NO LOAD OM=0, VOM=1 (or OM=1, VOM=0), IO=750mA, TEN/VSEL=High OM=0, VOM=1 (or OM=1, VOM=0), IO=750 mA, TEN/VSEL=Low VI= 8 to 15V, VI= 8 to 15V, EN=1 EN=0 LLC=0 LLC=1 LLC=0 LLC=1
Min.
8
Typ.
20 3.5 19.5 20.5 13.25 14.25 5 5 575
Max.
15 40 7 20.3
Unit
V mA V
18.7
VO
Output Voltage
12.75
13.75
V
VO VO
Line Regulation Load Regulation
OM=0, VOM=0 OM=0, VOM=1
40 60 200
mV mV s
OM=0, VOM=0/1, IO = 50 to 750mA OM=VOM=1, TEN/VSEL from low to high, IO = 6 to 450 mA, CO = 10 to 330 nF ISEL 3.3V or Floating ISEL = GND PCL=0 PCL=0 Output Shorted Output Shorted
13/18V 13/18V Rise and Fall transition Time (to be tr- tf measured at the 90% and 10% voltage range) IMAX Output Current Limiting ISC tOFF tON fTONE ATONE DTONE tr, tf VEXTM ZEXTM fSW Output Short Circuit Current Dynamic Overload protection OFF Time Dynamic Overload protection ON Time Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise and Fall Time External Input Voltage
OM=0, TEN/VSEL=High OM=0, TEN/VSEL=High OM=0, TEN/VSEL=High OM=0, TEN/VSEL=High VOUT/VEXTM, AC Coupling f = 10Hz to 50KHz
GEXTM External Modulation Gain
fDETIN
O
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V OL IOZ VIL VIH IIH
VDETIN ZDETIN
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External Modulation Impedance DC/DC Converter Switching Frequency Tone Detector Frequency Capture Range Tone Detector Input Amplitude Tone Detector Input Impedance DSQOUT Pin Logic LOW
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20 40 5
750 450
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1000 700
mA mA ms ms
300
900 tOFF/10 24 0.9 60 15 400 260 220
KHz VPP % s mVPP kHz
0.55
0.72 50 8 6
f = 10Hz to 50KHz
0.4Vpp sinewave fIN=22kHz sinewave
18 0.2 150
24 1.5
kHz VPP k
Tone present Tone absent
IOL=2mA VOH = 6V
0.3
0.5 10 0.8
V A V V
DSQOUT Pin Leakage Current TEN/VSEL Input Pin Logic LOW TEN/VSEL Input Pin Logic HIGH TEN/VSEL Pin Input Current
2 VIH = 5V 15
A
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Symbol
IOBK TSHDN
Parameter
Output Backward Current EN=0
Test Conditions
VOBK = 18V
Min.
Typ.
-6 150 15
Max.
-15
Unit
mA C C
Temperature Shutdown Threshold TSHDN Temperature Shutdown Hysteresis
Table 6: Gate And Sense Electrical Characteristics (TJ = 0 to 85C, VI = 12V)
Symbol Parameter Test Conditions
IGATE= -100mA IGATE= 100mA
Min.
Typ.
4.5 4.5 200
Max.
Unit
mV
RDSON-L Gate LOW RDSON RDSON-H Gate HIGH RDSON VSENSE Current Limit Sense Voltage
Table 7: I2C Electrical Characteristics (TJ = 0 to 85C, VI = 12V)
Symbol
VIL VIH II V OL fMAX
Parameter
LOW Level Input Voltage HIGH Level Input Voltage Input Current Low Level Output Voltage SDA, SCL SDA, SCL
Test Conditions
Min.
2 -10
Typ.
Max.
0.8
SDA, SCL, VI = 0.4 to 4.5V SDA (open drain), IOL = 6mA
Maximum Clock Frequency SCL
Table 8: Address Pin Characteristics (TJ = 0 to 85C, VIN=12V)
Symbol Parameter Test Conditions
VADDR-1 "0001000" Addr Pin Voltage VADDR-2 "0001001" Addr Pin Voltage VADDR-3 "0001010" Addr Pin Voltage VADDR-4 "0001011" Addr Pin Voltage
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0 1.3 2.3 3.3
500
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Unit
V V V KHz
10
A
0.6
Min.
Typ.
Max.
0.7 1.7 2.7 5
Unit
V V V V
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THERMAL DESIGN NOTES During normal operation, this device dissipates some power. The power dissipation depends on the selected communication mode (DiSEqC or 13/18 control word communication). W hen the device is used in DiSEqC mode, at maximum rated output current (750mA), the voltage drop on the linear regulator lead to a total dissipated power that is about 1.65W. If the control word communication mode is selected, at maximum rated current of 450mA, the total power dissipated is about 1W. By the way, during the 13/18V pulses code transmission (OM=VOM=1) the average power dissipation is higher than 1W because, in this case, before to start sending the 13/18V pulses code, the VUP voltage must be forced in steady state at 21.7V by VOM=1, (22.7V if LLC=1) in order to ensure the proper code transition rise and fall timing while the VOUT voltage is continuously switched between 13V and 18V; this means that, in the 13V half period the peak of power dissipation is about 3.8W typ. (@ Iout=450mA max.). Obviously this is the peak power dissipation as the average value during the code transmission has to be calculated taking into account the 0/1 bits combination. The heat generated requires a suitable heatsink to keep the junction temperature below the overtemperature protection threshold. Assuming a 45C temperature inside the Set-Top-Box case and a max continuos power dissipation of 1.65W, the total Rthj-amb has to be less than 48C/W. W hile this can be easily achieved using a through-hole power package that can be attached to a small heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous copper area of the pcb ground layer to dissipate the heat coming from the IC body by mean the ground exposed pad present on the bottom side of the PSO-20 package. Given for the PSO-20 an Rthj-case equal to 2C/W, a maximum of 46C/W are left to the PCB heatsink. This figure is achieved if a minimum of 6.5cm2 copper area is placed just below the IC body. This area can be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the opposite side where the IC is placed. In figure 9, is shown a suggested layout for the PSO-20 package with a dual layer PCB, where the IC exposed pad connected to GND and the square dissipating area are thermally connected through 32 vias holes, filled by solder. This arrangement, when L=25mm, achieves an Rthc-a of about 32C/W. Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to design a dissipating area having a shape as square as possible and not interrupted by other copper t r ac es . Figure 9: PowerSO-20 Suggested Pcb Heatsink Layout
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TYPICAL CHARACTERISTICS (unless otherwise specified Tj = 25C) Figure 10: Output Voltage vs Temperature Figure 13: Supply Current vs Temperature
Figure 11: Output Voltage vs Temperature
Figure 14: Supply Current vs Temperature
Figure 12: Load Regulation vs Temperature
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Figure 15: Supply Current vs Temperature
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Figure 16: Dynamic Overload Protection ON Time vs Temperature Figure 19: Output Current Limiting vs Temperature
Figure 17: Dynamic Overload Protection OFF Time vs Temperature
Figure 20: Tone Frequency vs Temperature
Figure 18: Output Current Limiting vs Temperature
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Figure 21: Tone Amplitude vs Temperature
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Figure 22: Tone Duty Cycle vs Temperature Figure 25: Undervoltage Lockout Threshold vs Temperature
Figure 23: Tone Rise Time vs Temperature
Figure 26: Output Backward Current vs Temperature
Figure 24: Tone Fall Time vs Temperature
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Figure 27: DC/DC Converter Efficiency vs Temperature
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Figure 28: Current Limit Sense Voltage vs Temperature Figure 31: TEN/VSEL Tone Enable Transient Response
VCC=12V, IO=50mA, EN=1, OM=0
Figure 29: 22kHz Tone Waveform
Figure 32: TEN/VSEL Tone Disable Transient Response
VCC=12V, IO=50mA, EN=TEN=1
Figure 30: TEN/VSEL Tone Enable Transient Response
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VCC=12V, IO=50mA, EN=1, OM=0
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
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PowerSO-20 MECHANICAL DATA
DIM. A a1 a2 a3 b c D (1) E e e3 E1 (1) E2 G h L N S T 0 10.0 0.80 0 10.90 0 0.40 0.23 15.80 13.90 1.27 11.43 11.10 2.90 0.10 1.10 1.10 0.0314 0.0000 0.4291 0.10 mm. MIN. TYP MAX. 3.60 0.30 3.30 0.10 0.53 0.32 16.00 14.50 0 0.0157 0.0090 0.6220 0.547 2 0.0500 0.4500 0.0039 MIN. inch TYP. MAX. 0.1417 0.0118 0.1299 0.0039 0.0209 0.0013 0.630 0.5710
10
8
(1) "D and E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006")
N
N
b DETAIL A
O
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1
20
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11
so Ob R a2 A DETAIL B
te le
0
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0.4370 0.1141 0.0039 0.0433 0.0433 10 8
0.3937
c a1 E
e
led a
DETAIL A
a3 DETAIL B E1 T
Gage Plan e 0.35
slug
E2
- C-
S
L
SEATI G PLANE N GC (COPLANARITY)
1
0
PSO20MEC
h x 45
0056635
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Tape & Reel PowerSO-20 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P W 15.1 16.5 3.8 3.9 23.9 23.7 12.8 20.2 60 30.4 15.3 16.7 4.0 4.1 24.1 24.3 0.594 0.650 0.149 0.153 0.941 0.933 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.602 0.658 MIN. TYP. MAX. 12.99 2 0.519 inch
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0.157 0.161 0.949 0.957
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Table 9: Revision History
Date
05-Jul-2004
Revision
1 First Release.
Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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