STLC3075
Integrated POTS interface for home access gateway and WLL
Features
Monochip SLIC optimized for WLL & VoIP applications Implements all Borsht function key features Single supply (4.5V to 12V) for fly-back configuration Single supply (5.5V to 12V) for buck-boost configuration Built in DC/DC converter controller Soft battery reversal with programmable transition time On-hook transmission Programmable off-hook detector threshold Metering pulse generation and filter Integrated ringing Integrated ring trip Parallel control interface (3.3V logic level) Programmable constant current feed Surface mount package Integrated thermal protection Dual gain value option
TQFP44
The battery level is properly adjusted depending on the operating mode. A useful characteristic for these applications is the integrated ringing generator. The control interface is parallel with open drain output and 3.3V logic levels. The metering pulses are generated on-chip starting from two logic signals (0, 3.3V): one signal defining the metering pulse frequency, the other signal defining the metering pulse duration. An on-chip circuit then provides the proper shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed by external components.
Automatic recognition flyback and buckboost configuration BCDIIIS 90V technology -40 C to +85C operating range
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A dedicated cancellation circuit avoids possible CODEC input saturation due to metering pulse echo. Constant current feed can be set from 20mA to 40mA. Off-hook detection threshold is programmable from 5mA to 9mA. The device, which is developed in BCDIIIS technology (90V process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when Tj exceeds 140C.
The STLC3075 is a SLIC device specifically designed for WLL (Wireless Local Loop), and ISDN terminal adaptors and VoIP applications. One distinctive characteristic of this device is its ability to operate with a single supply voltage (from +4.5V to +12V) and to self generate the negative battery by means of an on-chip DC/DC converter controller that drives an external MOS switch.
March 2007
Rev 7
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www.st.com
36
Contents
STLC3075
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. 1 3.2 DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 High impedance feeding (HI-Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 5 6 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Appendix A Measurement configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
A.1
Appendix B Over voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Appendix C Typical state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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STLC3075 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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STLC3075
Block diagram
1
Block diagram
Figure 1. Block diagram
PD D0 D1 D2 DET
GAIN SETTING
INPUT LOGIC AND DECODER
OUTPUT LOGIC
BGND
Status and functions
TIP TX RX ZAC1 ZAC RS ZB
LINE
OUTPUT
SUPERVISION AC PROC
DRIVER
STAGE
RING
DC PROC
CKTTX CTTX1 CTTX2 FTTX
TTX PROC
REFERENCE
RTTX
CAC
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ILTF RD IREF RLIM RTH
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Vcc Vss
Agnd
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VOLT.
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CREV
CSVR
DC/DC CONV.
CLK RSENSE GATE VF CZ
CVCC VPOS
VBAT
Vbat
AGND
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Pin description
STLC3075
2
Pin description
Figure 2. Pin connection
VBAT1 BGND 35 CREV VBAT N.C. CSVR 34 33 32 31 30 29 ILTF RD RTH IREF RING 37 N.C. N.C. N.C. 38
TIP
44 D0 D1 D2 PD GAIN SET N.C. DET CKTTX CTTX1 CTTX2 RTTX 1 2 3 4 5 6 7 8 9 10 11 12 FTTX
43
42
41
40
39
36
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RX ZAC1
13
14
15 ZAC
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19 TX 20 CZ 21 VF
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RLIM AGND CVCC VPOS RSENSE GATE CLK
17 ZB
22 N.C.
D00TL488
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STLC3075 Table 1.
N 1 2 3 4 5 D0 D1 D2 PD Gain SET
Pin description Pin description
Pin Control interface: input bit 0 Control interface: input bit 1 Control interface: input bit 2 Power down input. Normally connected to CVCC (or to logic level high) Control gain interface: 0 Level Rxgain = 0dB Txgain = -12dB 1 Level Rxgain = +6dB Txgain = -12dB Not connected Logic interface output of the supervision detector (active low) Metering pulse clock input (12 kHz or 16kHz square wave) Metering burst shaping external capacitor Metering burst shaping external capacitor Function
6, 22, 38, NC 39, 40, 42 7 8 9 10 11 DET CKTTX CTTX1 CTTX2 RTTX
Metering pulse cancellation buffer output. TTX filter network should be connected to this point. If not used, should be left open. Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering
12
FTTX
13
RX
4 wires input port (RX input). A 100k external resistor must be connected to AGND via the bias input stage. This signal refers to AGND. If connected to single supply CODEC output it must be DC decoupled with proper capacitor. RX buffer output (the AC impedance is connected from this node to ZAC)
14 15 16
ZAC1 ZAC RS
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18 19 20 21
17
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AC impedance synthesis
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Protection resistors image (the image resistor is connected from this node to ZAC) Balance network for 2 to 4 wire conversion (the balance impedance ZB is connected from this node to AGND. ZA impedance is connected from this node to ZAC1). AC feedback input, AC/DC split capacitor (CAC) 4 wire output port (TX output). The signal is referred to AGND. If connected to single supply CODEC input it must be DC decoupled with proper capacitor. Flyback compensation Feedback input for DC/DC converter controller Power switch controller clock (typ. 125KHz). This pin can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an internal auto-oscillation is internally generated and it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE output is disabled.
CAC TX CZ VF
23
CLK
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Pin description Table 1.
N 24
STLC3075 Pin description (continued)
Pin GATE Function Driver for external power MOS transistor (P-channel in buckboost configuration, N-channel in flyback configuration). Voltage input for current sensing. RSENSE resistor should be connected close to this pin and VPOS pin (Buckboost) or GND (Flyback). The PCB layout should minimize the extra resistance introduced by the copper tracks. Positive supply input Internal positive voltage supply filter Analog ground. Must be shorted with BGND. Constant current feed programming pin (via RLIM). RLIM should be connected close to this pin and AGND pin to avoid noise injection. Internal bias current setting pin. RREF should be connected close to this pin and AGND pin to avoid noise injection. Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin and AGND pin to avoid noise injection. DC feedback and ring trip input. RD should be connected close to this pin and AGND pin to avoid noise injection. Transversal line current image output Battery supply filter capacitor
25
RSENSE
26 27 28 29 30 31 32 33 34 35 36 37 41
VPOS CVCC AGND RLIM IREF RTH RD ILTF CSVR BG ND VBAT RING TIP
Battery ground, must be shorted with AGND Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted to VBAT1. 2 wire ports; RING wire (Ib is the current sunk into this pin)
43
CREV
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VBAT1
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2 wire ports; TIP wire (Ia is the current sourced from this pin) Reverse polarity transition time control. A proper capacitor connected between this pin and AGND is setting the reverse polarity transition time. This is the same transition time used to shape the 'trapezoidal ringing' during ringing injection. Frame connection. Must be shorted to VBAT
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STLC3075
Functional description
3
Functional description
The STLC3075 is a device specifically developed for WLL VoIP and ISDN-TA applications. It is based on a SLIC core, on purpose optimized for these applications, with the addition of a DC/DC converter controller to meet the WLL and ISDN-TA design requirements. The SLIC performs the standard feeding, signalling and transmission functions. STLC3075 can be set in three different operating modes via the D0, D1, D2 pins of the control logic interface (0 to 3.3V logic levels). The loop status is carried out on the DET pin (active low). The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels. The four possible SLIC's operating modes are: Power down High impedance feeding (HI-Z) Active Ringing
Table 2 shows how to set the different SLIC operating modes.
Table 2.
PD 0 1 1 1 1 1 1
SLIC operating modes
D0 0 0 0 0 1 1 1 D1 0 0 1 1 1 1 D2 X X 0 1 0 1 Power down H.I. feeding (HI-Z)
Active normal polarity
Active reverse polarity
3.1
DC/DC converter
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The DC/DC converter controller drives an external power MOS transistor N-Ch plus transformer (Flyback configuration) or P-Ch plus inductor (Buckboost configuration), in order to generate the negative battery voltage needed for the device operation. The DC/DC converter controller is synchronized with an external CLK (125kHz typ.) or with an internal clock generated when the pin CLK is connected to CVCC. One RSENSE in series to PGND supply (Flyback) or to VPOS supply (Buckboost) allows to fix the maximum allowed input peak current.
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Active TTX injection (N.P.) Active TTX injection (R.P.) Ring (D2 bit toggles @ fring)
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Operating mode
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This feature is implemented in order to avoid overload on VPOS supply in case of line transient (ex. ring trip detection). The 110m typical value guarantees an average current consumption from VPOS < 700mA for buckboost configuration. The 220m typical value guarantees an average current consumption from VPOS < 800mA for flyback configuration.
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Functional description The self generated battery voltage is set to a predefined value in on-hook state.
STLC3075
The typical value of -50V can be adjusted via one external resistor (RF1). When RING mode is selected this typical value is increased to -70V. Once the line goes in off-hook condition, the DC/DC converter automatically adjusts the generated battery voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimizing the power dissipation.
3.2
3.2.1
Operating modes
Power down
When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance. The line detectors are also disabled therefore the off-hook condition cannot be detected. The power down mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. The power down mode is also forced by STLC3075 in case of thermal overload (Tj > 140C). In this case the device goes back to the previous status as soon as the junction temperature decrease under the hysteresis threshold. No AC transmission is possible.
3.2.2
High impedance feeding (HI-Z)
This operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. The output voltage in on-hook condition is equal to the self generated battery voltage (-50V typical). When off-hook occurs the DET becomes active (low logic level). The off-hook threshold value in HI-Z mode is the same as the programmed value in ACTIVE mode. The DC characteristics in HI-Z mode are equal to the self generated battery with 2x(1600+Rp) in series (see Figure 3), where Rp is the external protection resistance. No AC transmission is possible.
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Figure 3.
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DC characteristics in HI-Z mode.
IL Vbat 2x(R1+Rp)
Slope: 2x(R1+Rp) (R1=1600ohm)
VL Vbat (-50V)
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STLC3075
Functional description
3.2.3
Active
DC characteristics & supervision
When this mode is selected the STLC3075 provides both DC feeding and AC transmission. The STLC3075 feeds the line with a constant current fixed by RLIM (20mA to 40mA range). The on-hook voltage is typically 40V allowing on-hook transmission; the self generated Vbat is -50V typical. If the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the STLC3075 behaves like a 40V voltage source with a series impedance equal to the protection resistors 2xRp (typ. 2x50). Figure 4. shows the typical DC characteristics in active mode. The line status (on/off hook) is monitored by the SLIC'S supervision circuit. The off-hook threshold can be programmed via the external resistor RTH in the range from 5mA to 9mA. Independently on the programmed constant current value, the TIP and RING buffers have a current source capability limited to 80mA typical. Figure 4. DC characteristics in active mode
IL Ilim (20 to 40mA)
2Rp
Moreover the power available at Vbat is controlled by the DC/DC converter that limits the peak current drawn from the VPOS supply. The maximum allowed current peak is set by RSENSE resistor.
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VL
Vbat (-50V)
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Functional description
STLC3075
AC characteristics
The SLIC provides the standard SLIC transmission functions. Once in active mode the SLIC can operate with two different Tx, Rx gains set by the gain set control bit (See Table 3 below). Table 3.
Gain set 0 1
Gain set in active mode
4 to 2 wires gain 0dB +6dB 2 to 4 wires gain -6dB -12dB Impedance synthesis scale factor x 50 x 25
Input impedance synthesis: can be real or complex and is set by a scaled (x50 or x25) external ZAC impedance Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the Tx output with a -6dB or -12dB gain and from the Rx input to the 2W port with a 0dB or +6dB gain 2 to 4 wires conversion: The balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedances ZA and ZB
Once in active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control bits (see also Table 4). Table 4.
D0 0 0 1 1
SLIC states in active mode
D1 1 1 1 1 D2 0 1 0 1 Active normal polarity
Operating mode
Active reverse polarity
Active TTX injection (N.P.) Active TTX injection (R.P.)
Polarity reversal
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The D2 bit controls the line polarity, the transition between the two polarities is performed in a 'soft' way. This means that the TIP and RING wires exchange their polarities following a ramp transition (see Figure 5). The transition time is controlled by an external capacitor CREV. This capacitor also sets the shape of the ringing trapezoidal waveform. When the control pins set the battery reversal, the line polarity is reversed with a proper transition time set via an external capacitor (CREV).
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Figure 5.
TIP/RING typical transition from direct to reverse polarity
GND T IP
4V typ.
40V typ ON-HOOK
dV/dT set by CREV RING
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STLC3075
Functional description
Metering pulse injection (TTX)
The metering pulses circuit consists of a burst shaping generator that generates a square shaped wave and a low pass filter to reduce the harmonic distortion of the output signal. The metering pulse is obtained from two logic signals:
CKTTX: is a square wave at the TTX frequency (12 or 16KHz) that must be permanently applied to the CKTTX pin or at least for all the duration of the TTX pulse (including rising and decay phases). D0: enables the TTX generation circuit and defines the TTX pulse duration.
These two signals are processed by a dedicated circuitry integrated on chip that generates the metering pulse as an amplitude modulated shaped square wave (SQTTX) (see Figure 6). Both the amplitude and the envelope of the square wave (SQTTX) can be programmed by means of external components. In particular the amplitude is set by the two RLV resistors while the shaping is set by the CS capacitor. Figure 6. Metering pulse generation circuit
Low Pass Filter
CTTX1
C1
RLV BURST
SHAPING GENERATOR
CS
SQTTX
R1 CFL
R2 FTTX OP1
+
RLV
CTTX2 D0 CKTTX
Square wave pulse metering
The waveform so generated is then filtered and injected on the line. The low pass filter is obtained by using the integrated buffer OP1 connected between pin FTTX (OP1 non inverting input) and RTTX (OP1 output) (see Figure 6) and by implementing a "Sallen and Key" configuration. Depending on the external components count it is possible to build an optimized application depending on the distortion level required. In particular harmonic distortion levels equal to 13%, 6% and 3% can be obtained respectively with first, second and third order filters (see Figure 6).
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Required external components vs. filter order.
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Sinusoidal wave pulse metering
CFL
T HD
1 2 3
X X X X X X X X X X
13% 6% 3%
The circuit showed in the "Application diagram" is related to the simple first order filter. Once the shaped and filtered signal is obtained at RTTX buffer output it is injected on the TIP/RING pins with a +6dB gain or +12dB gain. It should be noted that this is the nominal condition obtained in presence of ideal TTX echo cancellation (obtained via proper setting of RTTX and CTTX). In addition the effective level obtained on the line will depend on the line impedance and the protection resistors value. In typical applications (TTX line impedance =200 RP = 50 and , ,
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Functional description
STLC3075
ideal TTX echo cancellation), the metering pulse level on the line equals 1.33 or 2.66 times the level applied to the RTTX pin. As already mentioned the metering pulse echo cancellation is obtained by means of two external components (RTTX and CTTX) that should match the line impedance at the TTX frequency. This simple network has a double effect:
it synthesizes a low output impedance at the TIP/RING pins at the TTX frequency it cuts the eventual TTX echo that would have been transferred from the line to the TX output
3.2.4
Ringing
When this mode is selected, the STLC3075 self generates a higher negative battery (-70V typ.) in order to allow a balanced ringing signal of typically 65V peak. In this condition both the DC and AC feedback loops are disabled and the SLIC line drivers operate as voltage buffers. The ring waveform is obtained by toggling the D2 control bit at the desired ring frequency. This bit in fact controls the line polarity (0=direct; 1= reverse). As in the active mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see Figure 7). The shaping is defined by the CREV external capacitor. Figure 7. TIP/RING typical ringing waveform
GND TIP
2.5V typ.
dV/dT set by CREV RING VBAT
Selecting the proper capacitor value it is possible to get different crest factor values. The following table shows the crest factor values obtained with a 20Hz and 25Hz ring frequency and with 1REN. These value are valid either with European or USA specification: Table 5.
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CREST factor values @ 20 and 25Hz
CREST factor @20Hz 1.2 1.25 1.33 CREST factor @25Hz 1.26 1.32 Not(1)
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CREV 22nF 27nF 33nF
1. Distortion already less than 10%
The ring trip detection is performed by sensing the variation of the AC line impedance from on-hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. It should be noted that such a method is optimized for operation on short loop applications and may not operate properly in the case of long loop applications (> 500).
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STLC3075
Functional description Once the ring trip is detected, the DET output is activated (logic level low). At this point the card controller or a simple logic circuit stops the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3075 in the proper operating mode (normally active).
Ring level in presence of more telephones in parallel
As already mentioned in the previous section, the maximum current that can be drawn from the VPOS supply is controlled and limited via the external RSENSE. This also limits the power available at the self generated negative battery. If for any reason the ringer load is too low, the self generated battery drops in order to keep the power consumption to the fixed limit and consequently the ring voltage level is also reduced. In the typical buckboost configuration with RSENSE = 110m the peak current from VPOS is limited to around 900mApk, which correspond to an average current of 700mA max. In this condition the STLC3075 can drive up to 3REN with a ring frequency fr=25Hz (1REN = 1800 + 1.0F, european standard). In order to drive up to 5REN (1REN= 6930 + 8F, US standard) it is necessary to modify the external components as follows: CREV = 15nF; RD = 2.2K; RSENSE = 100m . In flyback configuration the value of RSENSE = 220m guarantees to match both European and USA standard. In order to drive 5REN (US standard) it is necessary to modify the external component: RD = 2K2.
3.2.5
Layout recommendation
A properly designed PCB layout is a basic issue to guarantee a correct behavior and good noise performance. Par ticular care must be taken on the ground connection. Using the configurations shown on Figure 10 and Figure 11 permits to avoid possible problems. The ground of the power supply (VPOS) has to be connected to the center of the star, named as SYSTEM-GND. This point should show a resistance as low as possible, that means it should be a ground plane. In particular to avoid noise problems the layout should prevent any coupling between the DC/DC converter components and analog pins that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). As a first recommendation the components CV, L, T1, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components. Additional improvements can be obtained by decoupling the center of the star from the analog ground of STLC3075 using small chokes by adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch frequency on VPOS
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Functional description
STLC3075
3.2.6
External components list
In order to properly define the external components value the following system parameters have to be defined:
the AC input impedance shown by the SLIC at the line terminals Zs to which the return loss measurement is referred. It can be real (typ. 600) or complex. the AC balance impedance, it is the equivalent impedance of the line `Zl' used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance. the value of the two protection resistors Rp in series with the line termination. the line impedance at the TTX frequency Zlttx the metering pulse level amplitude measured at line termination VLOTTX. In case of low order filtering, VLOTTX represents the amplitude (Vrms) of the fundamental frequency component (typ. 12 or 16kHz) the pulse metering envelope rise and decay time constant the slope of the ringing waveform VTR/T the value of the constant current limit current 'Ilim' the value of the off-hook current threshold ITH the value of the ring trip rectified average threshold current IRTH
the value of the required self generated negative battery VBATR in ring mode (max value is 70V). This value can be obtained from the desired ring peak level + 5V. the value of the maximum current peak drawn from VPOS 'IPK'.
Table 6.
Name RRX RREF CSVR RD CAC RP
External components for buckboost configuration
Function Rx input bias resistor Bias setting current Negative battery filter Ring trip threshold setting resistor AC/DC split capacitance Formula
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RTH CREV RDD CVCC
RLIM
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Line protection resistor Current limiting programming
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RREF = 1.3/Ibias Ibias = 50A
CSVR = 1/(2 fp 1.8M) fp = 50Hz RD = 100/IRTH 2K < RD < 5K
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Typ. value 100k 5% 26k 1% 1.5nF 10% 100V 4.12k 1%@ IRTH = 24mA 22F 20% 15V @ RD = 4.12k
Rp > 30 RLIM = 1300/Ilim 32.5k < RLIM < 65k RTH = 290/ITH 27k < RTH < 52k CREV = ((1/3750) · T/VTR)
50 1% 52.3k 1% @ Ilim = 25mA 32.4k 1% @ ITH = 9mA 22nF 10% 10V @ 12V/ms 100k 100nF 20% 10V
Off-hook threshold programming (Active mode) Reverse polarity transition time programming Pull up resistors Internally supply filter capacitor
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STLC3075 Table 6.
Name CVPOS
Functional description External components for buckboost configuration (continued)
Function Formula Typ. value 100F(1)
Positive supply filter capacitor with low impedance for switch mode power supply Battery supply filter capacitor with low impedance for switch mode power supply High frequency noise filter High frequency noise filter DC/DC converter switch P ch. MOS transistor RDS(ON) .2 VDS = -100V 1, Total gate charge= 20nC max. with VGS=4.5V and VDS=1V ID>500mA
CV CVB CRD(3)
100F 20% 100V(2) 470nF 20% 100V 100nF 10% 15V Possible choices: IRF9510 or IRF9520 or IRF9120 or equivalent SMBYW01-200 or equivalent
Q1
D1 RSENSE RF1 RF2 L
DC/DC converter series diode Vr > 100V, tRR 50ns DC/DC converter peak current RSENSE = 100mV/IPK limiting Negative battery programming 250K < RF1 < 300K(4) level Negative battery programming level DC/DC converter inductor DC resistance 0.1(5)
110m @ IPK = 900mA
1. CVPOS should be defined depending on the power supply current capability and maximum allowable ripple 2. For low ripple application use 2x47m F in parallel. 3. Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). 4. RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as shown in Table 7. VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.). This relation is valid providing that the VPOS power supply current capability and the RSENSE programming allow to source all the current requested by the particular ringer load configuration 5. For high efficiency in HI-Z mode coil resistance @125kHz must be < 3.
Table 7.
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VBAT (ACTIVE) VBATR (RING)
Pr e
VBAT values in RING and ACTIVE modes
267k -46V -62V 280k -48V -65V 294k -49V -68V 300k -50V -70V
du o
(s) ct
so Ob -
te le
ro P
300k 1% @ VBATR = -70V 9.1k 1%
uc d
s) t(
L=100H SUMIDA CDRH125 or equivalent
15/36
Functional description Table 8.
Name RRX RREF CSVR RD CAC RP RLIM RTH CREV RDD CVCC
STLC3075
External components for flyback configuration
Function Rx input bias resistor Bias setting current Negative battery filter Ring trip threshold setting resistor AC/DC split capacitance Line protection resistor Current limiting programming Off-hook threshold programming (Active mode) Reverse polarity transition time programming Pull up resistors Internally supply filter capacitor Positive supply filter capacitor with low impedance for switch mode power supply Battery supply filter capacitor with low impedance for switch mode power supply High frequency noise filter High frequency noise filter Flyback compensation capacitor Sense filter capacitor Sense filter resistor Rp > 30 RLIM = 1300/Ilim 32.5k < RLIM < 65k RTH = 290/ITH 27k < RTH < 52k CREV = ((1/3750)· T/VTR) RREF = 1.3/Ibias; Ibias = 50A CSVR = 1/(2 fp 1.8M) fp = 50Hz RD = 100/IRTH 2K < RD < 5K Formula Typ. value 100k 5% 26k 1% 1.5nF 10% 100V 4.12k 1% @ IRTH = 24mA 22F 20% 15V @ RD = 4.12k 50 1% 52.3k 1% @ Ilim = 25mA 32.4k 1% @ ITH = 9mA
22nF 10% 10V @ 12V/ms
CVPOS
CV CVB CRD(3) CZ CSF RSF RSENSE
O
bs
Q1 D1 T1
let o
DC/DC converter peak current limiting
ro P e
du
ct
(s)
so Ob -
te le
ro P
100nF 20% 10V
uc d
100k 100F(1)
s) t(
100F 20% 100V(2) 470nF 20% 100V 100nF 10% 15V 2.2nF, 20% 120pF, 20% 1k
RSENSE = 375mV/IPK RDS(ON) .05 0 , VDSS = 30V VDG=30V, ID = 6.5A Low threshold drive Vr > 350V, tRR 80ns
220m @ IPK = 1.7A
DC/DC converter switch N channel MOS transistor DC/DC converter series diode
STN4NF03L or equivalent
SMBYTW01-400 or equivalent Tyco COEV MAGNETICS MGPWG-00007 or Coilcraft FA2469-AL(4)
Flyback transformer 4W, turns ratio DC/DC converter transformer 1:16 for VPOS range from 4.5V to 8.5V
16/36
STLC3075 Table 8.
Name
Functional description External components for flyback configuration
Function Formula Typ. value Tyco COEV MAGNETICS MGPWG-00008 or Coilcraft FA2470-AL(5) 300k 1% @ VBATR = -70V 9.1k 1%
T1
Flyback transformer 4W, turns ratio DC/DC converter transformer 1:8 for VPOS range from 8.5V to 12V Negative battery programming level Negative battery programming level 250K
RF1 RF2
1. CVPOS should be defined depending on the power supply current capability and maximum allowable ripple. 2. For low ripple application use 2x47m F in parallel. 3. Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). 4. Coilcraft type FA2469-AL, Flyback transformer 4W, 1:16 with a VPOS range from 4.5V to 8.5V @ +20C unless otherwise specified. Also check Table 9 for further electrical specifications 5. Coilcraft type FA2470-AL, Flyback transformer 4W, 1:8 with a VPOS range from 8.5V to 12V @ +20C unless otherwise specified. Also check Table 10 for further electrical specifications 6. RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as as shown in Table 7. VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.). This relation is valid providing that the VPOS power supply current capability and the RSENSE programming allow to source all the current requested by the particular ringer load configuration.
Table 9.
Coilcraft type FA2469-AL electrical specifications
Limit 0.0205 0.414 0.036 16.50 Unit mH uH Tol
Test description Inductance Leakage inductance DC resistance DC resistance Turns ratio HI POT
Table 10.
bs O
let o
Inductance
Pr e
Coilcraft type FA2470-AL electrical specifications
Limit 0.0205 0.40 0.036 7.92 8:1 1.500 Unit mH uH ohm ohm VAC Tol Max Max Max Max +/-3.3% Notes 1-3, 10KHz, 100mVmrs 1-3, 100KHz, 100mVmrs Shor t pins 4,6 1-3 4-6 (4-6):(1-3), 10KHz, 100mVAC VDC to be applied for 1 second from pins 1,3 to pins 4,6. 500A max leakage current
du o
ct
(s)
16:1
so Ob ohm ohm VAC
te le
Max Max Max Max +/-4%
1-3, 10KHz, 100mVmrs 1-3, 100KHz, 100mVmrs Shor t pins 4,6 1-3 4-6 (4-6):(1-3), 10KHz, 100mVAC VDC to be applied for 1 second from pins 1,3 to pins 4,6. 500A max leakage current
ro P
uc d
Notes
s) t(
1.500
Test description
Leakage inductance DC resistance DC resistance Turns ratio HI POT
17/36
Functional description Table 11.
Name RS ZAC ZA(1) ZB(1) CCOMP CH RTTX(2) CTTX(2) RLV CS CFL
STLC3075
External components @gain set = 0
Function Protection resistance image Two wire AC impedance SLIC impedance balancing network Line impedance balancing network AC feedback loop compensation Trans-hybrid Loss frequency compensation Pulse metering cancellation resistor Pulse metering cancellation capacitor Pulse metering level resistor Pulse metering shaping capacitor Formula RS = 50 (2Rp) ZAC = 50 (Zs - 2Rp) ZA = 50 Zs ZB = 50 Zl fo = 250kHz CCOMP = 1/(2 fo 100 (RP)) CH = CCOMP RTTX = 50Re (Zlttx+2Rp) CTTX = 1/{50 2 fttx [lm(Zlttx)]} RLV = 63.3·103···VLOTTX = (|Zlttx + 2Rp|/|Zlttx|) CS = /(2 RLV) Typ. value 5k @ Rp = 50 25k 1% @ Zs = 600 30k 1% @ Zs = 600 30k 1% @ Zl = 600 120pF 10% 10V @ Rp = 50 120pF 10% 10V 15k @ Zlttx = 200 real
100nF 10% 10V(3) @ Zlttx = 200 real
Pulse metering filter capacitor CFL = 2/(2 fttx RLV)
1. In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|.
2. Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula: ZTTX=50*(Zlttx+2Rp). 3. In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz).
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
16.2k @ VLOTTX = 170mVrms
100nF 10% 10V @ = 3.2ms, RLV = 16.2k
uc d
s) t(
1.5nF 10% 10V @fttx = 12kHz RLV = 16.2k
18/36
STLC3075 Table 12.
Name RS ZAC ZA(1) ZB(1) CCOMP CH RTTX(2) CTTX (2) RLV CS CFL
Functional description External components @gain set = 1
Function Protection resistance image Two wire AC impedance SLIC impedance balancing network Line impedance balancing network AC feedback loop compensation Trans-hybrid Loss frequency compensation Pulse metering cancellation resistor Pulse metering cancellation capacitor Pulse metering level resistor Pulse metering shaping capacitor Formula RS = 50 (2Rp) ZAC = 50 (Zs - 2Rp) ZA = 50 Zs ZB = 50 Zl fo = 250kHz CCOMP = 1/(2 fo 100 (RP)) CH = CCOMP RTTX = 50Re (Zlttx+2Rp) CTTX = 1/{50 2 fttx [lm(Zlttx)]} RLV = 63.3·103···VLOTTX = (|Zlttx + 2Rp|/|Zlttx|) CS = /(2 RLV) Typ. value 5k @ Rp = 50 25k 1% @ Zs = 600 30k 1% @ Zs = 600 30k 1% @ Zl = 600 120pF 10% 10V @ Rp = 50 120pF 10% 10V 15k @ Zlttx = 200 real
100nF 10% 10V (3) @ Zlttx = 200 real
Pulse metering filter capacitor CFL = 2/(2 fttx RLV)
1. In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|. 2. Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula: ZTTX=50*(Zlttx+2Rp). 3. In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz).
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
16.2k @ VLOTTX = 170mVrms
uc d
s) t(
100nF 10% 10V @ = 3.2ms, RLV = 16.2k
1.5nF 10% 10V @fttx = 12kHz RLV = 16.2k
19/36
Functional description Figure 8. Application diagram with N-channel
RX RRX TX CVCC VPOS CVPOS
STLC3075
T1 RS RX RS ZAC CCOMP ZAC ZA ZB CH VDD RDD GAIN SET ZB VF CZ CLK RP CONTROL INTERFACE DET D0 D1 D2 PD TTX CLOCK RLV CTTX1 RLV CS CTTX2 FTTX CFL RTTX CAC ILTF RD DET D0 D1 D2 PD CKTTX RTH RLIM IREF RREF RLIM RTH CLK TIP RP RING CSVR CREV CREV CSVR RING VBAT CVB RF1 CV RF2 ZAC1 TX AGND BGND CVCC VPOS GATE RSF RSENSE CSF R SENSE D1 Q1 N-ch
CZ
STLC3075
TIP
RTTX AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CTTX CAC
RD
CRD
D04TL625A
PGND
Figure 9.
Application diagram without metering pulse generation with N-channel
RX RRX TX
RS
RX RS ZAC
TX
CCOMP ZAC ZA
CH VDD
O
bs
let o
od Pr e
CONTROL INTERFACE DET D0 D1 D2 PD
RDD
ct u
ZB
(s)
ZB DET D0 D1 D2 PD 8RES 9RES 10RES 12RES
ZAC1
so Ob CVCC AGND BGND CVCC
VPOS CVPOS
te le
VPOS GATE RSENSE VBAT VF CZ
ro P
CSF
uc d
s) t(
T1 Q1 RSF N-ch RSENSE D1 CVB RF1 CV CZ RF2
GAIN SET
STLC3075
CLK RP TIP RP RING CSVR CREV
CLK TIP RING
CREV RTH RLIM IREF RREF 11RES CAC ILTF RD RLIM
CSVR
RTH
RD AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CAC
CRD
D04TL626
PGND
20/36
STLC3075 Figure 10. Application diagram with P-channel
CVCC RX RRX TX VPOS CVPOS RSENSE
Functional description
RS
RX RS ZAC
TX
AGND BGND
CVCC
VPOS RSENSE GATE D1 VBAT CVB RF1 CV RF2 L Q1 P-ch
CCOMP ZAC ZA
ZAC1
ZB CH VDD RDD GAIN SET ZB
VF
CLK TIP
CLK RP TIP RP RING
STLC3075
CONTROL INTERFACE DET D0 D1 D2 PD TTX CLOCK RLV CTTX1 RLV CS CTTX2 FTTX CFL RTTX CAC ILTF RD DET D0 D1 D2 PD CKTTX
RING
CSVR CREV CREV RTH RLIM IREF RREF RLIM RTH CSVR
RTTX AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CTTX CAC
RD
CRD
D01TL493B
PGND
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
21/36
Functional description Figure 11. Application diagram without metering pulse generation
CVCC RX RRX TX VPOS CVPOS RSENSE
STLC3075
RS
RX RS ZAC
TX
AGND BGND
CVCC
VPOS RSENSE GATE D1 VBAT CVB RF1 CV RF2 L Q1 P-ch
CCOMP ZAC ZA
ZAC1
ZB CH VDD RDD ZB
VF
CLK GAIN SET
CLK RP TIP RP RING
STLC3075
CONTROL INTERFACE DET D0 D1 D2 PD DET D0 D1 D2 PD CKTTX CTTX1 CTTX2 FTTX RTTX CAC ILTF RD
TIP RING
CSVR CREV CREV RTH RLIM IREF RREF RLIM RTH CSVR
RD AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CAC
CRD
PGND
(*) Buckboost configuration.
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
D01TL494B
s) t(
22/36
STLC3075
Electrical characteristics
4
Electrical characteristics
Test conditions: VPOS = 6.0V, AGND = BGND, normal polarity, Tamb = 25C. External components as listed in the 'Typical values' column of the above external components tables.
Note:
Testing of all parameters is performed at 25C. Characterization as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range of: -40 to +85C.
Table 13.
Symbol VPOS A/BGND Vdig Tj Vbtot (1) ESD rating Charged device model
Absolute maximum ratings
Parameter Positive supply voltage AGND to BGND Pin D0, D1, D2, DET, CKTTX Max. junction temperature Vbtot=|VPOS|+|Vbat|. (Total voltage applied to the device supply pins). Human body model Value -0.4 to +13 -1 to +1 -0.4 to 5.5 150 90 Unit V V
1. Vbat is self generated by the on-chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 must be selected in order to fulfil the a.m. limits (see components tables).
Table 14.
Symbol VPOS A/BGND Vdig Top Vbat(1)
Operating range
Parameter Positive supply voltage AGND to BGND
Pin D0, D1, D2, DET, CKTTX, PD Ambient operating temperature range Self generated battery voltage
O
bs
let o
1. Vbat is self generated by the on-chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 must be selected in order to fulfil the a.m. limits (see Table 6: External components for buckboost configuration)
Table 15.
ro P e
Symbol Rth j-amb
uc d
(s) t
so Ob -
eP let
od r
1750 500
uc
s) t(
V V V
V
C
Value 4.5 to +12 -100 to +100 -0.25 to 5.25 -40 to +85 -74 max.
Unit V mV V C V
Thermal data
Parameter Thermal resistance junction to ambient typical. Value 60 Unit C/W
23/36
Electrical characteristics Table 16.
Symbol DC characteristics Il = 0 HI-Z (High impedance feeding) Tamb = 0C to 85C Il = 0 HI-Z (High impedance feeding) Tamb = -40C to 85C Il = 0, Active mode, Tamb = 0C to 85C Il = 0, active mode, Tamb = -40C to 85C Active mode Active mode Rel. to programmed value 20mA to 40mA HI-Z (High Impedance feeding)
STLC3075
Electrical characteristics
Parameter Test condition Min. Typ. Max. Unit
Vlohi
Line voltage
44
50
V
Vlohi
Line voltage
42
48
V
Vloa
Line voltage
33
40
V
Vloa Ilim Ilima Rfeed HI
Line voltage Lim. current programming range Lim. current accuracy Feeding resistance
31 20 -10 2.4
37 40
V
AC characteristics Long. to transv. (see appendix for test circuit) Transv. to long. (see appendix for test circuit) Transv. to long. (see appendix for test circuit) 2W return loss
L/T
Rp = 50 1% tolerance , Active N. P., RL = 600 (*) f = 300 to 3400Hz Rp = 50 1% tolerance , Active N. P., RL = 600 (*) f = 300 to 3400Hz Rp = 50 1% tolerance , Active N. P., RL = 600 (*) f = 1kHz
T/L
T/L
2WRL
THL
bs O
Ovl G24 G42
let o
Trans-hybrid loss
Pr e
du o
(s) ct
Ob -
so
eP let
od r
50 40
uc
s) t(
10
mA %
3.6
k
58
dB
45
dB
48
53
dB
300 to 3400Hz Active N. P., RL = 600 (*) 300 to 3400Hz 20Log|VRX/VTX| Active N. P., RL = 600 (*) At line terminals on ref. imped. Active N. P., RL = 600 (*) Active N. P., RL = 600 (*) 0dBm @ 1020Hz Active N. P., RL = 600 (*) 0dBm @ 1020Hz Active N. P., RL = 600 (*)
22
26
dB
30
dB
2W overload level TX output offset Transmit gain abs. Receive gain abs.
3.2 -250 -6.4 -0.4 250 -5.6 0.4
dBm mV dB dB
TXoff
24/36
STLC3075 Table 16.
Symbol
Electrical characteristics Electrical characteristics (continued)
Parameter Test condition Rel. 1020Hz; 0dBm 300 to 3400Hz Active N. P., RL = 600 (*) Rel. 1020Hz; 0dBm 300 to 3400Hz Active N. P., RL = 600 (*) Min. Typ. Max. Unit
G24f
TX gain variation vs. frequency
-0.12
0.12
dB
G24f
RX gain variation vs. freq.
-0.12
0.12
dB
V2Wp
Psophometric filtered Idle channel noise at line 0dB gain Active N. P., RL = 600 (*) set Tamb = 0 to +85C Psophometric filtered Idle channel noise at line 0dB gain Active N. P., RL = 600 (*) set Tamb = -40 to +85C Psophometric filtered Idle channel noise at line 0dB gain Active N. P., RL = 600 (*) set Tamb = 0 to +85C Psophometric filtered Idle channel noise at line 0dB gain Active N. P., RL = 600 (*) set Tamb = -40 to +85C Total harmonic distortion Metering pulse level on line CLK operating range Active N. P., RL = 600 (*)
-73
-6 8
dBmp
V2Wp
-68
dBmp
V4Wp
-75
-7 0
V4Wp Thd VTTX CLKfreq
Active - TTX; Gain Set = 1 Zl = 200 fttx = 12kHz
(*) RL: Line resistance
Ring
Vr ing
Line voltage
bs O
Vr ing
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
260 -1 0 %
uc d
-75 340 125
s) t(
dBmp
dBmp dB mVr ms
-4 4
10%
kHz
RING D2 toggling @ fr = 25Hz Load = 3REN Crest Factor = 1.25 1REN = 1800 + 1.0F Tamb = 0 to +85C RING D2 toggling @ fr = 25Hz Load = 3REN Crest Factor = 1.25 1REN = 1800 + 1.0F Tamb = -40 to +85C
45
49
Vrms
Line voltage
44
48
Vrms
25/36
Electrical characteristics Table 16.
Symbol Detectors IOFFTHA Off/hook current threshold ROFTHA IONTHA Off/hook loop resistance threshold On/hook current threshold Active mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Active mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Active mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Active mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) 8 10.5 10.5
STLC3075
Electrical characteristics (continued)
Parameter Test condition Min. Typ. Max. Unit
mA 3.4 6 k mA k mA 800
RONTHA On/hook loop resistance threshold IOFFTHI Off/hook current threshold
ROFFTHI Off/hook loop resistance threshold IONTHI RONTHI Ir t Ir ta Tr td Td Rlr t(1) ThAl On/hook current threshold On/hook loop resistance threshold
Ring trip detector threshold range RING Ring trip detector threshold accuracy Ring trip detection time Dialling distortion Loop resistance Tj for th. alarm activation RING
RING
Active mode
(1) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection.
Digital interface Inputs: D0, D1, D2, PD, CLK Outputs: DET Vih Vil Iih In put high voltage
bs O
Iil Vol
let o
Input low voltage -10 -10 Iol = 1mA
Input high current
Pr e
du o
(s) ct
so Ob -
eP let
od r
8 20 -1
uc
s) t(
6 50 15
mA k
mA % ms
-15 TBD
1 500 160
ms C
2 0.8 10 10 0.45
V V A A V
Input low current Output low voltage
26/36
STLC3075 Table 16.
Symbol
Electrical characteristics Electrical characteristics (continued)
Parameter Test condition Min. Typ. Max. Unit
PSRR and power consumption PSERRC Power supply rejection VPOS to 2W port Vripple = 100mVrms 50 to 4000Hz HI-Z on-hook Active on-hook RING (line open) RING off-hook RSENSE = 110m -20% 26 36 13 50 55 900 25 80 90 dB mA mA mA
Ivpos
VPOS supply current @ II = 0
Ipk(1)
Peak current limiting accuracy
+20% mApk
1. Buck-Boost configuration
bs O
let o
Pr e
du o
(s) ct
so Ob -
te le
ro P
uc d
s) t(
27/36
Package mechanical data
STLC3075
5
Package mechanical data
Figure 12. Mecanical data and package dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
0 (min.), 3.5(typ.), 7(max.)
D
33
bs O
let o
ro P e
B
44
34
du
(s) ct
D1
so Ob 23 22
te le
TQFP44 (10 x 10 x 1.4mm)
ro P
uc d
s) t(
A A2 A1
0.10mm .004 Seating Plane
E1
12 1 11
E
B C L K
e
TQFP4410
0076922 D
28/36
STLC3075
Ordering information
6
Ordering information
Table 17. Order codes
Part number E-STLC3075 Package TQFP44
7
Revision history
Table 18.
Date 04-Oct-2004
Document revision history
Revision 1 Initial release Changes
04-Nov-2004
2
Removed all max. values of the `Line voltage' parameter on page 16/26. Changed the unit from mA to% of the `Ilima' parameter on page 16/26. Added pin 4 PD in applications and block diagram. Added Table 2 `ESD rating'. Changed figures 9 and 10. Changed VTTX value.
09-Feb-2005 22-Apr-2005 14-Jul-2005
3 4 5
07-Feb-2007
6
09-Mar-2007
bs O
let o
Pr e
du o
7
(s) ct
Added RRX resistance in the Figure 9 and Figure 10. Updated Section 3.1 and Section 3.2.4. Updated RSENSE value and Ipk maximum value in Table 11. Updated Figure 23. Added Coilcraft references (FA2469-AL and FA2470-AL) to T1 parameter inTable 8. Moved Table 13, Table 14 and Table 15 to Chapter 4: Electrical characteristics. Added precision on single supply voltage range for fly-back and buck boost configurations on page 1.
so Ob -
te le
ro P
uc d
s) t(
29/36
Measurement configurations
STLC3075
Appendix A
A.1
Measurement configurations
STLC3075 test circuits
Referring to the application diagram as shown on Figure 10: Application diagram with Pchannel and using the typical values from Table 6: External components for buckboost configuration and Table 11: External components @gain set = 0 find below the proper configuration for each measurement. All measurements requiring DC current termination should be performed using 'Wandel & Glittering' DC Loop Holding Circuit GH-1' or equivalent. Figure 13. 2W return loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)
W&G GH1 Zref TIP 600ohm Vs 1Kohm 100mA DC mac E Zin = 100K 200 to 6kHz 1Kohm 100F 100F TX
STLC3075 application circuit
Figure 14. THL trans hybrid loss THL = 20Log|Vrx/Vtx/
W&G GH1
bs O
let o
Pr e
od
600ohm
uc
100mA DC mac
(s) t
100F 100F
so Ob TIP
te le
ro P
RING
TX
uc d
s) t(
RX
Vtx
STLC3075 application circuit
Zin = 100K 200 to 6kHz
RING
RX Vrx
30/36
STLC3075 Figure 15. G24 transmit gain G24 = 20Log|2Vtx/E|
W&G GH1 TIP 100F
100mA DC max Zin = 100K 200 to 6kHz
Measurement configurations
TX Vt x
600ohm
STLC3075 application circuit
E
100F RING RX
Figure 16. G42 receive gain G42 = 20Log|VI/Vrx|
W&G GH1 TIP 100F Vl 600ohm
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3075 application circuit
100F RING RX
Figure 17. PSRRC power supply rejection VPOS to 2W port PSSRC = 20Log|Vn/Vl|
Vl
bs O
let o
ro P e
uc d
(s) t
600ohm
Zin = 100K 200 to 6kHz
so Ob W&G GH1 100F
100mA DC max
eP let
TIP TX
ro
Vrx
uc d
s) t(
STLC3075 application circuit
100F RING VPOS RX
~
Vn
31/36
Measurement configurations Figure 18. L/T longitudinal to transversal conversion L/T = 20Log|Vcm/Vl|
W &G GH1 300ohm 100F TIP 100F
100mA DC max
STLC3075
TX
Impedance matching better than 0.1%
Vcm
Vl
Zin = 100K 200 to 6kHz
STLC3075 application circuit
100F RING RX
300ohm
100F
Figure 19. T/L transversal to longitudinal conversion T/L = 20Log|Vrx/Vcm|
100F W&G GH1 TIP 100F
100mA DC max Impedance matching better than 0.1% Zin = 100K 200 to 6kHz
300ohm
TX
STLC3075 application circuit
600ohm
Vcm
100F
300ohm
100F
Figure 20. VTTX metering pulse level on line
bs O
let o
Pr e
du o
(s) ct
Vlttx
so Ob TIP 200ohm RING
te le
TX
RING
ro P
RX
uc d
Vrx
s) t(
STLC3075 application circuit
RX CKTTX fttx (12 or 16kHz)
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STLC3075
Measurement configurations Figure 21. V2Wp and W4Wp: Idle channel sophometric noise at line and TX. V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l|
W&G GH1 TIP 100F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx psophometric filtered
600ohm Vl psophometric filtered
STLC3075 application c i rcu i t
100F RING RX
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Over voltage protection
STLC3075
Appendix B
Over voltage protection
Figure 22. Simplified configuration for indoor over voltage protection
BGND STPR120A
STLC3075
TIP SM6T39A 2x RI NG RP1 RP1 RP 2 RP2 TIP RING
VBAT STPR120A
RP1 = 30ohm: RP2 =Fuse or PTC > 18ohm
Figure 23. Standard over voltage protection configuration for K20 compliance
BGND
STLC3075
TI P 2x SM6T39A
RP1
LCP1521S
RP2
RING
RP1
VBAT
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RING
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STLC3075
Typical state diagram
Appendix C
Typical state diagram
Figure 24. Typical state diagram for STLC3075 operation
Normally used for On Hook Transmission Tj>Tth PD=0, D0=D1=0 Active On Hook Ring Pause D0=0, D1=1, D2=0
Power Down
Ring Burst
Ring Burst D0=1, D1=0, D2=0/1 PD=1, D0=D1=0 HI-Z Feeding Active Off Hook Off Hook Detection D0=0, D1=1, D2=0 Ringing
On Hook Detection for T>Tref Ring Trip Detection
On Hook Condition
Off Hook Detection
Note: all state transitions are under the microprocessor control.
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STLC3075
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