STR750Fxx STR751Fxx STR752Fxx STR755Fxx
ARM7TDMI-STM 32-bit MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
Features
Core ARM7TDMI-S 32-bit RISC CPU 54 DMIPS @ 60 MHz Memories Up to 256 KB Flash program memory (10k W/E cycles, retention 20 yrs @ 85C) 16 KB Read-While-Write Flash for data (100k W/E cycles, retention 20 yrs@ 85C) Flash Data Readout and Write Protection 16KBytes embedded high speed SRAM Memor y mapped interface (SMI) to ext. Serial Flash (64 MB) w. boot capability Clock, reset and supply management Single supply 3.3V 10% or 5V 10% Embedded 1.8V Voltage Regulators Int. RC for fast start-up and backup clock Up to 60 MHz operation using internal PLL with 4 or 8 MHz crystal/ceramic osc. Smar t Low Power Modes: SLOW, WFI, STOP and STANDBY with backup registers Real-time Clock, driven by low power internal RC or 32.768 kHz dedicated osc, for clock-calendar and Auto Wake-up Nested interrupt controller Fast interrupt handling with 32 vectors 16 IRQ priorities, 2 maskable FIQ sources 16 external interrupt / wake-up lines DMA 4-channel DMA controller Circular buffer management Suppor t for UART, SSP, Timers, ADC 6 Timers 16-bit watchdog timer (WDG) 16-bit timer for system timebase functions 3 synchronizable timers each with up to 2 input captures and 2 output compare/PWMs.
LQFP64 10x10 mm
LQFP100 14 x 14 mm
LFBGA64 8 x 8 x 1.7 mm
LFBGA100 10 x 10 x 1.7 mm
16-bit 6-ch. synchronizable PWM timer Dead time generation, edge/center-aligned waveforms and emergency stop Ideal for induction/brushless DC motors 8 Communications interfaces 1 I2C interface 3 HiSpeed UARTs w. Modem/LIN capability 2 SSP interfaces (SPI or SSI) up to 16 Mb/s 1 CAN interface (2.0B Active) 1 USB full-speed 12 Mb/s interface with 8 configurable endpoint sizes 10-bit A/D converter 16/11 chan. with prog. Scan Mode & FIFO Programmable Analog Watchdog feature Conversion time: min. 3.75 s Star t conversion can be triggered by timers Up to 72/38 I/O ports 72/38 GPIOs with High Sink capabilities Atomic bit SET and RES operations Device summary
Root part number
Table 1.
Reference
STR750Fxx STR750FV0, STR750FV1, STR750FV2 STR751Fxx STR751FR0, STR751FR1, STR751FR2 STR752Fxx STR752FR0, STR752FR1, STR752FR2 STR755Fxx STR755FR0, STR755FR1, STR755FR2 STR755FV0, STR755FV1, STR755FV2
October 2007
Rev 4
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www.st.com 1
Contents
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Contents
1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.0.1 Pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I/O characteristics versus the various power schemes (3.3V or 5.0V) . 29 Current consumption measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.1 5.2.2 5.2.3 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35 Embedded voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Contents
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TB and TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 80
7 8
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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Description
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
1
Description
The STR750 family of 32-bit microcontrollers combines the industry-standard ARM7TDMI 32-bit RISC core, featuring high performance, very low power, and very dense code, with a comprehensive set of peripherals and ST's latest 0.18 embedded Flash technology. The STR750 family comprises a range of devices integrating a common set of peripherals as well as USB, CAN and some key innovations like clock failure detection and an advanced motor control timer. It supports both 3.3V and 5V, and it is also available in an extended temperature range (-40 to +105C). This makes it a genuine general purpose microcontroller family, suitable for a wide range of applications:
Appliances, brushless motor drives USB peripherals, UPS, alarm systems Programmable logic controllers, circuit breakers, inverters Medical and portable equipment
2
Table 2.
Device overview
Device overview
STR755FR0 STR755FR1 STR755FR2 STR751FR0/ STR751FR1/ STR751FR2 STR752FR0/ STR752FR1/ STR752FR2 STR755FV0 STR755FV1/ STR755FV2 STR750FV0/ STR750FV1/ STR750FV2
Features Flash - Bank 0 (bytes) Flash - Bank 1 (bytes) RAM (bytes) Operating Temperature. Common Peripherals USB/CAN peripherals Operating Voltage Packages (x)
64K/128K/256K 16K RWW 16K Ambient temp.:-40 to +85C / -40 to +105C (see Table 49) Junction temp. -40 to + 125 C (see Table 10) 3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, 38 I/Os 13 Wake-up lines, 11 A/D Channels None 3.3V or 5V USB 3.3V CAN 3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, 72 I/Os 15 Wake-up lines, 16 A/D Channels None 3.3V or 5V T=LQFP100 14x14, H=LFBGA100 USB+CAN
T=LQFP64 10x10, H=LFBGA64
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Introduction
3
Introduction
This Datasheet contains the description of the STR750F family features, pinout, Electrical Characteristics, Mechanical Data and Ordering information. For complete information on the Microcontroller memory, registers and peripherals. Please refer to the STR750F Reference Manual. For information on the ARM7TDMI-S core please refer to the ARM7TDMI-S Technical Reference Manual available from Arm Ltd. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual For information on third-party development tools, please refer to the http://www.st.com/mcu website.
3.1
Functional description
The STR750F family includes devices in 2 package sizes: 64-pin and 100-pin. Both types have the following common features:
ARM7TDMI-STM core with embedded Flash & RAM
STR750F family has an embedded ARM core and is therefore compatible with all ARM tools and software. It combines the high performance ARM7TDMI-STM CPU with an extensive range of peripheral functions and enhanced I/O capabilities. All devices have on-chip highspeed single voltage FLASH memory and high-speed RAM. Figure 1 shows the general block diagram of the device family.
Embedded Flash memory
Up to 256 KBytes of embedded Flash is available in Bank 0 for storing programs and data. An additional Bank 1 provides 16 Kbytes of RWW (Read While Write) memory allowing it to be erased/programmed on-the-fly. This partitioning feature is ideal for storing application parameters.
When configured in burst mode, access to Flash memory is performed at CPU clock speed with 0 wait states for sequential accesses and 1 wait state for random access (maximum 60 MHz). When not configured in burst mode, access to Flash memory is performed at CPU clock speed with 0 wait states (maximum 32 MHz)
Embedded SRAM
16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
Enhanced interrupt controller (EIC)
In addition to the standard ARM interrupt controller, the STR750F embeds a nested interrupt controller able to handle up to 32 vectors and 16 priority levels. This additional hardware block provides flexible interrupt management features with minimal interrupt latency.
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Introduction
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Serial memory interface (SMI)
The Serial Memory interface is directly able to access up to 4 serial FLASH devices. It can be used to access data, execute code directly or boot the application from external memory. The memory is addressed as 4 banks of up to 16 Mbytes each.
Clocks and start-up
After RESET or when exiting from Low Power Mode, the CPU is clocked immediately by an internal RC oscillator (FREEOSC) at a frequency centered around 5 MHz, so the application code can start executing without delay. In parallel, the 4/8 MHz Oscillator is enabled and its stabilization time is monitored using a dedicated counter. An oscillator failure detection is implemented: when the clock disappears on the XT1 pin, the circuit automatically switches to the FREEOSC oscillator and an interrupt is generated. In Run mode, the AHB and APB clock speeds can be set at a large number of different frequencies thanks to the PLL and various prescalers: up to 60 MHz for AHB and up to 32 MHz for APB when fetching from Flash (64 MHz and 32 MHz when fetching from SRAM). In SLOW mode, the AHB clock can be significantly decreased to reduce power consumption. The built-in Clock Controller also provides the 48 MHz USB clock directly without any extra oscillators or PLL. For instance, starting from the 4 MHz crystal source, it is possible to obtain in parallel 60 MHz for the AHB clock, 48 MHz for the USB clock and 30 MHz for the APB peripherals.
Boot modes
At start-up, boot pins are used to select one of five boot options:
Boot from internal flash Boot from external serial Flash memory Boot from internal boot loader Boot from internal SRAM
Booting from SMI memory allows booting from a serial flash. This way, a specific boot monitor can be implemented. Alternatively, the STR750F can boot from the internal boot loader that implements a boot from UART.
Power supply schemes
You can connect the device in any of the following ways depending on your application.
Power Scheme 1: Single external 3.3V power source. In this configuration the VCORE supply required for the internal logic is generated internally by the main voltage regulator and the VBACKUP supply is generated internally by the low power voltage regulator. This scheme has the advantage of requiring only one 3.3V power source. Power Scheme 2: Dual external 3.3V and 1.8V power sources. In this configuration, the internal voltage regulators are switched off by forcing the VREG_DIS pin to high level. VCORE is provided externally through the V18 and V18REG power pins and VBACKUP through the V18_BKP pin. This scheme is intended to save power consumption for applications which already provide an 1.8V power supply. Power Scheme 3: Single external 5.0V power source. In this configuration the VCORE supply required for the internal logic is generated internally by the main voltage
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Introduction
regulator and the VBACKUP supply is generated internally by the low power voltage regulator. This scheme has the advantage of requiring only one 5.0V power source.
Power Scheme 4: Dual external 5.0V and 1.8V power sources. In this configuration, the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high level. VCORE is provided externally through the V18 and V18REG power pins and VBACKUP through the V18_BKP pin. This scheme is intended to provide 5V I/O capability.
Caution:
When powered by 5.0V, the USB peripheral cannot operate.
Low power modes
The STR750F supports 5 low power modes, SLOW, PCG, WFI, STOP and STANDBY.
SLOW MODE: the system clock speed is reduced. Alternatively, the PLL and the main oscillator can be stopped and the device is driven by a low power clock (fRTC). The clock is either an external 32.768 kHz oscillator or the internal low power RC oscillator. PCG MODE (Peripheral Clock Gating MODE): When the peripherals are not used, their APB clocks are gated to optimize the power consumption. WFI MODE (Wait For Interrupts): only the CPU clock is stopped, all peripherals continue to work and can wake-up the CPU when IRQs occur. STOP MODE: all clocks/peripherals are disabled. It is also possible to disable the oscillators and the Main Voltage Regulator (In this case the VCORE is entirely powered by V18_BKP). This mode is intended to achieve the lowest power consumption with SRAM and registers contents retained. The system can be woken up by any of the external interrupts / wake-up lines or by the RTC timer which can optionally be kept running. The RTC can be clocked either by the 32.768 kHz Crystal or the Low Power RC Oscillator. Alternatively, STOP mode gives flexibility to keep the either main oscillator, or the Flash or the Main Voltage Regulator enabled when a fast start after wake-up is preferred (at the cost of some extra power consumption). STANDBY MODE: This mode (only available in single supply power schemes) is intended to achieve the lowest power consumption even when the temperature is increasing. The digital power supply (VCORE) is completely removed (no leakage even at high ambient temperature). SRAM and all register contents are lost. Only the RTC remains powered by V18_BKP. The STR750F can be switched back from STANDBY to RUN mode by a trigger event on the WKP_STDBY pin or an alarm timeout on the RTC counter.
Caution:
It is important to bear in mind that it is forbidden to remove power from the VDD_IO power supply in any of the Low Power Modes (even in STANDBY MODE).
DMA
The flexible 4-channel general-purpose DMA is able to manage memory to memory, peripheral to memory and memory to peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. The DMA can be used with the main peripherals: UART0, SSP0, Motor control PWM timer (PWM), standard timer TIM0 and ADC.
RTC (real-time clock)
The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a
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periodic interrupt. It is clocked by an external 32.768 kHz oscillator or the internal low power RC oscillator. The RC has a typical frequency of 300 kHz and can be calibrated.
WDG (watchdog timer)
The watchdog timer is based on a 16-bit downcounter and 8-bit prescaler. It can be used as watchdog to reset the device when a problem occurs, or as free running timer for application time out management.
Timebase timer (TB)
The timebase timer is based on a 16-bit auto-reload counter and not connected to the I/O pins. It can be used for software triggering, or to implement the scheduler of a real-time operating system.
Synchronizable standard timers (TIM2:0)
The three standard timers are based on a 16-bit auto-reload counter and feature up to 2 input captures and 2 output compares (for external triggering or time base / time out management). They can work together with the PWM timer via the Timer Link feature for synchronization or event chaining. In reset state, timer Alternate Function I/Os are connected to the same I/O ports in both 64-pin and 100-pin devices. To optimize timer functions in 64-pin devices, timer Alternate Function I/Os can be connected, or "remapped", to other I/O ports as summarized in Table 3 and detailed in Table 6. This remapping is done by the application via a control register. Table 3. Standard timer alternate function I/Os
Number of alternate function I/Os Standard timer functions 100-pin package Input Capture TIM 0 Output Compare/PWM Input Capture TIM 1 Output Compare/PWM Input Capture TIM 2 Output Compare/PWM 2 1 2 2 2 1 2 1 2 2 2 1 1 2 1 2 64-pin package Default mapping 1 Remapped 2
Any of the standard timers can be used to generate PWM outputs. One timer (TIM0) is mapped to a DMA channel.
Motor control PWM timer (PWM)
The Motor Control PWM Timer (PWM) can be seen as a three-phase PWM multiplexed on 6 channels. The 16-bit PWM generator has full modulation capability (0...100%), edge or centre-aligned patterns and supports dead-time insertion. It has many features in common with the standard TIM timers which has the same architecture and it can work together with the TIM timers via the Timer Link feature for synchronization or event chaining.The PWM timer is mapped to a DMA channel.
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Introduction
I²C bus
The I²C bus interface can operate in multi-master and slave mode. It can support standard and fast modes (up to 400KHz).
High speed universal asynch. receiver transmitter (UART)
The three UART interfaces are able to communicate at speeds of up to 2 Mbit/s. They provide hardware management of the CTS and RTS signals and have LIN Master capability. To optimize the data transfer between the processor and the peripheral, two FIFOs (receive/transmit) of 16 bytes each have been implemented. One UART can be served by the DMA controller (UART0).
Synchronous serial peripheral (SSP)
The two SSPs are able to communicate up to 8 Mbit/s (SSP1) or up to 16 Mbit/s (SSP0) in standard full duplex 4-pin interface mode as a master device or up to 2.66 Mbit/s as a slave device. To optimize the data transfer between the processor and the peripheral, two FIFOs (receive/transmit) of 8 x 16 bit words have been implemented. The SSPs support the Motorola SPI or TI SSI protocols. One SSP can be served by the DMA controller (SSP0).
Controller area network (CAN)
The CAN is compliant with the specification 2.0 part B (active) with a bit rate up to 1Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Up to 32 message objects are handled through an internal RAM buffer. In LQFP64 devices, CAN and USB cannot be connected simultaneously.
Universal serial bus (USB)
The STR750F embeds a USB device peripheral compatible with the USB Full speed 12Mbs. The USB interface implements a full speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock source is generated from the internal main PLL. VDD must be in the range 3.3V10% for USB operation.
ADC (analog to digital converter)
The 10-bit Analog to Digital Converter, converts up to 16 external channels (11 channels in 64-pin devices) in single-shot or scan modes. In scan mode, continuous conversion is performed on a selected group of analog inputs. The minimum conversion time is 3.75 s (including the sampling time). The ADC can be served by the DMA controller. An analog watchdog feature allows you to very precisely monitor the converted voltage of up to four channels. An IRQ is generated when the converted voltage is outside the programmed thresholds. The events generated by TIM0, TIM2 and PWM timers can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers.
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GPIOs (general purpose input/output)
Each of the 72 GPIO pins (38 GPIOs in 64-pin devices) can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as Peripheral Alternate Function. Port 1.15 is an exception, it can be used as general-purpose input only or wake-up from STANDBY mode (WKP_STDBY). Most of the GPIO pins are shared with digital or analog alternate functions.
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Introduction
3.2
Block diagram
Figure 1.
BOOT1, BOOT0 as AF TEST NJTRST JTDI JTCK JTMS JTDO as AF
STR750 block diagram
ARM7TDMI-S CPU 60MHz AHB JTAG & ICE-RT GP DMA 4 streams AHB
BUS MATRIX
HRESETN PRESETN SRAM 16KB FLASH 256KB +16KB (RWW) NESTED INTERRUPT CTL CK_RTC CK_SYS HCLK PCLK CLOCK MANAGEMENT VDD_IO VCORE VBACKUP VDDA_PLL VDDA_ADC 32xIRQ 2xFIQ
RESET & POWER DC-DC 3.3V TO 1.8V MAIN LOW POWER
NRSTIN NRSTOUT VDD_IO V18 V18BKP VSS
Arbiter SCLK, MOSI MISO as AF 4 CS as AF SERIAL MEMORY INTERFACE
AHB LITE (up to 60MHz)
LP OSC OSC 32K FREE OSC PLL OSC 4M XT1 XT2 VDDA_PLL VSSA_PLL RTC_XT1 RTC_XT2
APB BRIDGE
CK_USB USB Full Speed
15AF P0[31:0] P1[19:0] P2[19:0] 16AF VDDA_ADC VSSA_ADC
EXT.IT WAKEUP GPIO PORT 0 GPIO PORT 1 GPIO PORT 2 10-bit ADC WATCHDOG RTC
USBDP USBDM RX,TX as AF RX,TX,CTS, RTS as AF RX,TX,CTS, RTS as AF RX,TX,CTS, RTS as AF MOSI,MISO, SCK,NSS as AF MOSI,MISO, SCK,NSS as AF SCL,SDA as AF
CAN 2.0B FIFO 2x(16x8bit) UART0 FIFO 2x(16x8bit) UART1 FIFO 2x(16x8bit) UART2 FIFO 2x(8x16bit) SSP0
TB TIMER 2xICAP, 2xOCMP as AF 2xICAP, 2xOCMP as AF 2xICAP, 2xOCMP as AF PWM1, PWM1N PWM2, PWM2N PWM3, PWM3N PWM_EMERGENCY as AF TIM0 TIMER TIM1 TIMER I2C TIM2 TIMER PWM TIMER APB (up to 32 MHz) FIFO 2x(8x16bit) SSP1
AF : a lter n a te function on I/O por t p in Note: I/Os shown for 100 pin devices. 64-pin devices have the I/O set shown in Figure 3.
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Pin description
Figure 2.
Pin description
ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1/ P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 TIM1_TI2 / P0.31 TIM1_OC2 / P0.30 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 TEST VSS_IO ADC_IN6 / UART1_RTS / P0.23 TIM2_OC1/ P2.04 UART1_RTS / P2.03 P2.02 ADC_IN5 / UART1_CTS / P0.22 UART1_TX / P0.21 UART1_RX / P0.20 JTMS / P1.19 JTCK / P1.18 JTDO / P1.17 JTDI / P1.16 NJTRST P2.01 P2.00 UART0_RTS / RTCK / P0.13
SMI_CS1 / ADC_IN2 / UART0_CTS / P0.12 SMI_CS2 / BOOT1 / UART0_TX / P0.11 SMI_CS3 / UART0_RX / P0.10 I2C_SDA / P0.09 I2C_SCL / P0.08 P2.19 P2.18 UART2_RTS / P2.17 ADC_IN12 / UART0_RTS P1.11 ADC_IN7 /UART2_RTS / P0.27 UART2_CTS / P0.26 UART2_TX / P0.25 UART2_RX / P0.24 ADC_IN4 / SSP1_NSS / USB_CK / P0.19 SSP1_MOSI / P0.18 ADC_IN3 / SSP1_MISO / P0.17 SSP1_SCLK / P0.16 P2.16 VDD_IO VDDA_PLL XT2 XT1 VSS_IO VSSA_PLL P2.15
= 16 A/D input channels = 15 External interrupts / Wake-up Lines
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
LQFP100 pinout
LQFP100
V18BKP I/Os
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VREG_DIS VSS_IO VSSA_ADC P2.10 P2.11 VDDA_ADC VDD_IO P1.02 / TIM2_OC2 P1.03 / TIM2_TI2 USB_DP USB_DN P0.14 / CAN_RX P0.15 / CAN_TX P2.12 P2.13 P1.15 / WKP_STDBY NRSTIN NRSTOUT XRTC2 XRTC1 V18BKP VSSBKP VSS18 V18REG P2.14
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P0.03 / TIM2_TI1 / ADC_IN1 VDD_IO VSS_IO VSS18 V18 P1.00 / TIM0_OC2 P1.01 / TIM0_TI2 P1.13 / ADC_IN14 P1.14/ ADC_IN15 P1.04 / PWM3N / ADC_IN9 P1.05 / PWM3 P1.06 / PWM2N/ ADC_IN10 P1.07 / PWM2 P1.08 / PWM1N/ ADC_IN11 P2.05 / PWM3N P2.06 / PWM3 P2.07 / PWM2N P2.08 / PWM2 P2.09 / PWM1N P1.09 / PWM1 P1.10 / PWM_EMERGENCY P0.04 / SMI_CS0 / SSP0_NSS P0.05 / SSP0_SCLK / SMI_CK P0.06 / SMI_DIN / SSP0_MISO P0.07 / SMI_DOUT / SSP0_MOSI
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 3. LQFP64 pinout
Pin description
ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1 / P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 TEST V SS_IO_4 UART1_TX / P0.21 UART1_RX / P0.20 JTMS / P1.19 JTCK / P1.18 JTDO / P1.17 JTDI / P1.16 NJTRST UART2_TX / UART0_RTS / RTCK / P0.13
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 V18BKP I/Os 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.09 / PWM1 P1.10 / PWM_EMERGENCY P0.04 / SMI_CS0 /SSP0_NSS P0.05 / SSP0_SCLK / SMI_CK P0.06 / SMI_DIN / SSP0_MISO P0.07 / SMI_DOUT / SSP0_MOSI VREG_DIS V SS_IO_2 V SSA_ADC VDDA_ADC VDD_IO_2 P1.03 / TIM2_TI2 P0.14 / CAN_RX or USB_DP P0.15 / CAN_TX or USB_DN NRSTIN NRSTOUT XRTC2 XRTC1 V 18BKP VSSBKP V SS18 V 18REG
P0.03 / TIM2_TI1 / ADC_IN1 V DD_IO_1 VSS_IO_1 V SS18 V18 P1.04 / PWM3N / ADC_IN9 P1.05 / PWM3 P1.06 / PWM2N / ADC_IN10 P1.07 / PWM2
= 11 A/D input channels = 13 External interrupts / Wake-up Lines
SMI_CS1 / ADC_IN2 / UART0_CTS / UART2_RX /P0.12 SMI_CS2 / BOOT1 / UART0_TX / P0.11 SMI_CS3 / UART0_RX / P0.10 I2C_SDA/ P0.09 I2C_SCL / P0.08 ADC_IN12 / UART0_RTS / P1.11 ADC_IN4 / SSP1_NSS / USB_CK / P0.19 SSP1_MOSI / P0.18 ADC_IN3 / SSP1_MISO / P0.17 SSP1_SCLK / P0.16 VDD_IO_3 VDDA_PLL XT2 XT1 VSS_IO_3 VSSA_PLL
P1.08 / PWM1N / ADC_IN11
13/84
Pin description Table 4.
1 A B C D E F G H J K P0.03 P1.12 P0.31 P0.29 P0.28 P2.03
STR750Fxx STR751Fxx STR752Fxx STR755Fxx LFBGA100 ball connections
2 3 4 P1.04 P1.05 V18 VSS18 5 6 7 P0.05 P0.04 VSS_IO VDD_IO 8 P0.06 P2.13 VSSA_ADC VDDA_ADC 9 P0.07 P1.03 P2.11 P2.12 10 P1.02 P2.10 USB_DP USB_DN P0.14 P0.15 XRTC2 XRTC1 VSS_IO
P1.13 P1.14 P0.02 P0.01 P0.00 VDD_IO P0.30 VSS_IO P0.23 P0.22 P0.21 P0.20
P1.06 P1.08 P1.07 P1.09 P1.10 P2.09 P1.01 P1.15
VSS_IO TEST P1.00 NRSTOUT VREG_DIS NRSTIN P2.02 P2.01 P2.19 P0.27 P0.18 P2.04 P2.05 P2.00 P2.07 P2.18 P2.17 P0.19 P0.26 P0.17 P0.16 P2.06 2.08 P0.24 P0.25 XT1 VSS18 V18REG P2.14 P2.15 XT2 VSSBKP V18BKP P2.16 VDD_IO
NJTRST P1.18 P1.19 P0.13 P0.11 P0.10 P1.16 P1.17 P0.12 P1.11 P0.09 P0.08
VDDA_PLL VSSA_PLL
Table 5.
LFBGA64 ball connections
1 2 VSS_IO VDD_IO P0.02 P0.28 P1.19 NJTRST P0.12 P0.09 3 P1.04 P1.05 P0.00 TEST P0.20 P1.16 P1.11 P0.08 4 P1.06 P1.07 V 18 VSS_IO P0.21 P1.17 P0.19 P0.17 5 P1.08 P1.09 VSS18 6 P0.05 P0.04 VDD_IO 7 P0.06 P1.10 VSS_IO 8 P0.07 P1.03 P0.14 P0.15 XRTC2 XRTC1
A B C D E F G H
P0.03 P1.12 P0.01 P0.29 P1.18 P0.13 P0.11 P0.10
VREG_DIS VDDA_ADC VSSA_ADC NRSTOUT V18REG VDD_IO P0.18 NRSTIN VSS18 VSS_IO P0.16 V18BKP VSSBKP
VDDA_PLL VSSA_PLL XT2 XT1
14/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Pin description
4.0.1
Pin description table
Legend / abbreviations for Table 6:
Type: Input levels: I = input, O = output, S = supply, All Inputs are LVTTL at VDD_IO = 3.3V+/-0.3V or TTL at VDD_IO = 5V 0.5V. In both cases, TT means VILmax =0.8V VIHmin=2.0V All inputs can be configured as floating or with internal weak pull-up or pull down (pu/pd) All Outputs can be configured as Open Drain (OD) or Push-Pull (PP) (see also note 6 below Table 6). There are 3 different types of Output with different drives and speed characteristics: O8: fmax = 40 MHz on CL=50pF and 8 mA static drive capability for VOL=0.4V and up to 20 mA for VOL=1.3V (seeOutput driving current on page 55) O4: fmax = 20 MHz on CL=50pF and 4 mA static drive capability for VOL=0.4V (seeOutput driving current on page 55) O2: fmax = 10 MHz on CL=50pF and 2 mA static drive capability of for VOL=0.4V (seeOutput driving current on page 55)
Inputs: Outputs:
External interrupts/wake-up lines: EITx
15/84
Pin description
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Port reset state
The reset state of the I/O ports is GPIO input floating. Exceptions are P1[19:16] and P0.13 which are configured as JTAG alternate functions:
The JTAG inputs (JTDI, JTMS and JTDI) are configured as input floating and are ready to accept JTAG sequences. The JTAG output JTDO is configured as floating when idle (no JTAG operation) and is configured in output push-pull only when serial JTAG data must be output. The JTAG output RTCK is always configured as output push-pull. It outputs '0' level during the reset phase and then outputs the JTCK input signal resynchronized 3 times by the internal AHB clock. The GPIO_PCx registers do not control JTAG AF selection, so the reset values of GPIO_PCx for P1[19:16] and P0. 13 are the same as other ports. Refer to the GPIO section of the STR750 Reference Manual for the register description and reset values. P0.11 and P0.00 are sampled by the boot logic after reset, prior to fetching the first word of user code at address 0000 0000h. When booting from SMI (and only in this case), the reset state of the following GPIOs is "SMI alternate function output enabled": P0.07 (SMI_DOUT) P0.05 (SMI_CLK) P0.04 (SMI_CS0) P0.06 (SMI_DIN)
Note that the other SMI pins: SMI_CS1,2,3 (P0.12, P0.11, P0.10) are not affected. To avoid excess power consumption, unused I/O ports must be tied to ground. Table 6.
Pin n LFBGA100(1) LFBGA64(2) Input Level
STR750F pin description
Usable in Standby Input Ext. int /Wake-up Output
LQFP100(1)
pu/pd
Pin name
Capability
LQFP64(2)
floating
OD
(3)
PP
Main function (after reset)
Type
Alternate function
1
B1
1
B1
P1.12 / ADC_IN13
I/O
TT
X
X
EIT12
O8
X
X
Port 1.12
ADC: Analog input 13 TIM2: Output Compare 1(4) ADC: Analog input 0
2
B2
2
P0.02 / C2 TIM2_OC1 / ADC_IN0 C1 P0.01 / TIM0_TI1 / MCO
I/O
TT
X
X
EIT0
O8
X
X
Port 0.02
3
B3
3
I/O
TT
X
X
O8
X
X
Port 0.01 Port 0.00 / Boot mode selection input 0 Port 0.31 Port 0.30
TIM0: Input Main Clock Capture / trigger Output / external clock 1
4
C2
4
P0.00 / C3 TIM0_OC1 / BOOT0 P0.31 / TIM1_TI2 P0.30 / TIM1_OC2
I/O
TT
X
X
O8
X
X
TIM0: Output Compare 1
5 6
C1 D2
I/O I/O
TT TT
X X
X X
O2 O2
X X
X X
TIM1: Input Capture / trigger / external clock 2 TIM1: Output Compare 2
16/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 6.
Pin n LFBGA100(1) LFBGA64(2) Input Level
Pin description
STR750F pin description (continued)
Usable in Standby Input Ext. int /Wake-up Output
LQFP100(1)
pu/pd
Pin name
Capability
LQFP64(2)
floating
OD
(3)
PP
Main function (after reset)
Type
Alternate function
7 8 9 10 11
D1 E1 E5 E4 E2
5 6 7 8
D1 D2
P0.29 / TIM1_TI1 / ADC_IN8 P0.28 / TIM1_OC1
I/O I/O I S I/O
TT TT
X X
X X
O2 O2
X X
X X
Port 0.29 Port 0.28
TIM1: Input Capture 1
ADC: Analog input 8
TIM1: Output Compare 1
D3 TEST D4 VSS_IO P0.23 / UART1_RTS / ADC_IN6 P2.04 / TIM2_OC1 P2.03 / UART1_RTS P2.02 P0.22 / UART1_CTS / ADC_IN5
Reserved, must be tied to ground Ground Voltage for digital I/Os TT X X O2 X X Port 0.23 UART1: Ready To Send output(4) TIM2: Output Compare 1(4) UART1: Ready To Send output(4) ADC analog input 6
12
F5
I/O
TT
X
X
O2
X
X
Port 2.04
13 14 15
F1 F4 E3
I/O I/O I/O
TT TT TT
X X X
X X X
O2 O2 O2
X X X
X X X
Port 2.03 Port 2.02 Port 0.22
UART1: Clear To Send input
ADC: Analog input 5
16 17
F2 F3
9 10
E4 E3
P0.21 / UART1_TX P0.20 / UART1_RX P1.19 / JTMS
I/O I/O
TT TT
X X
X X
O2 O2
X X
X X
Port 0.21 Port 0.20 JTAG mode selection input(6) JTAG clock input(6) JTAG data output(6) JTAG data input(6)
UART1: Transmit data output (remappable to P0.15)(4) UART1: Receive data input (remappable to P0.14)(4) Por t 1.19
18
G3
11
E2
I/O
TT
X
X
O2
X
X
19 20 21 22 23 24
G2 H3 H2 G1 G4 G5
12 13 14 15
E1 P1.18 / JTCK F4 P1.17 / JTDO F3 P1.16 / JTDI F2 NJTRST P2.01 P2.00
I/O I/O I/O I I/O I/O
TT TT TT TT TT TT
X X X
X X X
O2 O8 O2
X X X
X X X
Por t 1.18 Por t 1.17 Por t 1.16
JTAG reset input(5) X X X X O2 O2 X X X X Port 2.01 Port 2.00 Por t 0.13
25
H1
16
P0.13 / RTCK / F1 UART0_RTS UART2_TX
I/O
TT
X
X
O8
X
X
JTAG return clock output(6)
UART2: Transmit UART0: Ready To Send output(4) Data output (when remapped)(8)
17/84
Pin description Table 6.
Pin n LFBGA100(1) LFBGA64(2) Input Level
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
STR750F pin description (continued)
Usable in Standby Input Ext. int /Wake-up Output
LQFP100(1)
pu/pd
Pin name
Capability
LQFP64(2)
floating
OD
(3)
PP
Main function (after reset)
Type
Alternate function
26
J2
P0.12 / UART2_RX / 17 G2 UART0_CTS / ADC_IN2 / SMI_CS1
UART0: Clear To Send input I/O TT X X O4 X X Port 0.12 Serial Memory Interface: chip select output 1
ADC: Analog input 2 UART2: Receive Data input (when remapped)(8) Serial Memory Interface: chip select output 2 Serial Memory Interface: chip select output 3
27
J1
P0.11 / UART0_TX / 18 G1 BOOT1 / SMI_CS2 P0.10 / 19 H1 UART0_RX / SMI_CS3 20 H2 P0.09 / I2C_SDA 21 H3 P0.08 / I2C_SCL P2.19 P2.18 P2.17 / UART2_RTS P1.11 22 G3 /UART0_RTS ADC_IN12 P0.27 / UART2_RTS / ADC_IN7 P0.26 / UART2_CTS P0.25 / UART2_TX P0.24 / UART2_RX
I/O
TT
X
X
O4
X
X
Port 0.11/Boot mode selection input 1 Port 0.10 Port 0.09 Port 0.08 Port 2.19 Port 2.18 Port 2.17
UART0: Transmit data output
28 29 30 31 32 33
K1 K2 K3 H4 H5 H6
I/O I/O I/O I/O I/O I/O
TT TT TT TT TT TT
X X X X X X
X X X X X X
EIT4
O2 O4
X X X X X X
X X X X X X
UART0: Receive Data input I2C: Serial Data I2C: Serial clock
EIT3
O4 O2 O2 O2
UART2: Ready To Send output(4) UART0: Ready To Send output(4) UART2: Ready To Send output(8) ADC: Analog input 12 ADC: Analog input 7
34
J3
I/O
TT
X
X
EIT11
O8
X
X
Port 1.11
35
J4
I/O
TT
X
X
O2
X
X
Port 0.27
36 37 38
J6 J7 H7
I/O I/O I/O
TT TT TT
X X X
X X X
O2 O2 O2
X X X
X X X
Port 0.26 Port 0.25 Port 0.24
UART2: Clear To Send input UART2: Transmit data output (remappable to P0.13)(8) UART2: Receive data input (remappable to P0.12)(8) SSP1: Slave select input (remappable to P0.11)(8) USB: 48 MHz Clock input ADC: Analog input 4
39
J5
P0.19 / USB_CK / 23 G4 SSP1_NSS / ADC_IN4
I/O
TT
X
X
EIT6
O2
X
X
Port 0.19
40
K4
24 H5
P0.18 / SSP1_MOSI
I/O
TT
X
X
O2
X
X
Port 0.18
SSP1: Master out/slave in data (remappable to P0.10)(8) SSP1: Master in/slave out data (remappable to P0.09)(8) ADC: Analog input 3
41
K5
P0.17 / 25 H4 SSP1_MISO / ADC_IN3 26 H6 P0.16 / SSP1_SCLK
I/O
TT
X
X
O2
X
X
Port 0.17
42
K6
I/O
TT
X
X
O2
X
X
Port 0.16
SSP1: serial clock (remappable to P0.08)(8)
18/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 6.
Pin n LFBGA100(1) LFBGA64(2) Input Level
Pin description
STR750F pin description (continued)
Usable in Standby Input Ext. int /Wake-up Output
LQFP100(1)
pu/pd
Pin name
Capability
LQFP64(2)
floating
OD
(3)
PP
Main function (after reset)
Type
Alternate function
43 44 45 46 47 48 49 50 51
H9 J9 K9 K8 K7 J10 K10 J8 H8
P2.16 27 G5 VDD_IO 28 G7 VDDA_PLL 29 H7 XT2
I/O S S
TT
X
X
O2
X
X
Port 2.16 Supply voltage for digital I/Os Supply voltage for PLL 4 MHz main oscillator
30 H8 XT1 31 G6 VSS_IO 32 G8 VSSA_PLL P2.15 P2.14 S S I/O I/O TT TT X X X X O2 O2 X X X X Ground voltage for digital I/Os Ground voltage for PLL Port 2.15 Port 2.14 Stabilization for main voltage regulator. Requires external capacitors of at least 10F between V18REG and VSS18. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used,
52
G8
33
F5 V18REG
S
53 54
F8 F9
34 35
F6 VSS18 F7 VSSBKP
S S
Ground Voltage for the main voltage regulator Stabilization for low power voltage regulator. Ground Voltage for the low power voltage regulator. Requires external capacitors of at least 1F between V18BKP and VSSBKP. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used, X 32 kHz oscillator for Realtime Clock X
55
G9
36
E7 V18BKP
S
56 57 58 59 60 61 62 63 64 65 66
H10
37
F8 XRTC1 E8 XRTC2 E5 NRSTOUT E6 NRSTIN P1.15 / WKP_STDBY P2.13 P2.12 O I I I/O I/O I/O I/O I/O I/O TT TT TT TT TT TT X X X X X X X X X EIT5 EIT15 O2 O2 O2 O2 X X X X X X X X
G10 38 E7 E9 D6 B8 D9 F10 E10 D10 C10 39 40
X X X
Reset output Reset input Port 1.15 Port 2.13 Port 2.12 Port 0.15 Port 0.14 CAN: Transmit data output CAN: Receive data input Wake-up from STANDBY input pin
4 1 D8
(7) (7)
P0.15 / CAN_TX P0.14 / CAN_RX USB_DN USB_DP
4 2 C8
(7) (7)
4 1 D8
(7) (7)
USB: bidirectional data (data -) USB: bidirectional data (data +) TIM2: Input Capture / trigger / external clock 2 (remappable to P0.07)(8)
4 2 C8
(7) (7)
67
B9
43
B8 P1.03 / TIM2_TI2
I/O
TT
X
X
O2
X
X
Port 1.03
19/84
Pin description Table 6.
Pin n LFBGA100(1) LFBGA64(2) Input Level
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
STR750F pin description (continued)
Usable in Standby Input Ext. int /Wake-up Output
LQFP100(1)
pu/pd
Pin name
Capability
LQFP64(2)
floating
OD
(3)
PP
Main function (after reset)
Type
Alternate function
68 69 70 71 72 73 74 75 76
A10 D7 D8 C9 B10 C8 C7 E8 A9
P1.02 / TIM2_OC2 44 C6 VDD_IO 45 D6 VDDA_ADC P2.11 P2.10 46 D7 VSSA_ADC 47 C7 VSS_IO 48 D5 VREG_DIS 49 P0.07 / A8 SMI_DOUT / SSP0_MOSI A7 P0.06 / SMI_DIN / SSP0_MISO
I/O S S I/O I/O S S I I/O
TT
X
X
O2
X
X
Port 1.02
TIM2: Output compare 2 (remappable to P0.06)(8)
Supply Voltage for digital I/Os Supply Voltage for A/D converter TT TT X X X X O2 O2 X X X X Port 2.11 Port 2.10 Ground Voltage for A/D converter Ground Voltage for digital I/Os TT TT X X EIT2 O4 X X Voltage Regulator Disable input Port 0.07 Serial Memory Interface: data output Serial Memory Interface: data input SSP0: Serial clock Serial Memory Interface: chip select output 0 SSP0: Master out Slave in data SSP0: Master in Slave out data Serial Memory Interface: Serial clock output SSP0: Slave select input
77
A8
50
I/O
TT
X
X
O4
X
X
Port 0.06
78
A7
51
P0.05 / A6 SSP0_SCLK / SMI_CK B6 P0.04 / SMI_CS0 / SSP0_NSS
I/O
TT
X
X
EIT1
O4
X
X
Port 0.05
79
B7
52
I/O
TT
X
X
O4
X
X
Port 0.04
80 81 82 83 84 85 86
C5 B6 C6 G7 G6 F7 F6
53 54
P1.10 B7 PWM_EMERGE NC Y B5 P1.09 / PWM1 P2.09 / PWM1N P2.08 / PWM2 P2.07 / PWM2N P2.06 / PWM3 P2.05 / PWM3N P1.08 / PWM1N / ADC_IN11
I/O I/O I/O I/O I/O I/O I/O
TT TT TT TT TT TT TT
X X X X X X X
X X X X X X X
EIT10 EIT9
O2 O4 O2 O2 O2 O2 O2
X X X X X X X
X X X X X X X
Port 1.10 Port 1.09 Port 2.09 Port 2.08 Port 2.07 Port 2.06 Port 2.05
PWM: Emergency input PWM: PWM1 output PWM: PWM1 complementary output(4) PWM: PWM2 output(4) PWM: PWM2 complementary output(4) PWM: PWM3 output(4) PWM: PWM3 complementary output(4) PWM: PWM1 complementary output(8) ADC: analog input 11
87 88 89 90
A6 B5 A5 B4
55 56 57 58
A5
I/O I/O I/O I/O
TT TT TT TT
X X X X
X X X X EIT7 EIT8
O4 O4 O4 O4
X X X X
X X X X
Port 1.08 Port 1.07 Port 1.06 Port 1.05
B4 P1.07 / PWM2 A4 P1.06 / PWM2N / ADC_IN10
PWM: PWM2 output(4) PWM: PWM2 complementary output(4) ADC: analog input 10
B3 P1.05 / PWM3
PWM: PWM3 output(4)
20/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 6.
Pin n LFBGA100(1) LFBGA64(2) Input Level
Pin description
STR750F pin description (continued)
Usable in Standby Input Ext. int /Wake-up Output
LQFP100(1)
pu/pd
Pin name
Capability
LQFP64(2)
floating
OD
(3)
PP
Main function (after reset)
Type
Alternate function
91
A4
59
A3
P1.04 / PWM3N / ADC_IN9 P1.14 / ADC_IN15 P1.13 / ADC_IN14 P1.01 / TIM0_TI2 P1.00 / TIM0_OC2
I/O
TT
X
X
O4
X
X
Port 1.04
PWM: PWM3 complementary output(4)
ADC: analog input 9
92 93
A3 A2
I/O I/O
TT TT
X X
X X EIT13
O8 O8
X X
X X
Port 1.14 Port 1.13
ADC: analog input 15 ADC: analog input 14 TIM0: Input Capture / trigger / external clock 2 (remappable to P0.05)(8) TIM0: Output compare 2 (remappable to P0.04)(8)
94
D5
I/O
TT
X
X
O2
X
X
Port 1.01
95
E6
I/O
TT
X
X
O2
X
X
Port 1.00
96
C4
60 C4 V18
S
Stabilization for main voltage regulator. Requires external capacitors 33nF between V18 and VSS18. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used. Ground Voltage for the main voltage regulator. Ground Voltage for digital I/Os Supply Voltage for digital I/Os TT X X O2 X X Port 0.03 TIM2: Input Capture / trigger / external clock 1 ADC: analog input 1
97 98 99 100
D4 D3 C3 A1
61 C5 VSS18 62 63 64 A2 VSS_IO B2 VDD_IO A1 P0.03 / TIM2_TI1 / ADC_IN1
S S S I/O
1. For STR755FVx part numbers, the USB pins must be left unconnected. 2. The non available pins on LQPFP64 and LFBGA64 packages are internally tied to low level. 3. None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O pin and VDD_IO. 4. In the 100-pin package, this Alternate Function is duplicated on two ports. You can configure one port to use this AF, the other port is then free for general purpose I/O (GPIO), external interrupt/wake-up lines, or analog input (ADC_IN) where these functions are listed in the table. 5. It is mandatory that the NJTRST pin is reset to ground during the power-up phase. It is recommended to connect this pin to NRSTOUT pin (if available) or NRSTIN. 6. After reset, these pins are enabled as JTAG alternate function see (Port reset state on page 16). To use these ports as general purpose I/O (GPIO), the DBGOFF control bit in the GPIO_REMAP0R register must be set by software (in this case, debugging these I/Os via JTAG is not possible). 7. There are two different TQFP and BGA 64-pin packages: in the first one, pins 41 and 42 are mapped to USB DN/DP while for the second one, they are mapped to P0.15/CAN_TX and P0.14/CAN_RX. 8. For details on remapping these alternate functions, refer to the GPIO_REMAP0R register description.
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Pin description Figure 4.
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Required external capacitors when regulators are used
33 nF 33 nF 96 VSS18 V18 97 V 18BKP 5 5 VSSBKP 54 1F
61 60 VSS18 V18
V18BKP 36 VSSBKP 35 1F
LQFP100
V SS18
53 10 F
LQFP64
VSS18
V18REG 52 V DD_IO 44 1 F 33 nF
34 10 F
V18REG 33 V DD_IO 27 1 F
33 nF
D4 C4 VSS18 V18
V 18BKP G 9 VSSBKP F9 1F
C 5 C4 V SS18 V 1 8
V18BKP E7 VSSBKP F7 1F
LFBGA100
LFBGA64
V SS18 F8 10 F V18REG G8
V SS18
F6 10 F
V18REG F5 VDD_IO G5 1 F
V DD_IO J9 1 F
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Pin description
4.1
Memory map
Figure 5. Memory map
Peripheral Memory Space 32 Kbytes
0xFFFF FFFF 0xFFFF FC00 0xFFFF FBFF 0xFFFF F800 0xFFFF F7FF 0xFFFF F400 0xFFFF F3FF
0xE000 0000 0xDFFF FFFF
Addressable Memory Space 4 Gbytes
0xFFFF FFFF 0xFFFF 8000 APB TO ARM7 BRIDGE
32K
Reserved EIC EXTIT
1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K
7
FLASH Memory Space 128/256 Kbytes
0x2010 DFFF 0x2010 C000 0x2010 0017 0x2010 0000
0xFFFF F000 0xFFFF EFFF 0xFFFF EC00 0xFFFF EBFF
RTC DMA Reserved
6
0xC000 0000 0xBFFF FFFF
SystemMemory 8K Flash registers
0xFFFF E800 0xFFFF E7FF
24B
GPIO I/O Ports
0xFFFF E400 0xFFFF E3FF 0xFFFF E000 0xFFFF DFFF 0xFFFF DC00 0xFFFF DBFF
Reserved UART2 UART1 UART0 Reserved I2C Reserved CAN Reserved SSP1 SSP0 Reserved WDG Reserved USB Registers Reserved
5
0xA000 0000 0x9FFF FFFF
0xFFFF D800 0xFFFF D7FF 0x200C 0x200C 0x200C 0x200C 0x200C 4000 3FFF 2000 1FFF 0000 0xFFFF D400 0xFFFF D3FF
B1F1 B1F0
8K 8K
0xFFFF D000 0xFFFF CFFF 0xFFFF CC00 0xFFFF CBFF 0xFFFF C800 0xFFFF C7FF 0xFFFF C400 0xFFFF C3FF
4
0x9000 0013 0x9000 0000 0x83FF FFFF 0x8000 0000 0x7FFF FFFF
SMI Registers
20B 4 x 16M
SMI Ext. Memory
0xFFFF C000 0xFFFF BFFF 0xFFFF BC00 0xFFFF BBFF
3
0x6000 0047 0x6000 0000 0x5FFF FFFF CONF + MRCC
0xFFFF B800 0xFFFF B7FF 0xFFFF B400 0xFFFF B3FF
1K
0x2003 FFFF
0xFFFF B000 0xFFFF AFFF
B0F7(2)
64K
0xFFFF AC00 0xFFFF ABFF 0xFFFF A800 0xFFFF A7FF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
2
0x4000 3FFF 0x4000 0000 0x3FFF FFFF Internal SRAM
0x2003 0000 0x2002 FFFF
16K
0x2002 0000 0x2001 FFFF
B0F6(2)
64K
A400 A3FF A200 USB RAM 256 x16-bit A000 9FFF
Reserved
0xFFFF 9C00 0xFFFF 9BFF
PWM
1
0x2010 0017 0x2000 0000 0x1FFF FFFF Internal Flash
B0F5
64K
0xFFFF 9800 0xFFFF 97FF 0xFFFF 9400 0xFFFF 93FF
TIM2 TIM1
128K/256K+16K+32B
0x2001 0000 0x2000 FFFF
0xFFFF 9000 0xFFFF 8FFF
B0F4
0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 8000 7FFF 6000 5FFF 4000 3FFF 2000 1FFF 0000
32K 8K 8K 8K 8K
TIM0 TB Timer ADC Reserved
0xFFFF 8C00 0xFFFF 8BFF 0xFFFF 8800 0xFFFF 87FF 0xFFFF 8400 0xFFFF 83FF 0xFFFF 8000
0
0x0000 0000 Boot Memory(1)
B0F3 B0F2 B0F1 B0F0
128K/256K
(1) In internal Flash Boot Mode, internal FLASH is aliased at 0x0000 0000h (2) Only available in STR750Fx2 Reser ved
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
5
5.1
Electrical parameters
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TAmax (given by the selected temperature range). Data based on product characterisation, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA=25 C, VDD_IO=3.3 V (for the 3.0 VVDD_IO3.6 V voltage range) and V18=1.8 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
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Electrical parameters
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6. Figure 6. Pin loading conditions
STR7 PIN
CL=50pF
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7. Figure 7. Pin input voltage
STR7 PIN
VIN
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
5.1.6
Power supply schemes
When mentioned, some electrical parameters can refer to a dedicated power scheme among the four possibilities. The four different power schemes are described below.
Power supply scheme 1: Single external 3.3 V power source
Figure 8. Power supply scheme 1
V18_BKP
1F VSS_BKP
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
NORMAL MODE
VBACKUP
VREG_DIS V18
33nF
LOW POWER V LPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH V18
BACKUP CIRCUITRY OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
VSS18 V18REG
10F
VSS18
VDD_IO 3.3V
1F
+/-0.3V
VSS_IO
MAIN VMVREG = 1.8V VOLTAGE REGULATOR VIO=3.3V
OUT
VCORE
KERNEL LOGIC (CPU & DIGITAL & MEMORIES)
GP I/Os
IN
I/O LOGIC
VDD_PLL VSS_PLL VDD_ADC
3.3V PLL
3.3V
VSS_ADC ADCIN
ADC
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Electrical parameters
Power supply scheme 2: Dual external 1.8V and 3.3V supply
Figure 9. Power supply scheme 2
V18_BKP
VSS_BKP
VDD_IO
VREG_DIS
OFF
VBACKUP VLPVREG
V18 V18REG 1.8V VSS18 VDD_IO 3.3V
VSS_IO
LOW POWER VOLTAGE REGULATOR
BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
POWER SWITCH
OFF
+/-0.3V
MAIN VOLTAGE REGULATOR VIO=3.3V
OUT
VMVREG
VCORE
KERNEL (CORE & DIGITAL & MEMORIES)
GP I/Os I/O LOGIC
IN
VDD_PLL VSS_PLL
3.3V PLL
VDD_ADC
3.3V
VSS_ADC ADCIN
ADC
NOTE : THE EXTERNAL 3.3 V POWER SUPPLY MUST ALWAYS BE KEPT ON
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Power supply scheme 3: Single external 5 V power source
Figure 10. Power supply scheme 3
V18_BKP
1F VSS_BKP
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
NORMAL MODE
VBACKUP
VREG_DIS V18
33nF
LOW POWER V LPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH V18
BACKUP CIRCUITRY OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
VSS18 V18REG
10F
VSS18
VDD_IO 5.0V
1F
+/-0.5V
VSS_IO
MAIN VMVREG = 1.8V VOLTAGE REGULATOR VIO=5.0V
OUT
VCORE
KERNEL LOGIC (CPU & DIGITAL & MEMORIES)
GP I/Os
IN
I/O LOGIC
VDD_PLL VSS_PLL VDD_ADC
5.0V PLL
5.0V
VSS_ADC ADCIN
ADC
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Electrical parameters
Power supply scheme 4: Dual external 1.8 V and 5.0 V supply
Figure 11. Power supply scheme 4
V18_BKP
VSS_BKP
VDD_IO
VREG_DIS
OFF
VBACKUP VLPVREG
V18 V18REG 1.8V VSS18 VDD_IO 5.0V
VSS_IO
LOW POWER VOLTAGE REGULATOR
BACKUP CIRCUITRY (OSC32K, RTC WAKEUP LOGIC, BACKUP REGISTERS)
POWER SWITCH
OFF
+/-0.5V
MAIN VOLTAGE REGULATOR VIO=5.0V
OUT
VMVREG
VCORE
KERNEL (CORE & DIGITAL & MEMORIES)
GP I/Os I/O LOGIC
IN
VDD_PLL VSS_PLL VDD_ADC
5.0V PLL
5.0V
VSS_ADC ADCIN
ADC
NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON
5.1.7
I/O characteristics versus the various power schemes (3.3V or 5.0V)
Unless otherwise mentioned, all the I/O characteristics are valid for both
VDD_IO=3.0 V to 3.6 V with bit EN33=1 VDD_IO=4.5 V to 5.5 V with bit EN33=0
When VDD_IO=3.0 V to 3.6 V, I/Os are not 5V tolerant.
5.1.8
Current consumption measurements
All the current consumption measurements mentioned below refer to Power scheme 1 and 2 as described in Figure 12 and Figure 13
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 12. Power consumption measurements in power scheme 1 (regulators enabled)
VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins ballast regulator I33 transistor V18 pins (including V18BKP) I18 1.8V internal load 3.3V internal load IDDA_ADC PLL load ADC load
IDD 3.3V Supply
IDD is measured, which corresponds to the total current consumption : IDD = IDDA_PLL + IDDA_ADC + I33 + I18
Figure 13. Power consumption measurements in power scheme 2 (regulators disabled)
VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins 3.3V internal load IDDA_ADC PLL load ADC load
IDD_v33 3.3V Supply 1.8V Supply IDD_v18
V18 pins (including V18BKP)
I33
I18 IDD_v33 and IDD_v18 are measured which correspond to: IDD_v33 = IDDA_PLL + IDDA_ADC + I33 IDD_v18 = I18
1.8V internal load
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Electrical parameters
Figure 14. Power consumption measurements in power scheme 3 (regulators enabled)
VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins ballast regulator I50 transistor V18 pins (including V18BKP) I18 1.8V internal load 5.0V internal load IDDA_ADC PLL load ADC load
IDD 5.0V Supply
IDD is measured, which corresponds to the total current consumption : IDD = IDDA_PLL + IDDA_ADC + I50 + I18
Figure 15. Power consumption measurements in power scheme 4 (regulators disabled)
VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins 5.0V internal load IDDA_ADC PLL load ADC load
IDD_v50 5.0V Supply 1.8V Supply IDD_v18
V18 pins (including V18BKP)
I50
I18 IDD_v50 and IDD_v18 are measured which correspond to: IDD_v50= IDDA_PLL + IDDA_ADC + I50 IDD_v18 = I18
1.8V internal load
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
5.2
Absolute maximum ratings
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
5.2.1
Voltage characteristics
Table 7.
Symbol
Voltage characteristics
Ratings Mi n -0.3 -0.3 VSS-0.3 to VDD_IO+0.3 Max 6.5 2.0 VSS-0.3 to VDD_IO+0.3 50 25 50 see : Absolute maximum ratings (electrical sensitivity) on page 52 see : Absolute maximum ratings (electrical sensitivity) on page 52 mV Unit V
VDD_x - VSS_X(1) Including VDDA_ADC and VDDA_PLL V18 - VSS18 Digital 1.8 V Supply voltage on all V18 power pins (when 1.8 V is provided externally) Input voltage on any pin (2) Variations between different 3.3 V or 5.0 V power pins Variations between different 1.8 V power pins(3) Variations between all the different ground pins Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model)
VIN |VDDx| |V18x| |VSSX - VSS| VESD(HBM)
VESD(MM)
1. All 3.3 V or 5.0 V power (VDD_IO, VDDA_ADC, VDDA_PLL) and ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins must always be connected to the external 3.3V or 5.0V supply. When powered by 3.3V, I/Os are not 5V tolerant. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
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Electrical parameters
5.2.2
Current characteristics
Table 8.
Symbol IVDD_IO(1) IVSS_IO(1) IIO
Current characteristics
Ratings Total current into VDD_IO power lines (source) (2) Total current out of VSS ground lines (sink)
(2)
Maximum value 150 150 25 - 25
Unit
Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRSTIN pin IINJ(PIN) (3) & (4) IINJ(PIN)(3) Injected current on XT1 and XT2 pins Injected current on any other pin (5) pins) (5)
mA 5 5 5 25
Total injected current (sum of all I/O and control
1. The user can use GPIOs to source or sink high current (up to 20 mA for O8 type High Sink I/Os). In this case, the user must ensure that these absolute max. values are not exceeded (taking into account the RUN power consumption) and must follow the rules described in Section 5.3.8: I/O port pin characteristics on page 54. 2. All 3.3 V or 5.0 V power (VDD_IO, VDDA_ADC, VDDA_PLL) and ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins must always be connected to the external 3.3V or 5.0V supply. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
5.2.3
Thermal characteristics
Table 9.
Symbol TSTG TJ
Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value -65 to +150 150 Unit C C
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
5.3
5.3.1
Operating conditions
General operating conditions
Subject to general operating conditions for VDD_IO, and TA unless otherwise specified. Table 10.
Symbol
General operating conditions
Parameter Conditions Accessing SRAM with 0 wait states Accessing Flash in burst mode, TA85 C Min 0 0 Max 64 60 Unit
fHCLK
Internal AHB Clock frequency
Accessing Flash in burst mode TA>85 C Accessing Flash with 0 wait states Accessing Flash in RWW mode 0 0 0 3.0 4.5 1.65 LQFP100
56
MHz
32 16 32 3.6 5.5 1.95 434 444 mW 487 344 V MHz
fPCLK
Internal APB Clock frequency Standard Operating Voltage Power Scheme 1 & 2
VDD_IO
Standard Operating Voltage Power Scheme 3 & 4 Standard Operating Voltage Power Scheme 2 & 4
V18
PD
Power dissipation at TA= 85 C for suffix 6 or TA= 105 C for suffix 7(1)
LQFP64 LFBGA100 LFBGA64
Ambient temperature for 6 suffix Maximum power dissipation version Low power dissipation(2) TA Ambient temperature for 7 suffix Maximum power dissipation version Low power dissipation (2) 6 Suffix Version TJ Junction temperature range 7 Suffix Version
-40 -40 -40 -40 -40 -40
85 105 105 125 105 125
C C C C C C
1. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 6.2: Thermal characteristics on page 79). 2. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 6.2: Thermal characteristics on page 79).
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Electrical parameters
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA. Table 11.
Symbol tVDD_IO
Operating conditions at power-up / power-down
Parameter VDD_IO rise time rate V18 rise time rate (1) When 1.8 V power is supplied externally 20 20 Conditions Min(1) 20 20 Typ Max(1) Unit s/V ms/V s/V ms/V
tV18
1. Data guaranteed by characterization, not tested in production.
5.3.3
Embedded voltage regulators
Subject to general operating conditions for VDD_IO, and TA Table 12.
Symbol VMVREG VLPVREG
Embedded voltage regulators
Parameter MVREG power supply(1) LPVREG power supply(2) Voltage Regulators start-up time (to reach 90% of final V18 value) at VDD_IO power-up(3) Conditions load <150 mA load <10 mA VDD_IO rise slope = 20 s/V VDD_IO rise slope = 20 ms/V Min 1.65 1.30 Typ 1.80 1.40 80 35 Max 1.95 1.50 Unit V V s ms
tVREG_PWRUP(1)
1. VMVREG is observed on the V18, V18REG and V18BKP pins except in the following case: - In STOP mode with MVREG OFF (LP_PARAM13 bit). See note 2. - In STANDBY mode. See note 2. 2. In STANDBY mode, VLPVREG is observed on the V18BKP pin In STOP mode, VLPVREG is observed on the V18, V18REG and V18BKP pins. 3. Once VDD_IO has reached 3.0 V, the RSM (Regulator Startup Monitor) generates an internal RESET during this start-up time.
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
5.3.4
Supply current characteristics
The current consumption is measured as described in Figure 12 on page 30 and Figure 13 on page 30. Subject to general operating conditions for VDD_IO, and TA
Maximum power consumption
For the measurements in Table 13 and Table 14, the MCU is placed under the following conditions:
All I/O pins are configured in output push-pull 0 All peripherals are disabled except if explicitly mentioned. Embedded Regulators are used to provide 1.8 V (except if explicitly mentioned). Maximum power consumption in RUN and WFI modes
Parameter Conditions (1) Typ(2) Max (3) Unit
Table 13.
Symbol
IDD
External Clock with PLL multiplication, code running from RAM, all peripherals enabled in the 3.3V Supply current in MRCC_PLCKEN register: fHCLK=60 and 5V RUN mode MHz, fPCLK=30 MHz range Single supply scheme see Figure 12 / Figure 14 External Clock, code running from RAM: fHCLK=60 MHz, fPCLK=30 MHz 3.3V Supply current in Single supply scheme see and 5V WFI mode Figure 12./ Figure 14 range Parameter setting BURST=1, WFI_FLASHEN=1
80
90
mA
62
67
mA
1. The conditions for these consumption measurements are described at the beginning of Section 5.3.4. 2. Typical data are based on TA=25C, VDD_IO=3.3V or 5.0V and V18=1.8V unless otherwise specified. 3. Data based on product characterisation, tested in production at VDD_IO max and V18 max (1.95V in dual supply mode or regulator output value in single supply mode) and TA max.
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 14.
Symbol
Electrical parameters
Maximum power consumption in STOP and STANDBY modes
Max(3) Parameter Conditions (1) Typ(2) TA 25C 16 8 3 22 8 6 20 25 TA 85C 117 60 20 160 60 50 25 30 TA 105C 250 110 26 310 110 65 28 33 A Unit
LP_PARAM bits: ALL OFF(4) Single supply scheme see Figure 12. Supply current in STOP mode IDD LP_PARAM bits: ALL OFF Dual supply scheme see Figure 13. LP_PARAM bits: ALL OFF(4) Single supply scheme see Figure 10 LP_PARAM bits: ALL OFF Dual supply scheme see Figure 11 Supply current in STANDBY mode
3.3V range IDD_V18 IDD_V33 5V range IDD_V18 IDD_V50 3.3 V range
12 5 <1 15 5 3 10 15
A A A
RTC OFF 5V range
1. The conditions for these consumption measurements are described at the beginning of Section 5.3.4. 2. Typical data are based on TA=25C, VDD_IO=3.3V or 5.0V and V18=1.8V unless otherwise specified. 3. Data based on product characterisation, tested in production at VDD_IO max and V18 max (1.95V in dual supply mode or regulator output value in single supply mode). 4. In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4V, which significantly reduces the leakage currents.
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 16. Power consumption in STOP mode Figure 17. Power consumption in STOP mode in Single supply scheme (3.3 V Single supply scheme (5 V range) range)
300 250 I S t op (uA) 200 150 100 50 0 -40 25 45 55 Temp (C) 75 95 105 TYP (3.3V) I S t op (uA) MAX (3.6V) 350 300 250 200 150 100 50 0 -40 25 45 55 Temp (C) 75 95 105 TYP (5.0V) MAX (5.5V)
Figure 18. Power consumption in STANDBY mode (3.3 V range)
30 25 I St andby (uA) 20 15 10 5 0 -40 25 Temp (C) 105 TYP (3.3V)
Figure 19. Power consumption in STANDBY mode (5 V range)
35 30 I St andby (uA) 25 20 15 10 5 0 -40 25 Temp (C) 105 TYP (5.0V) MAX (5.5V) MAX (3.6V)
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
Typical power consumption
The following measurement conditions apply to Table 15, Table 16 and Table 17. In RUN mode:
Program is executed from Flash (except if especially mentioned). The program consists of an infinite loop. When fHCLK > 32 MHz, burst mode is activated. A standard 4 MHz crystal source is used. In all cases the PLL is used to multiply the frequency. All measurements are done in the single supply scheme with internal regulators used (see Figure 12) In WFI Mode the measurement conditions are similar to RUN mode (OSC4M and PLL enabled). In addition, the Flash can be disabled depending on burst mode activation: For AHB frequencies greater than 32 MHz, burst mode is activated and the Flash is kept enabled by setting the WFI_FLASH_EN bit (this bit cannot be reset when burst mode is activated). For AHB frequencies less than or equal to 32 MHz, burst mode is deactivated, WFI_FLASH_EN is reset and the LP_PARAM14 bit is set (Flash is disabled in WFI mode).
In WFI Mode:
In SLOW mode:
The same program as in RUN mode is executed from Flash. The CPU is clocked by the FREEOSC, OSC4M, LPOSC or OSC32K. Only EXTIT peripheral is enabled in the MRCC_PCLKEN register. In SLOW-WFI, the measurement conditions are similar to SLOW mode (CPU clocked by a low frequency clock). In addition, the LP_PARAM14 bit is set (FLASH is OFF). The WFI routine itself is executed from SRAM (it is not allowed to execute a WFI from the internal FLASH) Several measurements are given: in the single supply scheme with internal regulators used (see Figure 12): and in the dual supply scheme (see Figure 13). Three measurements are given: The RTC is disabled, only the consumption of the LPVREG and RSM remain (almost no leakage currents) The RTC is running, clocked by a standard 32.768 kHz crystal. The RTC is running, clocked by the internal Low Power RC oscillator (LPOSC)
In SLOW-WFI mode:
In STOP mode:
In STANDBY mode:
STANDBY mode is only supported in the single supply scheme (see Figure 12)
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Subject to general operating conditions for VDD_IO, and TA Table 15.
Symbol
Single supply typical power consumption in Run, WFI, Slow and Slow-WFI modes
Para meter Conditions 3.3V 5V typ(1) typ(2) Unit
Clocked by OSC4M with PLL multiplication, all peripherals enabled in the MRCC_PLCKEN register: fHCLK=60 MHz, fPCLK=30 MHz fHCLK=56 MHz, fPCLK=28 MHz fHCLK=48 MHz, fPCLK=24 MHz fHCLK=32 MHz, fPCLK=32 MHz fHCLK=16 MHz, fPCLK=16 MHz Supply current in fHCLK=8 MHz, fPCLK=8 MHz RUN mode(4) Clocked by OSC4M with PLL multiplication, only EXTIT peripheral enabled in the MRCC_PLCKEN register: fHCLK=60 MHz, fPCLK=30 MHz fHCLK=56 MHz, fPCLK=28 MHz fHCLK=48 MHz, fPCLK=24 MHz fHCLK=32 MHz, fPCLK=32 MHz fHCLK=16 MHz, fPCLK=16 MHz fHCLK=8 MHz, fPCLK=8 MHz Clocked by OSC4M with PLL multiplication, only EXTIT peripheral enabled in the MRCC_PLCKEN register: fHCLK=60 MHz, fPCLK=30 MHz(5) Supply current in fHCLK=56 MHz, fPCLK=28 MHz(5) fHCLK=48 MHz, fPCLK=24 MHz(5) WFI mode(4) fHCLK=32 MHz, fPCLK=32 MHz(6) fHCLK=16 MHz, fPCLK= 16 MHz (6) fHCLK= 8 MHz, fPCLK= 8 MHz(6) Clocked by FREEOSC: fHCLK=fPCLK=~5 MHz, Supply current in Clocked by OSC4M: fHCLK=fPCLK=4 MHz Clocked by LPOSC: fHCLK=fPCLK=~300 kHz SLOW mode(4) Clocked by OSC32K: fHCLK=fPCLK=32.768 kHz Clocked by FREEOSC: fHCLK=fPCLK=~5 MHz Supply current in Clocked by OSC4M: fHCLK=fPCLK=4 MHz SLOW-WFI Clocked by LPOSC: fHCLK=fPCLK=~300 kHz (4)(7) mode Clocked by OSC32K: fHCLK=fPCLK=32.768 kHz
1. Typical data based on TA=25 C and VDD_IO=3.3V. 2. Typical data based on TA=25 C and VDD_IO=5.0V.
80 75 65 59 34 20
82 77 67 61 37 22
mA
65 60 54 42 22 16
67 62 55 44 24 18
mA
I D D (3)
62 59 53 22 13 10 9 8 3.65 3.5 3.5 3.1 1.15 0.98
63 60 54 23 15 11 10 9 3.9 4.2 4.0 3.75 1.65 1.5
mA
mA
mA
3. The conditions for these consumption measurements are described at the beginning of Section 5.3.4 on page 36. 4. Single supply scheme see Figure 14. 5. Parameter setting BURST=1, WFI_FLASHEN=1 6. Parameter setting BURST=0, WFI_FLASHEN=0 7. Parameter setting WFI_FLASHEN=0, OSC4MOFF=1
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 16.
Electrical parameters
Dual supply supply typical power consumption in Run, WFI, Slow and Slow-WFI modes
To calculate the power consumption in Dual supply mode, refer to the values given in Table 15. and consider that this consumption is split as follows: IDD(single supply)~IDD(dual supply)= IDD_V18 + IDD(VDD_IO) For 3.3V range: IDD(VDD_IO) ~ 1 to 2 mA For 5V range: IDD(VDD_IO) ~ 2 to 3 mA Therefore most of the consumption is sunk on the V18 power supply This formula does not apply in STOP and STANDBY modes, refer to Table 17.
Subject to general operating conditions for VDD_IO, and TA Table 17.
Symbol
Typical power consumption in STOP and STANDBY modes
Parameter Conditions LP_PARAM bits: ALL OFF(5) LP_PARAM bits : MVREG ON, OSC4M OFF, FLASH OFF(6) LP_PARAM bits: MVREG ON, OSC4M ON , FLASH OFF(6) LP_PARAM bits: MVREG ON, OSC4M OFF, FLASH ON (6) LP_PARAM bits: MVREG ON, OSC4M ON, FLASH ON
(6)
3.3V Typ(1) 12 130 1950 630 2435 5 <1 410 1475 550 <1 910 1475 11 14
5V Typ(2) 15 135 1930 635 2425 5 <1 410 1435 550 1 910 1445 14 18
Unit
Supply current in STOP mode(4)
A
IDD(3) Supply current in STOP mode(7)
LPPARAM bits: ALL OFF, with V18=1.8 V LP_PARAM bits: OSC4M ON, FLASH OFF LP_PARAM bits: OSC4M OFF, FLASH ON LP_PARAM bits: OSC4M ON, FLASH ON Supply current in STANDBY mode(4) RTC OFF RTC ON clocked by OSC32K
IDD_V18 IDD_V33 IDD_V18 IDD_V33 IDD_V18 IDD_V33 IDD_V18 IDD_V33
A
A
1. Typical data are based on TA=25C, VDD_IO=3.3 V and V18=1.8 V unless otherwise indicated in the table. 2. Typical data are based on TA=25C, VDD_IO=5.0 V and V18=1.8 V unless otherwise indicated in the table. 3. The conditions for these consumption measurements are described at the beginning of Section 5.3.4 on page 36. 4. Single supply scheme see Figure 12. 5. In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4 V, which significantly reduces the leakage currents. 6. In this mode, the whole digital circuitry is powered internally by the MVREG at 1.8 V. 7. Dual supply scheme see Figure 13.
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Supply and clock manager power consumption
Table 18.
Symbol
Supply and clock manager power consumption
Parameter Conditions(1) External components specified in: 4/8 MHz crystal / ceramic resonator oscillator (XT1/XT2) on page 46 3.3V Typ 1815 5V Typ 1795 Unit
Supply current of resonator oscillator IDD(OSC4M) in STOP or WFI mode (LP_PARAM bit: OSC4M ON) IDD(FLASH) FLASH static current consumption in STOP or WFI mode (LP_PARAM bit FLASH ON)
515
515
Main Voltage Regulator static current IDD(MVREG) consumption in STOP mode (LP_PARAM bit: MVREG ON) STOP mode includes leakage where V18 is internally set to 1.4 V STANDBY mode where V18BKP and V18 are internally set to 1.4 V and 0 V respectively
130
135
A
12
15
Low Power Voltage Regulator + RSM IDD(LPVREG) current static current consumption
11
14
1. Measurements performed in 3.3V single supply mode see Figure 12
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Electrical parameters
On-Chip peripheral power consumption
Conditions: VDD_IO=VDDA_ADC=VDDA_PLL=3.3 V or 5 V 10% unless otherwise specified. TA= 25 C Clocked by OSC4M with PLL multiplication, fCK_SYS=64 MHz, fHCLK=32 MHz, fPCLK=32 MHz On-Chip peripherals
Parameter TIM Timer supply current (1) PWM Timer supply SSP supply current current(2)
(3)
Table 19.
Symbol IDD(TIM) IDD(PWM) IDD(SSP) IDD(UART) IDD(I2C) IDD(ADC) IDD(USB) IDD(CAN)
.
Typ (3.3V and 5.0V) 0.7 1 1.3 1.6 0.3 1.2 0.90 2.8
Unit
UART supply current (4) I2C supply current
(5)
mA
ADC supply current when converting (6) USB supply current Note: VDD_IO must be 3.3 V 10% CAN supply current (8)
(7)
1. Data based on a differential IDD measurement between reset configuration and timer counter running at 32 MHz. No IC/OC programmed (no I/O pads toggling) 2. Data based on a differential IDD measurement between reset configuration and PWM running at 32 MHz. This measurement does not include PWM pads toggling consumption. 3. Data based on a differential IDD measurement between reset configuration and permanent SPI master communication at maximum speed 16 MHz. The data sent is 55h. This measurement does not include the pad toggling consumption. 4. Data based on a differential IDD measurement between reset configuration and a permanent UART data transmit sequence at 1Mbauds. This measurement does not include the pad toggling consumption. 5. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent I2C master communication at 100kHz (data sent equal to 55h). This measurement includes the pad toggling consumption but not the external 10kOhm external pull-up on clock and data lines. 6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions at 8 MHz in scan mode on 16 inputs configured as AIN. 7. Data based on a differential IDD measurement between reset configuration and a running generic HID application. 8. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data transmit sequence in loopback mode at 1MHz. This measurement does not include the pad toggling consumption.
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Electrical parameters
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5.3.5
Clock and timing characteristics
XT1 external clock source
Subject to general operating conditions for VDD_IO, and TA. Table 20.
Symbol fXT1 VXT1H VXT1L tw(XT1H) tw(XT1L) tr(XT1) tf(XT1) IL CIN(XT1)
XT1 external clock source
Parameter External clock source frequency XT1 input pin high level voltage XT1 input pin low level voltage XT1 high or low time (3) XT1 rise or fall time (3) VSS VIN VDD_IO 5 45 55 see Figure 20 0.7xVDD_IO VSS 6 ns 20 1 A pF % Conditions(1) (2) Min Typ 4 Max 60 VDD_IO V 0.3xVDD_IO Unit MHz
XTx Input leakage current XT1 input capacitance(3)
DuCy(XT1) Duty cycle
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production.
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Electrical parameters
XRTC1 external clock source
Subject to general operating conditions for VDD_IO, and TA. Table 21.
Symbol fXRTC1 VXRTC1H VXRTC1L
XRTC1 external clock source
Parameter External clock source frequency XRTC1 input pin high level voltage XRTC1 input pin low level voltage see Figure 20 0.7xVDD_IO VSS 900 ns 50 VSSVINVDD_I
O
Conditions(1)
Min
Typ 32.768
Max 500 VDD_IO
Unit kHz
V 0.3xVDD_IO
tw(XRTC1H) XRTC1 high or low tw(XRTC1L) time(2) tr(XRTC1) tf(XRTC1) IL CIN(RTC1) XRTC1 rise or fall time(2)
XRTCx Input leakage current XRTC1 input capacitance(2)
1 5 30 70
A pF %
DuCy(RTC1) Duty cycle
1. Data based on typical application software.
2. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 20. Typical application with an external clock source
90% VXT1H 10%
VXT1L tr(XT1) tf(XT1) tw(XT1H) tw(XT1L)
TXT1
XT2 EXTERNAL CLOCK SOURCE hi-Z XT1 IL
fOSC4M
STR750
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Electrical parameters
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4/8 MHz crystal / ceramic resonator oscillator (XT1/XT2)
The STR750 system clock or the input of the PLL can be supplied by a OSC4M which is a 4 MHz clock generated from a 4 MHz or 8 MHz crystal or ceramic resonator. If using an 8 MHz oscillator, software set the XTDIV bit to enable a divider by 2 and generate a 4 MHz OSC4M clock. All the information given in this paragraph are based on product characterisation with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). Table 22.
Symbol
4/8 MHz crystal / ceramic resonator oscillator (XT1/XT2)(1)
Parameter Conditions 4 MHz Crystal/Resonator Oscillator connected on XT1/XT2 XTDIV=0 or 8 MHz Crystal/Resonator Oscillator connected on XT1/XT2 XTDIV=1 200 Min Typ Max Unit
fOSC4M
Oscillator frequency
4
MHz
RF CL1(2) CL2 i2
Feedback resistor Recommended load capacitance versus equivalent RS=200 serial resistance of the crystal or (3) ceramic resonator (RS) XT2 driving current VDD_IO=3.3 V or 5.0 V
240
270
k
60
pF
425 1
A ms
tSU(OSC4M)(4) Star tup time at VDD_IO power-up
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5-pF to 25-pF range (typ.) designed for high-frequency applications and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance). 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(OSC4M) is the typical start-up time measured from the moment VDD_IO is powered (with a quick VDD_IO ramp-up from 0 to 3.3V (<50s) to a stabilized 4MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal/ceramic resonator manufacturer.
Figure 21. Typical application with a 4 or 8 MHz crystal or ceramic resonator
XTDIV
WHEN RESONATOR WITH INTEGRATED CAPACITORS CL1 XT1
LINEAR AMPLIFIER
/2
FEEDBACK LOOP
fOSC4M
RESONATOR
RF
CL2 XT2
VDD/2 Ref
i2
STR75X
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Electrical parameters
OSC32K crystal / ceramic resonator oscillator
The STR7 RTC clock can be supplied with a 32.768 kHz Crystal/Ceramic resonator oscillator. All the information given in this paragraph are based on product characterisation with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). Table 23.
Symbol fOSC32K RF CL1 CL2 i2
OSC32K crystal / ceramic resonator oscillator
Parameter Oscillator Frequency Feedback resistor VDD_IO=3.3 V or 5.0 V 270 Conditions Min Typ 32.768 310 12.5 370 15 Max Unit kHz k pF
Recommended load capacitance RS=40K versus equivalent serial resistance of the crystal or ceramic resonator (RS)(1) XT2 driving current VDD_IO=3.3 V or 5.0 V VIN=VSS VDD_IO is stabilized 1
5 2.5
A s
tSU(OSC32K)(2) Star tup time
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Refer to crystal/ceramic resonator manufacturer for more details 2. tSU(OSC32K) is the start-up time measured from the moment it is enabled (by software) to a stabilized 32 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal/ceramic resonator manufacturer
Figure 22. Typical application with a 32.768 kHz crystal or ceramic resonator
WHEN RESONATOR WITH INTEGRATED CAPACITORS
i2
FEEDBACK LOOP
CL1
XRTC1
fOSC32K
CL2
32 kHz RESONATOR XRTC2
RF STR750
PLL characteristics
PLL Jitter Terminology
Self-referred single period jitter (period jitter) Period Jitter is defined as the difference of the maximum period (Tmax) and minimum period (Tmin) at the output of the PLL where Tmax is the maximum time difference between 2 consecutive clock rising edges and Tmin is the minimum time difference between 2 consecutive clock rising edges. See Figure 23
Self-referred long term jitter (N period jitter) Self-referred long term Jitter is defined as the difference of the maximum period (Tmax) and minimum period (Tmin) at the output of the PLL where Tmax is the maximum time
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Electrical parameters
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difference between N+1 consecutive clock rising edges and Tmin is the minimum time difference between N+1 consecutive clock rising edges. N should be kept sufficiently large to have a long term jitter (ex: thousands). For N=1, this becomes the single period jitter. See Figure 23
Cycle-to-cycle jitter (N period jitter) This corresponds to the time variation between adjacent cycles over a random sample of adjacent clock cycles pairs. Jitter(cycle-to-cycle) = Max(Tcycle n- Tcycle n-1) for n=1 to N. See Figure 24
Figure 23. Self-referred jitter (single and long term)
n IDEAL CK_PLL T n+1 --n+N
ACTUAL CK_PLL single period jitter
trigger point
long term jitter
Figure 24. Cycle-to-cycle jitter
n IDEAL CK_PLL T n+1 n+2 --n+N
ACTUAL CK_PLL
Tcycle 1
Tcycle 2
Tcycle N-1
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Electrical parameters
PLL characteristics
Subject to general operating conditions for VDD_IO, and TA. Table 24.
Symbol
PLL characteristics
Value Parameter PLL input clock Test Conditions Min Typ 4.0 40 fPLL_INx 24 When PLL operates (locked) 336 60 165 960 300 fPLL_IN = 4 MHz(4) VDD_IO is stable fPLL_IN = 4 MHz(4) VDD_IO is stable +/-250 +/-2.5 +/-500 Max(1) Unit MHz % MH z MHz s ps ns ps
fPLL_IN fPLL_OUT fVCO tLOCK tJITTER1(2)(3) tJITTER2(2)(3) tJITTER3(2)(3)
PLL input clock duty cycle PLL multiplier output clock VCO frequency range PLL lock time Single period jitter (+/-3 peak to peak) Long term jitter (+/-3 peak to peak)
Cycle to cycle jitter (+/-3 peak fPLL_IN = 4 MHz(4) VDD_IO is stable to peak)
1. Data based on product characterisation, not tested in production. 2. Refer to jitter terminology in : PLL characteristics on page 47 for details on how jitter is specified. 3. The jitter specification holds true only up to 50mV (peak-to-peak) noise on VDDA_PLL and V18 supplies. Jitter will increase if the noise is more than 50mV. In addition, it assumes that the input clock has no jitter. 4. The PLL parameters (MX1, MX0, PRESC1, PRESC2) must respect the constraints described in: PLL characteristics on page 47.
Internal RC oscillators (FREEOSC & LPOSC)
Subject to general operating conditions for VDD_IO, and TA. Table 25.
Symbol fCK_FREEOSC fCK_LPOSC
Internal RC oscillators (FREEOSC & LPOSC)
Parameter FREEOSC Oscillator Frequency LPOSC Oscillator Frequency Conditions Mi n 3 150 Typ 5 300 Max 8 500 Unit MHz kHz
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Electrical parameters
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5.3.6
Memory characteristics
Flash memory
Subject to general operating conditions for VDD_IO and V18, TA = -40 to 105 C unless otherwise specified. Table 26.
Symbol tPW tPDW tPB0 tPB1 tES tES tES tES tRPD tPSL tESL
Flash memory characteristics
Value Parameter Word Program Double Word Program Bank 0 Program (256K) Bank 1 Program (16K) Sector Erase (64K) Sector Erase (8K) Bank 0 Erase (256K) Bank 1 Erase (16K) Recover y when disabled Program Suspend Latency Erase Suspend Latency Single Word programming of a checker-board pattern Single Word programming of a checker-board pattern Not preprogrammed (all 1) Preprogrammed (all 0) Not preprogrammed (all 1) Preprogrammed (all 0) Not preprogrammed (all 1) Preprogrammed (all 0) Not preprogrammed (all 1) Preprogrammed (all 0) Test Conditions Typ 35 60 2 125 1.54 1.176 392 343 8.0 6.6 0.9 0.8 4.9(2) 224(2) 2.94(2) 2.38(2) 560(2) 532(2) 13.7 11.2 1.5 1.3 20 10 300 Max(1) Unit s s s ms s ms s s s s s
1. Data based on characterisation not tested in production 2. 10K program/erase cycles.
Table 27.
Symbol
Flash memory endurance and data retention
Value Parameter Conditions Min(1) 10 100 TA=85 C Min time from Erase Resume to next Erase Suspend 20 20 Unit Typ Max kcycles kcycles Years ms
NEND_B0 Endurance (Bank 0 sectors) NEND_B1 Endurance (Bank 1 sectors) YRET tESR Data Retention Erase Suspend Rate
1. Data based on characterisation not tested in production.
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Electrical parameters
5.3.7
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electro magnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as:
Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 28.
Symbol
EMC characteristics
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Conditions VDD_IO=3.3 V or 5 V, TA=+25 C, fCK_SYS=32 MHz conforms to IEC 1000-4-2 Level/ Class Class A
VFESD
VEFTB
Fast transient voltage burst limits to be applied VDD_IO=3.3 V or 5 V, through 100pF on VDD and VSS pins to induce TA=+25 C, fCK_SYS=32 MHz a functional disturbance conforms to IEC 1000-4-4
Class A
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Electrical paramete |
